efm32g230_pac/usart2/
status.rs

1#[doc = "Register `STATUS` reader"]
2pub struct R(crate::R<STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RXENS` reader - Receiver Enable Status"]
17pub type RXENS_R = crate::BitReader<bool>;
18#[doc = "Field `TXENS` reader - Transmitter Enable Status"]
19pub type TXENS_R = crate::BitReader<bool>;
20#[doc = "Field `MASTER` reader - SPI Master Mode"]
21pub type MASTER_R = crate::BitReader<bool>;
22#[doc = "Field `RXBLOCK` reader - Block Incoming Data"]
23pub type RXBLOCK_R = crate::BitReader<bool>;
24#[doc = "Field `TXTRI` reader - Transmitter Tristated"]
25pub type TXTRI_R = crate::BitReader<bool>;
26#[doc = "Field `TXC` reader - TX Complete"]
27pub type TXC_R = crate::BitReader<bool>;
28#[doc = "Field `TXBL` reader - TX Buffer Level"]
29pub type TXBL_R = crate::BitReader<bool>;
30#[doc = "Field `RXDATAV` reader - RX Data Valid"]
31pub type RXDATAV_R = crate::BitReader<bool>;
32#[doc = "Field `RXFULL` reader - RX FIFO Full"]
33pub type RXFULL_R = crate::BitReader<bool>;
34impl R {
35    #[doc = "Bit 0 - Receiver Enable Status"]
36    #[inline(always)]
37    pub fn rxens(&self) -> RXENS_R {
38        RXENS_R::new((self.bits & 1) != 0)
39    }
40    #[doc = "Bit 1 - Transmitter Enable Status"]
41    #[inline(always)]
42    pub fn txens(&self) -> TXENS_R {
43        TXENS_R::new(((self.bits >> 1) & 1) != 0)
44    }
45    #[doc = "Bit 2 - SPI Master Mode"]
46    #[inline(always)]
47    pub fn master(&self) -> MASTER_R {
48        MASTER_R::new(((self.bits >> 2) & 1) != 0)
49    }
50    #[doc = "Bit 3 - Block Incoming Data"]
51    #[inline(always)]
52    pub fn rxblock(&self) -> RXBLOCK_R {
53        RXBLOCK_R::new(((self.bits >> 3) & 1) != 0)
54    }
55    #[doc = "Bit 4 - Transmitter Tristated"]
56    #[inline(always)]
57    pub fn txtri(&self) -> TXTRI_R {
58        TXTRI_R::new(((self.bits >> 4) & 1) != 0)
59    }
60    #[doc = "Bit 5 - TX Complete"]
61    #[inline(always)]
62    pub fn txc(&self) -> TXC_R {
63        TXC_R::new(((self.bits >> 5) & 1) != 0)
64    }
65    #[doc = "Bit 6 - TX Buffer Level"]
66    #[inline(always)]
67    pub fn txbl(&self) -> TXBL_R {
68        TXBL_R::new(((self.bits >> 6) & 1) != 0)
69    }
70    #[doc = "Bit 7 - RX Data Valid"]
71    #[inline(always)]
72    pub fn rxdatav(&self) -> RXDATAV_R {
73        RXDATAV_R::new(((self.bits >> 7) & 1) != 0)
74    }
75    #[doc = "Bit 8 - RX FIFO Full"]
76    #[inline(always)]
77    pub fn rxfull(&self) -> RXFULL_R {
78        RXFULL_R::new(((self.bits >> 8) & 1) != 0)
79    }
80}
81#[doc = "USART Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
82pub struct STATUS_SPEC;
83impl crate::RegisterSpec for STATUS_SPEC {
84    type Ux = u32;
85}
86#[doc = "`read()` method returns [status::R](R) reader structure"]
87impl crate::Readable for STATUS_SPEC {
88    type Reader = R;
89}
90#[doc = "`reset()` method sets STATUS to value 0x40"]
91impl crate::Resettable for STATUS_SPEC {
92    #[inline(always)]
93    fn reset_value() -> Self::Ux {
94        0x40
95    }
96}
efm32g230_pac/usart2/status.rs

efm32g230_pac/usart2/
status.rs
