efm32g230_pac/usart2/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SYNC` reader - USART Synchronous Mode"]
38pub type SYNC_R = crate::BitReader<bool>;
39#[doc = "Field `SYNC` writer - USART Synchronous Mode"]
40pub type SYNC_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `LOOPBK` reader - Loopback Enable"]
42pub type LOOPBK_R = crate::BitReader<bool>;
43#[doc = "Field `LOOPBK` writer - Loopback Enable"]
44pub type LOOPBK_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 1>;
45#[doc = "Field `CCEN` reader - Collision Check Enable"]
46pub type CCEN_R = crate::BitReader<bool>;
47#[doc = "Field `CCEN` writer - Collision Check Enable"]
48pub type CCEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
49#[doc = "Field `MPM` reader - Multi-Processor Mode"]
50pub type MPM_R = crate::BitReader<bool>;
51#[doc = "Field `MPM` writer - Multi-Processor Mode"]
52pub type MPM_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
53#[doc = "Field `MPAB` reader - Multi-Processor Address-Bit"]
54pub type MPAB_R = crate::BitReader<bool>;
55#[doc = "Field `MPAB` writer - Multi-Processor Address-Bit"]
56pub type MPAB_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
57#[doc = "Oversampling\n\nValue on reset: 0"]
58#[derive(Clone, Copy, Debug, PartialEq)]
59#[repr(u8)]
60pub enum OVS_A {
61    #[doc = "0: Regular UART mode with 16X oversampling in asynchronous mode"]
62    X16 = 0,
63    #[doc = "1: Double speed with 8X oversampling in asynchronous mode"]
64    X8 = 1,
65    #[doc = "2: 6X oversampling in asynchronous mode"]
66    X6 = 2,
67    #[doc = "3: Quadruple speed with 4X oversampling in asynchronous mode"]
68    X4 = 3,
69}
70impl From<OVS_A> for u8 {
71    #[inline(always)]
72    fn from(variant: OVS_A) -> Self {
73        variant as _
74    }
75}
76#[doc = "Field `OVS` reader - Oversampling"]
77pub type OVS_R = crate::FieldReader<u8, OVS_A>;
78impl OVS_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub fn variant(&self) -> OVS_A {
82        match self.bits {
83            0 => OVS_A::X16,
84            1 => OVS_A::X8,
85            2 => OVS_A::X6,
86            3 => OVS_A::X4,
87            _ => unreachable!(),
88        }
89    }
90    #[doc = "Checks if the value of the field is `X16`"]
91    #[inline(always)]
92    pub fn is_x16(&self) -> bool {
93        *self == OVS_A::X16
94    }
95    #[doc = "Checks if the value of the field is `X8`"]
96    #[inline(always)]
97    pub fn is_x8(&self) -> bool {
98        *self == OVS_A::X8
99    }
100    #[doc = "Checks if the value of the field is `X6`"]
101    #[inline(always)]
102    pub fn is_x6(&self) -> bool {
103        *self == OVS_A::X6
104    }
105    #[doc = "Checks if the value of the field is `X4`"]
106    #[inline(always)]
107    pub fn is_x4(&self) -> bool {
108        *self == OVS_A::X4
109    }
110}
111#[doc = "Field `OVS` writer - Oversampling"]
112pub type OVS_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, OVS_A, 2, 5>;
113impl<'a> OVS_W<'a> {
114    #[doc = "Regular UART mode with 16X oversampling in asynchronous mode"]
115    #[inline(always)]
116    pub fn x16(self) -> &'a mut W {
117        self.variant(OVS_A::X16)
118    }
119    #[doc = "Double speed with 8X oversampling in asynchronous mode"]
120    #[inline(always)]
121    pub fn x8(self) -> &'a mut W {
122        self.variant(OVS_A::X8)
123    }
124    #[doc = "6X oversampling in asynchronous mode"]
125    #[inline(always)]
126    pub fn x6(self) -> &'a mut W {
127        self.variant(OVS_A::X6)
128    }
129    #[doc = "Quadruple speed with 4X oversampling in asynchronous mode"]
130    #[inline(always)]
131    pub fn x4(self) -> &'a mut W {
132        self.variant(OVS_A::X4)
133    }
134}
135#[doc = "Field `CLKPOL` reader - Clock Polarity"]
136pub type CLKPOL_R = crate::BitReader<bool>;
137#[doc = "Field `CLKPOL` writer - Clock Polarity"]
138pub type CLKPOL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 8>;
139#[doc = "Field `CLKPHA` reader - Clock Edge For Setup/Sample"]
140pub type CLKPHA_R = crate::BitReader<bool>;
141#[doc = "Field `CLKPHA` writer - Clock Edge For Setup/Sample"]
142pub type CLKPHA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 9>;
143#[doc = "Field `MSBF` reader - Most Significant Bit First"]
144pub type MSBF_R = crate::BitReader<bool>;
145#[doc = "Field `MSBF` writer - Most Significant Bit First"]
146pub type MSBF_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 10>;
147#[doc = "Field `CSMA` reader - Action On Slave-Select In Master Mode"]
148pub type CSMA_R = crate::BitReader<bool>;
149#[doc = "Field `CSMA` writer - Action On Slave-Select In Master Mode"]
150pub type CSMA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 11>;
151#[doc = "Field `TXBIL` reader - TX Buffer Interrupt Level"]
152pub type TXBIL_R = crate::BitReader<bool>;
153#[doc = "Field `TXBIL` writer - TX Buffer Interrupt Level"]
154pub type TXBIL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 12>;
155#[doc = "Field `RXINV` reader - Receiver Input Invert"]
156pub type RXINV_R = crate::BitReader<bool>;
157#[doc = "Field `RXINV` writer - Receiver Input Invert"]
158pub type RXINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 13>;
159#[doc = "Field `TXINV` reader - Transmitter output Invert"]
160pub type TXINV_R = crate::BitReader<bool>;
161#[doc = "Field `TXINV` writer - Transmitter output Invert"]
162pub type TXINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 14>;
163#[doc = "Field `CSINV` reader - Chip Select Invert"]
164pub type CSINV_R = crate::BitReader<bool>;
165#[doc = "Field `CSINV` writer - Chip Select Invert"]
166pub type CSINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 15>;
167#[doc = "Field `AUTOCS` reader - Automatic Chip Select"]
168pub type AUTOCS_R = crate::BitReader<bool>;
169#[doc = "Field `AUTOCS` writer - Automatic Chip Select"]
170pub type AUTOCS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 16>;
171#[doc = "Field `AUTOTRI` reader - Automatic TX Tristate"]
172pub type AUTOTRI_R = crate::BitReader<bool>;
173#[doc = "Field `AUTOTRI` writer - Automatic TX Tristate"]
174pub type AUTOTRI_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 17>;
175#[doc = "Field `SCMODE` reader - SmartCard Mode"]
176pub type SCMODE_R = crate::BitReader<bool>;
177#[doc = "Field `SCMODE` writer - SmartCard Mode"]
178pub type SCMODE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 18>;
179#[doc = "Field `SCRETRANS` reader - SmartCard Retransmit"]
180pub type SCRETRANS_R = crate::BitReader<bool>;
181#[doc = "Field `SCRETRANS` writer - SmartCard Retransmit"]
182pub type SCRETRANS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 19>;
183#[doc = "Field `SKIPPERRF` reader - Skip Parity Error Frames"]
184pub type SKIPPERRF_R = crate::BitReader<bool>;
185#[doc = "Field `SKIPPERRF` writer - Skip Parity Error Frames"]
186pub type SKIPPERRF_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 20>;
187#[doc = "Field `BIT8DV` reader - Bit 8 Default Value"]
188pub type BIT8DV_R = crate::BitReader<bool>;
189#[doc = "Field `BIT8DV` writer - Bit 8 Default Value"]
190pub type BIT8DV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 21>;
191#[doc = "Field `ERRSDMA` reader - Halt DMA On Error"]
192pub type ERRSDMA_R = crate::BitReader<bool>;
193#[doc = "Field `ERRSDMA` writer - Halt DMA On Error"]
194pub type ERRSDMA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 22>;
195#[doc = "Field `ERRSRX` reader - Disable RX On Error"]
196pub type ERRSRX_R = crate::BitReader<bool>;
197#[doc = "Field `ERRSRX` writer - Disable RX On Error"]
198pub type ERRSRX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 23>;
199#[doc = "Field `ERRSTX` reader - Disable TX On Error"]
200pub type ERRSTX_R = crate::BitReader<bool>;
201#[doc = "Field `ERRSTX` writer - Disable TX On Error"]
202pub type ERRSTX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 24>;
203#[doc = "TX Delay Transmission\n\nValue on reset: 0"]
204#[derive(Clone, Copy, Debug, PartialEq)]
205#[repr(u8)]
206pub enum TXDELAY_A {
207    #[doc = "0: Frames are transmitted immediately"]
208    NONE = 0,
209    #[doc = "1: Transmission of new frames are delayed by a single baud period"]
210    SINGLE = 1,
211    #[doc = "2: Transmission of new frames are delayed by two baud periods"]
212    DOUBLE = 2,
213    #[doc = "3: Transmission of new frames are delayed by three baud periods"]
214    TRIPLE = 3,
215}
216impl From<TXDELAY_A> for u8 {
217    #[inline(always)]
218    fn from(variant: TXDELAY_A) -> Self {
219        variant as _
220    }
221}
222#[doc = "Field `TXDELAY` reader - TX Delay Transmission"]
223pub type TXDELAY_R = crate::FieldReader<u8, TXDELAY_A>;
224impl TXDELAY_R {
225    #[doc = "Get enumerated values variant"]
226    #[inline(always)]
227    pub fn variant(&self) -> TXDELAY_A {
228        match self.bits {
229            0 => TXDELAY_A::NONE,
230            1 => TXDELAY_A::SINGLE,
231            2 => TXDELAY_A::DOUBLE,
232            3 => TXDELAY_A::TRIPLE,
233            _ => unreachable!(),
234        }
235    }
236    #[doc = "Checks if the value of the field is `NONE`"]
237    #[inline(always)]
238    pub fn is_none(&self) -> bool {
239        *self == TXDELAY_A::NONE
240    }
241    #[doc = "Checks if the value of the field is `SINGLE`"]
242    #[inline(always)]
243    pub fn is_single(&self) -> bool {
244        *self == TXDELAY_A::SINGLE
245    }
246    #[doc = "Checks if the value of the field is `DOUBLE`"]
247    #[inline(always)]
248    pub fn is_double(&self) -> bool {
249        *self == TXDELAY_A::DOUBLE
250    }
251    #[doc = "Checks if the value of the field is `TRIPLE`"]
252    #[inline(always)]
253    pub fn is_triple(&self) -> bool {
254        *self == TXDELAY_A::TRIPLE
255    }
256}
257#[doc = "Field `TXDELAY` writer - TX Delay Transmission"]
258pub type TXDELAY_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, TXDELAY_A, 2, 26>;
259impl<'a> TXDELAY_W<'a> {
260    #[doc = "Frames are transmitted immediately"]
261    #[inline(always)]
262    pub fn none(self) -> &'a mut W {
263        self.variant(TXDELAY_A::NONE)
264    }
265    #[doc = "Transmission of new frames are delayed by a single baud period"]
266    #[inline(always)]
267    pub fn single(self) -> &'a mut W {
268        self.variant(TXDELAY_A::SINGLE)
269    }
270    #[doc = "Transmission of new frames are delayed by two baud periods"]
271    #[inline(always)]
272    pub fn double(self) -> &'a mut W {
273        self.variant(TXDELAY_A::DOUBLE)
274    }
275    #[doc = "Transmission of new frames are delayed by three baud periods"]
276    #[inline(always)]
277    pub fn triple(self) -> &'a mut W {
278        self.variant(TXDELAY_A::TRIPLE)
279    }
280}
281#[doc = "Field `BYTESWAP` reader - Byteswap In Double Accesses"]
282pub type BYTESWAP_R = crate::BitReader<bool>;
283#[doc = "Field `BYTESWAP` writer - Byteswap In Double Accesses"]
284pub type BYTESWAP_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 28>;
285impl R {
286    #[doc = "Bit 0 - USART Synchronous Mode"]
287    #[inline(always)]
288    pub fn sync(&self) -> SYNC_R {
289        SYNC_R::new((self.bits & 1) != 0)
290    }
291    #[doc = "Bit 1 - Loopback Enable"]
292    #[inline(always)]
293    pub fn loopbk(&self) -> LOOPBK_R {
294        LOOPBK_R::new(((self.bits >> 1) & 1) != 0)
295    }
296    #[doc = "Bit 2 - Collision Check Enable"]
297    #[inline(always)]
298    pub fn ccen(&self) -> CCEN_R {
299        CCEN_R::new(((self.bits >> 2) & 1) != 0)
300    }
301    #[doc = "Bit 3 - Multi-Processor Mode"]
302    #[inline(always)]
303    pub fn mpm(&self) -> MPM_R {
304        MPM_R::new(((self.bits >> 3) & 1) != 0)
305    }
306    #[doc = "Bit 4 - Multi-Processor Address-Bit"]
307    #[inline(always)]
308    pub fn mpab(&self) -> MPAB_R {
309        MPAB_R::new(((self.bits >> 4) & 1) != 0)
310    }
311    #[doc = "Bits 5:6 - Oversampling"]
312    #[inline(always)]
313    pub fn ovs(&self) -> OVS_R {
314        OVS_R::new(((self.bits >> 5) & 3) as u8)
315    }
316    #[doc = "Bit 8 - Clock Polarity"]
317    #[inline(always)]
318    pub fn clkpol(&self) -> CLKPOL_R {
319        CLKPOL_R::new(((self.bits >> 8) & 1) != 0)
320    }
321    #[doc = "Bit 9 - Clock Edge For Setup/Sample"]
322    #[inline(always)]
323    pub fn clkpha(&self) -> CLKPHA_R {
324        CLKPHA_R::new(((self.bits >> 9) & 1) != 0)
325    }
326    #[doc = "Bit 10 - Most Significant Bit First"]
327    #[inline(always)]
328    pub fn msbf(&self) -> MSBF_R {
329        MSBF_R::new(((self.bits >> 10) & 1) != 0)
330    }
331    #[doc = "Bit 11 - Action On Slave-Select In Master Mode"]
332    #[inline(always)]
333    pub fn csma(&self) -> CSMA_R {
334        CSMA_R::new(((self.bits >> 11) & 1) != 0)
335    }
336    #[doc = "Bit 12 - TX Buffer Interrupt Level"]
337    #[inline(always)]
338    pub fn txbil(&self) -> TXBIL_R {
339        TXBIL_R::new(((self.bits >> 12) & 1) != 0)
340    }
341    #[doc = "Bit 13 - Receiver Input Invert"]
342    #[inline(always)]
343    pub fn rxinv(&self) -> RXINV_R {
344        RXINV_R::new(((self.bits >> 13) & 1) != 0)
345    }
346    #[doc = "Bit 14 - Transmitter output Invert"]
347    #[inline(always)]
348    pub fn txinv(&self) -> TXINV_R {
349        TXINV_R::new(((self.bits >> 14) & 1) != 0)
350    }
351    #[doc = "Bit 15 - Chip Select Invert"]
352    #[inline(always)]
353    pub fn csinv(&self) -> CSINV_R {
354        CSINV_R::new(((self.bits >> 15) & 1) != 0)
355    }
356    #[doc = "Bit 16 - Automatic Chip Select"]
357    #[inline(always)]
358    pub fn autocs(&self) -> AUTOCS_R {
359        AUTOCS_R::new(((self.bits >> 16) & 1) != 0)
360    }
361    #[doc = "Bit 17 - Automatic TX Tristate"]
362    #[inline(always)]
363    pub fn autotri(&self) -> AUTOTRI_R {
364        AUTOTRI_R::new(((self.bits >> 17) & 1) != 0)
365    }
366    #[doc = "Bit 18 - SmartCard Mode"]
367    #[inline(always)]
368    pub fn scmode(&self) -> SCMODE_R {
369        SCMODE_R::new(((self.bits >> 18) & 1) != 0)
370    }
371    #[doc = "Bit 19 - SmartCard Retransmit"]
372    #[inline(always)]
373    pub fn scretrans(&self) -> SCRETRANS_R {
374        SCRETRANS_R::new(((self.bits >> 19) & 1) != 0)
375    }
376    #[doc = "Bit 20 - Skip Parity Error Frames"]
377    #[inline(always)]
378    pub fn skipperrf(&self) -> SKIPPERRF_R {
379        SKIPPERRF_R::new(((self.bits >> 20) & 1) != 0)
380    }
381    #[doc = "Bit 21 - Bit 8 Default Value"]
382    #[inline(always)]
383    pub fn bit8dv(&self) -> BIT8DV_R {
384        BIT8DV_R::new(((self.bits >> 21) & 1) != 0)
385    }
386    #[doc = "Bit 22 - Halt DMA On Error"]
387    #[inline(always)]
388    pub fn errsdma(&self) -> ERRSDMA_R {
389        ERRSDMA_R::new(((self.bits >> 22) & 1) != 0)
390    }
391    #[doc = "Bit 23 - Disable RX On Error"]
392    #[inline(always)]
393    pub fn errsrx(&self) -> ERRSRX_R {
394        ERRSRX_R::new(((self.bits >> 23) & 1) != 0)
395    }
396    #[doc = "Bit 24 - Disable TX On Error"]
397    #[inline(always)]
398    pub fn errstx(&self) -> ERRSTX_R {
399        ERRSTX_R::new(((self.bits >> 24) & 1) != 0)
400    }
401    #[doc = "Bits 26:27 - TX Delay Transmission"]
402    #[inline(always)]
403    pub fn txdelay(&self) -> TXDELAY_R {
404        TXDELAY_R::new(((self.bits >> 26) & 3) as u8)
405    }
406    #[doc = "Bit 28 - Byteswap In Double Accesses"]
407    #[inline(always)]
408    pub fn byteswap(&self) -> BYTESWAP_R {
409        BYTESWAP_R::new(((self.bits >> 28) & 1) != 0)
410    }
411}
412impl W {
413    #[doc = "Bit 0 - USART Synchronous Mode"]
414    #[inline(always)]
415    pub fn sync(&mut self) -> SYNC_W {
416        SYNC_W::new(self)
417    }
418    #[doc = "Bit 1 - Loopback Enable"]
419    #[inline(always)]
420    pub fn loopbk(&mut self) -> LOOPBK_W {
421        LOOPBK_W::new(self)
422    }
423    #[doc = "Bit 2 - Collision Check Enable"]
424    #[inline(always)]
425    pub fn ccen(&mut self) -> CCEN_W {
426        CCEN_W::new(self)
427    }
428    #[doc = "Bit 3 - Multi-Processor Mode"]
429    #[inline(always)]
430    pub fn mpm(&mut self) -> MPM_W {
431        MPM_W::new(self)
432    }
433    #[doc = "Bit 4 - Multi-Processor Address-Bit"]
434    #[inline(always)]
435    pub fn mpab(&mut self) -> MPAB_W {
436        MPAB_W::new(self)
437    }
438    #[doc = "Bits 5:6 - Oversampling"]
439    #[inline(always)]
440    pub fn ovs(&mut self) -> OVS_W {
441        OVS_W::new(self)
442    }
443    #[doc = "Bit 8 - Clock Polarity"]
444    #[inline(always)]
445    pub fn clkpol(&mut self) -> CLKPOL_W {
446        CLKPOL_W::new(self)
447    }
448    #[doc = "Bit 9 - Clock Edge For Setup/Sample"]
449    #[inline(always)]
450    pub fn clkpha(&mut self) -> CLKPHA_W {
451        CLKPHA_W::new(self)
452    }
453    #[doc = "Bit 10 - Most Significant Bit First"]
454    #[inline(always)]
455    pub fn msbf(&mut self) -> MSBF_W {
456        MSBF_W::new(self)
457    }
458    #[doc = "Bit 11 - Action On Slave-Select In Master Mode"]
459    #[inline(always)]
460    pub fn csma(&mut self) -> CSMA_W {
461        CSMA_W::new(self)
462    }
463    #[doc = "Bit 12 - TX Buffer Interrupt Level"]
464    #[inline(always)]
465    pub fn txbil(&mut self) -> TXBIL_W {
466        TXBIL_W::new(self)
467    }
468    #[doc = "Bit 13 - Receiver Input Invert"]
469    #[inline(always)]
470    pub fn rxinv(&mut self) -> RXINV_W {
471        RXINV_W::new(self)
472    }
473    #[doc = "Bit 14 - Transmitter output Invert"]
474    #[inline(always)]
475    pub fn txinv(&mut self) -> TXINV_W {
476        TXINV_W::new(self)
477    }
478    #[doc = "Bit 15 - Chip Select Invert"]
479    #[inline(always)]
480    pub fn csinv(&mut self) -> CSINV_W {
481        CSINV_W::new(self)
482    }
483    #[doc = "Bit 16 - Automatic Chip Select"]
484    #[inline(always)]
485    pub fn autocs(&mut self) -> AUTOCS_W {
486        AUTOCS_W::new(self)
487    }
488    #[doc = "Bit 17 - Automatic TX Tristate"]
489    #[inline(always)]
490    pub fn autotri(&mut self) -> AUTOTRI_W {
491        AUTOTRI_W::new(self)
492    }
493    #[doc = "Bit 18 - SmartCard Mode"]
494    #[inline(always)]
495    pub fn scmode(&mut self) -> SCMODE_W {
496        SCMODE_W::new(self)
497    }
498    #[doc = "Bit 19 - SmartCard Retransmit"]
499    #[inline(always)]
500    pub fn scretrans(&mut self) -> SCRETRANS_W {
501        SCRETRANS_W::new(self)
502    }
503    #[doc = "Bit 20 - Skip Parity Error Frames"]
504    #[inline(always)]
505    pub fn skipperrf(&mut self) -> SKIPPERRF_W {
506        SKIPPERRF_W::new(self)
507    }
508    #[doc = "Bit 21 - Bit 8 Default Value"]
509    #[inline(always)]
510    pub fn bit8dv(&mut self) -> BIT8DV_W {
511        BIT8DV_W::new(self)
512    }
513    #[doc = "Bit 22 - Halt DMA On Error"]
514    #[inline(always)]
515    pub fn errsdma(&mut self) -> ERRSDMA_W {
516        ERRSDMA_W::new(self)
517    }
518    #[doc = "Bit 23 - Disable RX On Error"]
519    #[inline(always)]
520    pub fn errsrx(&mut self) -> ERRSRX_W {
521        ERRSRX_W::new(self)
522    }
523    #[doc = "Bit 24 - Disable TX On Error"]
524    #[inline(always)]
525    pub fn errstx(&mut self) -> ERRSTX_W {
526        ERRSTX_W::new(self)
527    }
528    #[doc = "Bits 26:27 - TX Delay Transmission"]
529    #[inline(always)]
530    pub fn txdelay(&mut self) -> TXDELAY_W {
531        TXDELAY_W::new(self)
532    }
533    #[doc = "Bit 28 - Byteswap In Double Accesses"]
534    #[inline(always)]
535    pub fn byteswap(&mut self) -> BYTESWAP_W {
536        BYTESWAP_W::new(self)
537    }
538    #[doc = "Writes raw bits to the register."]
539    #[inline(always)]
540    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
541        self.0.bits(bits);
542        self
543    }
544}
545#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
546pub struct CTRL_SPEC;
547impl crate::RegisterSpec for CTRL_SPEC {
548    type Ux = u32;
549}
550#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
551impl crate::Readable for CTRL_SPEC {
552    type Reader = R;
553}
554#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
555impl crate::Writable for CTRL_SPEC {
556    type Writer = W;
557}
558#[doc = "`reset()` method sets CTRL to value 0"]
559impl crate::Resettable for CTRL_SPEC {
560    #[inline(always)]
561    fn reset_value() -> Self::Ux {
562        0
563    }
564}
efm32g230_pac/usart2/ctrl.rs

efm32g230_pac/usart2/
ctrl.rs
