efm32g230_pac/timer1/
route.rs1#[doc = "Register `ROUTE` reader"]
2pub struct R(crate::R<ROUTE_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ROUTE_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ROUTE_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ROUTE_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `ROUTE` writer"]
17pub struct W(crate::W<ROUTE_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ROUTE_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ROUTE_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ROUTE_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CC0PEN` reader - CC Channel 0 Pin Enable"]
38pub type CC0PEN_R = crate::BitReader<bool>;
39#[doc = "Field `CC0PEN` writer - CC Channel 0 Pin Enable"]
40pub type CC0PEN_W<'a> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, 0>;
41#[doc = "Field `CC1PEN` reader - CC Channel 1 Pin Enable"]
42pub type CC1PEN_R = crate::BitReader<bool>;
43#[doc = "Field `CC1PEN` writer - CC Channel 1 Pin Enable"]
44pub type CC1PEN_W<'a> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, 1>;
45#[doc = "Field `CC2PEN` reader - CC Channel 2 Pin Enable"]
46pub type CC2PEN_R = crate::BitReader<bool>;
47#[doc = "Field `CC2PEN` writer - CC Channel 2 Pin Enable"]
48pub type CC2PEN_W<'a> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, 2>;
49#[doc = "Field `CDTI0PEN` reader - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
50pub type CDTI0PEN_R = crate::BitReader<bool>;
51#[doc = "Field `CDTI0PEN` writer - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
52pub type CDTI0PEN_W<'a> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, 8>;
53#[doc = "Field `CDTI1PEN` reader - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
54pub type CDTI1PEN_R = crate::BitReader<bool>;
55#[doc = "Field `CDTI1PEN` writer - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
56pub type CDTI1PEN_W<'a> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, 9>;
57#[doc = "Field `CDTI2PEN` reader - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
58pub type CDTI2PEN_R = crate::BitReader<bool>;
59#[doc = "Field `CDTI2PEN` writer - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
60pub type CDTI2PEN_W<'a> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, 10>;
61#[doc = "I/O Location\n\nValue on reset: 0"]
62#[derive(Clone, Copy, Debug, PartialEq)]
63#[repr(u8)]
64pub enum LOCATION_A {
65 #[doc = "0: Location 0"]
66 LOC0 = 0,
67 #[doc = "1: Location 1"]
68 LOC1 = 1,
69 #[doc = "2: Location 2"]
70 LOC2 = 2,
71 #[doc = "3: Location 3"]
72 LOC3 = 3,
73}
74impl From<LOCATION_A> for u8 {
75 #[inline(always)]
76 fn from(variant: LOCATION_A) -> Self {
77 variant as _
78 }
79}
80#[doc = "Field `LOCATION` reader - I/O Location"]
81pub type LOCATION_R = crate::FieldReader<u8, LOCATION_A>;
82impl LOCATION_R {
83 #[doc = "Get enumerated values variant"]
84 #[inline(always)]
85 pub fn variant(&self) -> LOCATION_A {
86 match self.bits {
87 0 => LOCATION_A::LOC0,
88 1 => LOCATION_A::LOC1,
89 2 => LOCATION_A::LOC2,
90 3 => LOCATION_A::LOC3,
91 _ => unreachable!(),
92 }
93 }
94 #[doc = "Checks if the value of the field is `LOC0`"]
95 #[inline(always)]
96 pub fn is_loc0(&self) -> bool {
97 *self == LOCATION_A::LOC0
98 }
99 #[doc = "Checks if the value of the field is `LOC1`"]
100 #[inline(always)]
101 pub fn is_loc1(&self) -> bool {
102 *self == LOCATION_A::LOC1
103 }
104 #[doc = "Checks if the value of the field is `LOC2`"]
105 #[inline(always)]
106 pub fn is_loc2(&self) -> bool {
107 *self == LOCATION_A::LOC2
108 }
109 #[doc = "Checks if the value of the field is `LOC3`"]
110 #[inline(always)]
111 pub fn is_loc3(&self) -> bool {
112 *self == LOCATION_A::LOC3
113 }
114}
115#[doc = "Field `LOCATION` writer - I/O Location"]
116pub type LOCATION_W<'a> = crate::FieldWriterSafe<'a, u32, ROUTE_SPEC, u8, LOCATION_A, 2, 16>;
117impl<'a> LOCATION_W<'a> {
118 #[doc = "Location 0"]
119 #[inline(always)]
120 pub fn loc0(self) -> &'a mut W {
121 self.variant(LOCATION_A::LOC0)
122 }
123 #[doc = "Location 1"]
124 #[inline(always)]
125 pub fn loc1(self) -> &'a mut W {
126 self.variant(LOCATION_A::LOC1)
127 }
128 #[doc = "Location 2"]
129 #[inline(always)]
130 pub fn loc2(self) -> &'a mut W {
131 self.variant(LOCATION_A::LOC2)
132 }
133 #[doc = "Location 3"]
134 #[inline(always)]
135 pub fn loc3(self) -> &'a mut W {
136 self.variant(LOCATION_A::LOC3)
137 }
138}
139impl R {
140 #[doc = "Bit 0 - CC Channel 0 Pin Enable"]
141 #[inline(always)]
142 pub fn cc0pen(&self) -> CC0PEN_R {
143 CC0PEN_R::new((self.bits & 1) != 0)
144 }
145 #[doc = "Bit 1 - CC Channel 1 Pin Enable"]
146 #[inline(always)]
147 pub fn cc1pen(&self) -> CC1PEN_R {
148 CC1PEN_R::new(((self.bits >> 1) & 1) != 0)
149 }
150 #[doc = "Bit 2 - CC Channel 2 Pin Enable"]
151 #[inline(always)]
152 pub fn cc2pen(&self) -> CC2PEN_R {
153 CC2PEN_R::new(((self.bits >> 2) & 1) != 0)
154 }
155 #[doc = "Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
156 #[inline(always)]
157 pub fn cdti0pen(&self) -> CDTI0PEN_R {
158 CDTI0PEN_R::new(((self.bits >> 8) & 1) != 0)
159 }
160 #[doc = "Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
161 #[inline(always)]
162 pub fn cdti1pen(&self) -> CDTI1PEN_R {
163 CDTI1PEN_R::new(((self.bits >> 9) & 1) != 0)
164 }
165 #[doc = "Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
166 #[inline(always)]
167 pub fn cdti2pen(&self) -> CDTI2PEN_R {
168 CDTI2PEN_R::new(((self.bits >> 10) & 1) != 0)
169 }
170 #[doc = "Bits 16:17 - I/O Location"]
171 #[inline(always)]
172 pub fn location(&self) -> LOCATION_R {
173 LOCATION_R::new(((self.bits >> 16) & 3) as u8)
174 }
175}
176impl W {
177 #[doc = "Bit 0 - CC Channel 0 Pin Enable"]
178 #[inline(always)]
179 pub fn cc0pen(&mut self) -> CC0PEN_W {
180 CC0PEN_W::new(self)
181 }
182 #[doc = "Bit 1 - CC Channel 1 Pin Enable"]
183 #[inline(always)]
184 pub fn cc1pen(&mut self) -> CC1PEN_W {
185 CC1PEN_W::new(self)
186 }
187 #[doc = "Bit 2 - CC Channel 2 Pin Enable"]
188 #[inline(always)]
189 pub fn cc2pen(&mut self) -> CC2PEN_W {
190 CC2PEN_W::new(self)
191 }
192 #[doc = "Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
193 #[inline(always)]
194 pub fn cdti0pen(&mut self) -> CDTI0PEN_W {
195 CDTI0PEN_W::new(self)
196 }
197 #[doc = "Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
198 #[inline(always)]
199 pub fn cdti1pen(&mut self) -> CDTI1PEN_W {
200 CDTI1PEN_W::new(self)
201 }
202 #[doc = "Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
203 #[inline(always)]
204 pub fn cdti2pen(&mut self) -> CDTI2PEN_W {
205 CDTI2PEN_W::new(self)
206 }
207 #[doc = "Bits 16:17 - I/O Location"]
208 #[inline(always)]
209 pub fn location(&mut self) -> LOCATION_W {
210 LOCATION_W::new(self)
211 }
212 #[doc = "Writes raw bits to the register."]
213 #[inline(always)]
214 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
215 self.0.bits(bits);
216 self
217 }
218}
219#[doc = "I/O Routing Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [route](index.html) module"]
220pub struct ROUTE_SPEC;
221impl crate::RegisterSpec for ROUTE_SPEC {
222 type Ux = u32;
223}
224#[doc = "`read()` method returns [route::R](R) reader structure"]
225impl crate::Readable for ROUTE_SPEC {
226 type Reader = R;
227}
228#[doc = "`write(|w| ..)` method takes [route::W](W) writer structure"]
229impl crate::Writable for ROUTE_SPEC {
230 type Writer = W;
231}
232#[doc = "`reset()` method sets ROUTE to value 0"]
233impl crate::Resettable for ROUTE_SPEC {
234 #[inline(always)]
235 fn reset_value() -> Self::Ux {
236 0
237 }
238}