efm32g230_pac/timer1/
ien.rs

1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `OF` reader - Overflow Interrupt Enable"]
38pub type OF_R = crate::BitReader<bool>;
39#[doc = "Field `OF` writer - Overflow Interrupt Enable"]
40pub type OF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 0>;
41#[doc = "Field `UF` reader - Underflow Interrupt Enable"]
42pub type UF_R = crate::BitReader<bool>;
43#[doc = "Field `UF` writer - Underflow Interrupt Enable"]
44pub type UF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 1>;
45#[doc = "Field `CC0` reader - CC Channel 0 Interrupt Enable"]
46pub type CC0_R = crate::BitReader<bool>;
47#[doc = "Field `CC0` writer - CC Channel 0 Interrupt Enable"]
48pub type CC0_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 4>;
49#[doc = "Field `CC1` reader - CC Channel 1 Interrupt Enable"]
50pub type CC1_R = crate::BitReader<bool>;
51#[doc = "Field `CC1` writer - CC Channel 1 Interrupt Enable"]
52pub type CC1_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 5>;
53#[doc = "Field `CC2` reader - CC Channel 2 Interrupt Enable"]
54pub type CC2_R = crate::BitReader<bool>;
55#[doc = "Field `CC2` writer - CC Channel 2 Interrupt Enable"]
56pub type CC2_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 6>;
57#[doc = "Field `ICBOF0` reader - CC Channel 0 Input Capture Buffer Overflow Interrupt Enable"]
58pub type ICBOF0_R = crate::BitReader<bool>;
59#[doc = "Field `ICBOF0` writer - CC Channel 0 Input Capture Buffer Overflow Interrupt Enable"]
60pub type ICBOF0_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 8>;
61#[doc = "Field `ICBOF1` reader - CC Channel 1 Input Capture Buffer Overflow Interrupt Enable"]
62pub type ICBOF1_R = crate::BitReader<bool>;
63#[doc = "Field `ICBOF1` writer - CC Channel 1 Input Capture Buffer Overflow Interrupt Enable"]
64pub type ICBOF1_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 9>;
65#[doc = "Field `ICBOF2` reader - CC Channel 2 Input Capture Buffer Overflow Interrupt Enable"]
66pub type ICBOF2_R = crate::BitReader<bool>;
67#[doc = "Field `ICBOF2` writer - CC Channel 2 Input Capture Buffer Overflow Interrupt Enable"]
68pub type ICBOF2_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 10>;
69impl R {
70    #[doc = "Bit 0 - Overflow Interrupt Enable"]
71    #[inline(always)]
72    pub fn of(&self) -> OF_R {
73        OF_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Underflow Interrupt Enable"]
76    #[inline(always)]
77    pub fn uf(&self) -> UF_R {
78        UF_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 4 - CC Channel 0 Interrupt Enable"]
81    #[inline(always)]
82    pub fn cc0(&self) -> CC0_R {
83        CC0_R::new(((self.bits >> 4) & 1) != 0)
84    }
85    #[doc = "Bit 5 - CC Channel 1 Interrupt Enable"]
86    #[inline(always)]
87    pub fn cc1(&self) -> CC1_R {
88        CC1_R::new(((self.bits >> 5) & 1) != 0)
89    }
90    #[doc = "Bit 6 - CC Channel 2 Interrupt Enable"]
91    #[inline(always)]
92    pub fn cc2(&self) -> CC2_R {
93        CC2_R::new(((self.bits >> 6) & 1) != 0)
94    }
95    #[doc = "Bit 8 - CC Channel 0 Input Capture Buffer Overflow Interrupt Enable"]
96    #[inline(always)]
97    pub fn icbof0(&self) -> ICBOF0_R {
98        ICBOF0_R::new(((self.bits >> 8) & 1) != 0)
99    }
100    #[doc = "Bit 9 - CC Channel 1 Input Capture Buffer Overflow Interrupt Enable"]
101    #[inline(always)]
102    pub fn icbof1(&self) -> ICBOF1_R {
103        ICBOF1_R::new(((self.bits >> 9) & 1) != 0)
104    }
105    #[doc = "Bit 10 - CC Channel 2 Input Capture Buffer Overflow Interrupt Enable"]
106    #[inline(always)]
107    pub fn icbof2(&self) -> ICBOF2_R {
108        ICBOF2_R::new(((self.bits >> 10) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - Overflow Interrupt Enable"]
113    #[inline(always)]
114    pub fn of(&mut self) -> OF_W {
115        OF_W::new(self)
116    }
117    #[doc = "Bit 1 - Underflow Interrupt Enable"]
118    #[inline(always)]
119    pub fn uf(&mut self) -> UF_W {
120        UF_W::new(self)
121    }
122    #[doc = "Bit 4 - CC Channel 0 Interrupt Enable"]
123    #[inline(always)]
124    pub fn cc0(&mut self) -> CC0_W {
125        CC0_W::new(self)
126    }
127    #[doc = "Bit 5 - CC Channel 1 Interrupt Enable"]
128    #[inline(always)]
129    pub fn cc1(&mut self) -> CC1_W {
130        CC1_W::new(self)
131    }
132    #[doc = "Bit 6 - CC Channel 2 Interrupt Enable"]
133    #[inline(always)]
134    pub fn cc2(&mut self) -> CC2_W {
135        CC2_W::new(self)
136    }
137    #[doc = "Bit 8 - CC Channel 0 Input Capture Buffer Overflow Interrupt Enable"]
138    #[inline(always)]
139    pub fn icbof0(&mut self) -> ICBOF0_W {
140        ICBOF0_W::new(self)
141    }
142    #[doc = "Bit 9 - CC Channel 1 Input Capture Buffer Overflow Interrupt Enable"]
143    #[inline(always)]
144    pub fn icbof1(&mut self) -> ICBOF1_W {
145        ICBOF1_W::new(self)
146    }
147    #[doc = "Bit 10 - CC Channel 2 Input Capture Buffer Overflow Interrupt Enable"]
148    #[inline(always)]
149    pub fn icbof2(&mut self) -> ICBOF2_W {
150        ICBOF2_W::new(self)
151    }
152    #[doc = "Writes raw bits to the register."]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
155        self.0.bits(bits);
156        self
157    }
158}
159#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
160pub struct IEN_SPEC;
161impl crate::RegisterSpec for IEN_SPEC {
162    type Ux = u32;
163}
164#[doc = "`read()` method returns [ien::R](R) reader structure"]
165impl crate::Readable for IEN_SPEC {
166    type Reader = R;
167}
168#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
169impl crate::Writable for IEN_SPEC {
170    type Writer = W;
171}
172#[doc = "`reset()` method sets IEN to value 0"]
173impl crate::Resettable for IEN_SPEC {
174    #[inline(always)]
175    fn reset_value() -> Self::Ux {
176        0
177    }
178}