efm32g230_pac/prs/
ch3_ctrl.rs

1#[doc = "Register `CH3_CTRL` reader"]
2pub struct R(crate::R<CH3_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH3_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH3_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH3_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH3_CTRL` writer"]
17pub struct W(crate::W<CH3_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH3_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH3_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH3_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH3_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "3: Analog Comparator 1"]
52    ACMP1 = 3,
53    #[doc = "6: Digital to Analog Converter 0"]
54    DAC0 = 6,
55    #[doc = "8: Analog to Digital Converter 0"]
56    ADC0 = 8,
57    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
58    USART0 = 16,
59    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
60    USART1 = 17,
61    #[doc = "18: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
62    USART2 = 18,
63    #[doc = "28: Timer 0"]
64    TIMER0 = 28,
65    #[doc = "29: Timer 1"]
66    TIMER1 = 29,
67    #[doc = "30: Timer 2"]
68    TIMER2 = 30,
69    #[doc = "40: Real-Time Counter"]
70    RTC = 40,
71    #[doc = "48: General purpose Input/Output"]
72    GPIOL = 48,
73    #[doc = "49: General purpose Input/Output"]
74    GPIOH = 49,
75}
76impl From<SOURCESEL_A> for u8 {
77    #[inline(always)]
78    fn from(variant: SOURCESEL_A) -> Self {
79        variant as _
80    }
81}
82#[doc = "Field `SOURCESEL` reader - Source Select"]
83pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
84impl SOURCESEL_R {
85    #[doc = "Get enumerated values variant"]
86    #[inline(always)]
87    pub fn variant(&self) -> Option<SOURCESEL_A> {
88        match self.bits {
89            0 => Some(SOURCESEL_A::NONE),
90            1 => Some(SOURCESEL_A::VCMP),
91            2 => Some(SOURCESEL_A::ACMP0),
92            3 => Some(SOURCESEL_A::ACMP1),
93            6 => Some(SOURCESEL_A::DAC0),
94            8 => Some(SOURCESEL_A::ADC0),
95            16 => Some(SOURCESEL_A::USART0),
96            17 => Some(SOURCESEL_A::USART1),
97            18 => Some(SOURCESEL_A::USART2),
98            28 => Some(SOURCESEL_A::TIMER0),
99            29 => Some(SOURCESEL_A::TIMER1),
100            30 => Some(SOURCESEL_A::TIMER2),
101            40 => Some(SOURCESEL_A::RTC),
102            48 => Some(SOURCESEL_A::GPIOL),
103            49 => Some(SOURCESEL_A::GPIOH),
104            _ => None,
105        }
106    }
107    #[doc = "Checks if the value of the field is `NONE`"]
108    #[inline(always)]
109    pub fn is_none(&self) -> bool {
110        *self == SOURCESEL_A::NONE
111    }
112    #[doc = "Checks if the value of the field is `VCMP`"]
113    #[inline(always)]
114    pub fn is_vcmp(&self) -> bool {
115        *self == SOURCESEL_A::VCMP
116    }
117    #[doc = "Checks if the value of the field is `ACMP0`"]
118    #[inline(always)]
119    pub fn is_acmp0(&self) -> bool {
120        *self == SOURCESEL_A::ACMP0
121    }
122    #[doc = "Checks if the value of the field is `ACMP1`"]
123    #[inline(always)]
124    pub fn is_acmp1(&self) -> bool {
125        *self == SOURCESEL_A::ACMP1
126    }
127    #[doc = "Checks if the value of the field is `DAC0`"]
128    #[inline(always)]
129    pub fn is_dac0(&self) -> bool {
130        *self == SOURCESEL_A::DAC0
131    }
132    #[doc = "Checks if the value of the field is `ADC0`"]
133    #[inline(always)]
134    pub fn is_adc0(&self) -> bool {
135        *self == SOURCESEL_A::ADC0
136    }
137    #[doc = "Checks if the value of the field is `USART0`"]
138    #[inline(always)]
139    pub fn is_usart0(&self) -> bool {
140        *self == SOURCESEL_A::USART0
141    }
142    #[doc = "Checks if the value of the field is `USART1`"]
143    #[inline(always)]
144    pub fn is_usart1(&self) -> bool {
145        *self == SOURCESEL_A::USART1
146    }
147    #[doc = "Checks if the value of the field is `USART2`"]
148    #[inline(always)]
149    pub fn is_usart2(&self) -> bool {
150        *self == SOURCESEL_A::USART2
151    }
152    #[doc = "Checks if the value of the field is `TIMER0`"]
153    #[inline(always)]
154    pub fn is_timer0(&self) -> bool {
155        *self == SOURCESEL_A::TIMER0
156    }
157    #[doc = "Checks if the value of the field is `TIMER1`"]
158    #[inline(always)]
159    pub fn is_timer1(&self) -> bool {
160        *self == SOURCESEL_A::TIMER1
161    }
162    #[doc = "Checks if the value of the field is `TIMER2`"]
163    #[inline(always)]
164    pub fn is_timer2(&self) -> bool {
165        *self == SOURCESEL_A::TIMER2
166    }
167    #[doc = "Checks if the value of the field is `RTC`"]
168    #[inline(always)]
169    pub fn is_rtc(&self) -> bool {
170        *self == SOURCESEL_A::RTC
171    }
172    #[doc = "Checks if the value of the field is `GPIOL`"]
173    #[inline(always)]
174    pub fn is_gpiol(&self) -> bool {
175        *self == SOURCESEL_A::GPIOL
176    }
177    #[doc = "Checks if the value of the field is `GPIOH`"]
178    #[inline(always)]
179    pub fn is_gpioh(&self) -> bool {
180        *self == SOURCESEL_A::GPIOH
181    }
182}
183#[doc = "Field `SOURCESEL` writer - Source Select"]
184pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH3_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
185impl<'a> SOURCESEL_W<'a> {
186    #[doc = "No source selected"]
187    #[inline(always)]
188    pub fn none(self) -> &'a mut W {
189        self.variant(SOURCESEL_A::NONE)
190    }
191    #[doc = "Voltage Comparator"]
192    #[inline(always)]
193    pub fn vcmp(self) -> &'a mut W {
194        self.variant(SOURCESEL_A::VCMP)
195    }
196    #[doc = "Analog Comparator 0"]
197    #[inline(always)]
198    pub fn acmp0(self) -> &'a mut W {
199        self.variant(SOURCESEL_A::ACMP0)
200    }
201    #[doc = "Analog Comparator 1"]
202    #[inline(always)]
203    pub fn acmp1(self) -> &'a mut W {
204        self.variant(SOURCESEL_A::ACMP1)
205    }
206    #[doc = "Digital to Analog Converter 0"]
207    #[inline(always)]
208    pub fn dac0(self) -> &'a mut W {
209        self.variant(SOURCESEL_A::DAC0)
210    }
211    #[doc = "Analog to Digital Converter 0"]
212    #[inline(always)]
213    pub fn adc0(self) -> &'a mut W {
214        self.variant(SOURCESEL_A::ADC0)
215    }
216    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
217    #[inline(always)]
218    pub fn usart0(self) -> &'a mut W {
219        self.variant(SOURCESEL_A::USART0)
220    }
221    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
222    #[inline(always)]
223    pub fn usart1(self) -> &'a mut W {
224        self.variant(SOURCESEL_A::USART1)
225    }
226    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
227    #[inline(always)]
228    pub fn usart2(self) -> &'a mut W {
229        self.variant(SOURCESEL_A::USART2)
230    }
231    #[doc = "Timer 0"]
232    #[inline(always)]
233    pub fn timer0(self) -> &'a mut W {
234        self.variant(SOURCESEL_A::TIMER0)
235    }
236    #[doc = "Timer 1"]
237    #[inline(always)]
238    pub fn timer1(self) -> &'a mut W {
239        self.variant(SOURCESEL_A::TIMER1)
240    }
241    #[doc = "Timer 2"]
242    #[inline(always)]
243    pub fn timer2(self) -> &'a mut W {
244        self.variant(SOURCESEL_A::TIMER2)
245    }
246    #[doc = "Real-Time Counter"]
247    #[inline(always)]
248    pub fn rtc(self) -> &'a mut W {
249        self.variant(SOURCESEL_A::RTC)
250    }
251    #[doc = "General purpose Input/Output"]
252    #[inline(always)]
253    pub fn gpiol(self) -> &'a mut W {
254        self.variant(SOURCESEL_A::GPIOL)
255    }
256    #[doc = "General purpose Input/Output"]
257    #[inline(always)]
258    pub fn gpioh(self) -> &'a mut W {
259        self.variant(SOURCESEL_A::GPIOH)
260    }
261}
262#[doc = "Edge Detect Select\n\nValue on reset: 0"]
263#[derive(Clone, Copy, Debug, PartialEq)]
264#[repr(u8)]
265pub enum EDSEL_A {
266    #[doc = "0: Signal is left as it is"]
267    OFF = 0,
268    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
269    POSEDGE = 1,
270    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
271    NEGEDGE = 2,
272    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
273    BOTHEDGES = 3,
274}
275impl From<EDSEL_A> for u8 {
276    #[inline(always)]
277    fn from(variant: EDSEL_A) -> Self {
278        variant as _
279    }
280}
281#[doc = "Field `EDSEL` reader - Edge Detect Select"]
282pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
283impl EDSEL_R {
284    #[doc = "Get enumerated values variant"]
285    #[inline(always)]
286    pub fn variant(&self) -> EDSEL_A {
287        match self.bits {
288            0 => EDSEL_A::OFF,
289            1 => EDSEL_A::POSEDGE,
290            2 => EDSEL_A::NEGEDGE,
291            3 => EDSEL_A::BOTHEDGES,
292            _ => unreachable!(),
293        }
294    }
295    #[doc = "Checks if the value of the field is `OFF`"]
296    #[inline(always)]
297    pub fn is_off(&self) -> bool {
298        *self == EDSEL_A::OFF
299    }
300    #[doc = "Checks if the value of the field is `POSEDGE`"]
301    #[inline(always)]
302    pub fn is_posedge(&self) -> bool {
303        *self == EDSEL_A::POSEDGE
304    }
305    #[doc = "Checks if the value of the field is `NEGEDGE`"]
306    #[inline(always)]
307    pub fn is_negedge(&self) -> bool {
308        *self == EDSEL_A::NEGEDGE
309    }
310    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
311    #[inline(always)]
312    pub fn is_bothedges(&self) -> bool {
313        *self == EDSEL_A::BOTHEDGES
314    }
315}
316#[doc = "Field `EDSEL` writer - Edge Detect Select"]
317pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH3_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
318impl<'a> EDSEL_W<'a> {
319    #[doc = "Signal is left as it is"]
320    #[inline(always)]
321    pub fn off(self) -> &'a mut W {
322        self.variant(EDSEL_A::OFF)
323    }
324    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
325    #[inline(always)]
326    pub fn posedge(self) -> &'a mut W {
327        self.variant(EDSEL_A::POSEDGE)
328    }
329    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
330    #[inline(always)]
331    pub fn negedge(self) -> &'a mut W {
332        self.variant(EDSEL_A::NEGEDGE)
333    }
334    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
335    #[inline(always)]
336    pub fn bothedges(self) -> &'a mut W {
337        self.variant(EDSEL_A::BOTHEDGES)
338    }
339}
340impl R {
341    #[doc = "Bits 0:2 - Signal Select"]
342    #[inline(always)]
343    pub fn sigsel(&self) -> SIGSEL_R {
344        SIGSEL_R::new((self.bits & 7) as u8)
345    }
346    #[doc = "Bits 16:21 - Source Select"]
347    #[inline(always)]
348    pub fn sourcesel(&self) -> SOURCESEL_R {
349        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
350    }
351    #[doc = "Bits 24:25 - Edge Detect Select"]
352    #[inline(always)]
353    pub fn edsel(&self) -> EDSEL_R {
354        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
355    }
356}
357impl W {
358    #[doc = "Bits 0:2 - Signal Select"]
359    #[inline(always)]
360    pub fn sigsel(&mut self) -> SIGSEL_W {
361        SIGSEL_W::new(self)
362    }
363    #[doc = "Bits 16:21 - Source Select"]
364    #[inline(always)]
365    pub fn sourcesel(&mut self) -> SOURCESEL_W {
366        SOURCESEL_W::new(self)
367    }
368    #[doc = "Bits 24:25 - Edge Detect Select"]
369    #[inline(always)]
370    pub fn edsel(&mut self) -> EDSEL_W {
371        EDSEL_W::new(self)
372    }
373    #[doc = "Writes raw bits to the register."]
374    #[inline(always)]
375    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
376        self.0.bits(bits);
377        self
378    }
379}
380#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch3_ctrl](index.html) module"]
381pub struct CH3_CTRL_SPEC;
382impl crate::RegisterSpec for CH3_CTRL_SPEC {
383    type Ux = u32;
384}
385#[doc = "`read()` method returns [ch3_ctrl::R](R) reader structure"]
386impl crate::Readable for CH3_CTRL_SPEC {
387    type Reader = R;
388}
389#[doc = "`write(|w| ..)` method takes [ch3_ctrl::W](W) writer structure"]
390impl crate::Writable for CH3_CTRL_SPEC {
391    type Writer = W;
392}
393#[doc = "`reset()` method sets CH3_CTRL to value 0"]
394impl crate::Resettable for CH3_CTRL_SPEC {
395    #[inline(always)]
396    fn reset_value() -> Self::Ux {
397        0
398    }
399}
efm32g230_pac/prs/ch3_ctrl.rs

efm32g230_pac/prs/
ch3_ctrl.rs
