efm32g230_pac/pcnt0/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Mode Select\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum MODE_A {
41    #[doc = "0: The module is disabled."]
42    DISABLE = 0,
43    #[doc = "1: Single input LFACLK oversampling mode (available in EM0-EM2)."]
44    OVSSINGLE = 1,
45    #[doc = "2: Externally clocked single input counter mode (available in EM0-EM3)."]
46    EXTCLKSINGLE = 2,
47    #[doc = "3: Externally clocked quadrature decoder mode (available in EM0-EM3)."]
48    EXTCLKQUAD = 3,
49}
50impl From<MODE_A> for u8 {
51    #[inline(always)]
52    fn from(variant: MODE_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `MODE` reader - Mode Select"]
57pub type MODE_R = crate::FieldReader<u8, MODE_A>;
58impl MODE_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> MODE_A {
62        match self.bits {
63            0 => MODE_A::DISABLE,
64            1 => MODE_A::OVSSINGLE,
65            2 => MODE_A::EXTCLKSINGLE,
66            3 => MODE_A::EXTCLKQUAD,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `DISABLE`"]
71    #[inline(always)]
72    pub fn is_disable(&self) -> bool {
73        *self == MODE_A::DISABLE
74    }
75    #[doc = "Checks if the value of the field is `OVSSINGLE`"]
76    #[inline(always)]
77    pub fn is_ovssingle(&self) -> bool {
78        *self == MODE_A::OVSSINGLE
79    }
80    #[doc = "Checks if the value of the field is `EXTCLKSINGLE`"]
81    #[inline(always)]
82    pub fn is_extclksingle(&self) -> bool {
83        *self == MODE_A::EXTCLKSINGLE
84    }
85    #[doc = "Checks if the value of the field is `EXTCLKQUAD`"]
86    #[inline(always)]
87    pub fn is_extclkquad(&self) -> bool {
88        *self == MODE_A::EXTCLKQUAD
89    }
90}
91#[doc = "Field `MODE` writer - Mode Select"]
92pub type MODE_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE_A, 2, 0>;
93impl<'a> MODE_W<'a> {
94    #[doc = "The module is disabled."]
95    #[inline(always)]
96    pub fn disable(self) -> &'a mut W {
97        self.variant(MODE_A::DISABLE)
98    }
99    #[doc = "Single input LFACLK oversampling mode (available in EM0-EM2)."]
100    #[inline(always)]
101    pub fn ovssingle(self) -> &'a mut W {
102        self.variant(MODE_A::OVSSINGLE)
103    }
104    #[doc = "Externally clocked single input counter mode (available in EM0-EM3)."]
105    #[inline(always)]
106    pub fn extclksingle(self) -> &'a mut W {
107        self.variant(MODE_A::EXTCLKSINGLE)
108    }
109    #[doc = "Externally clocked quadrature decoder mode (available in EM0-EM3)."]
110    #[inline(always)]
111    pub fn extclkquad(self) -> &'a mut W {
112        self.variant(MODE_A::EXTCLKQUAD)
113    }
114}
115#[doc = "Field `CNTDIR` reader - Non-Quadrature Mode Counter Direction Control"]
116pub type CNTDIR_R = crate::BitReader<bool>;
117#[doc = "Field `CNTDIR` writer - Non-Quadrature Mode Counter Direction Control"]
118pub type CNTDIR_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
119#[doc = "Field `EDGE` reader - Edge Select"]
120pub type EDGE_R = crate::BitReader<bool>;
121#[doc = "Field `EDGE` writer - Edge Select"]
122pub type EDGE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
123#[doc = "Field `FILT` reader - Enable Digital Pulse Width Filter"]
124pub type FILT_R = crate::BitReader<bool>;
125#[doc = "Field `FILT` writer - Enable Digital Pulse Width Filter"]
126pub type FILT_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
127#[doc = "Field `RSTEN` reader - Enable PCNT Clock Domain Reset"]
128pub type RSTEN_R = crate::BitReader<bool>;
129#[doc = "Field `RSTEN` writer - Enable PCNT Clock Domain Reset"]
130pub type RSTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 5>;
131impl R {
132    #[doc = "Bits 0:1 - Mode Select"]
133    #[inline(always)]
134    pub fn mode(&self) -> MODE_R {
135        MODE_R::new((self.bits & 3) as u8)
136    }
137    #[doc = "Bit 2 - Non-Quadrature Mode Counter Direction Control"]
138    #[inline(always)]
139    pub fn cntdir(&self) -> CNTDIR_R {
140        CNTDIR_R::new(((self.bits >> 2) & 1) != 0)
141    }
142    #[doc = "Bit 3 - Edge Select"]
143    #[inline(always)]
144    pub fn edge(&self) -> EDGE_R {
145        EDGE_R::new(((self.bits >> 3) & 1) != 0)
146    }
147    #[doc = "Bit 4 - Enable Digital Pulse Width Filter"]
148    #[inline(always)]
149    pub fn filt(&self) -> FILT_R {
150        FILT_R::new(((self.bits >> 4) & 1) != 0)
151    }
152    #[doc = "Bit 5 - Enable PCNT Clock Domain Reset"]
153    #[inline(always)]
154    pub fn rsten(&self) -> RSTEN_R {
155        RSTEN_R::new(((self.bits >> 5) & 1) != 0)
156    }
157}
158impl W {
159    #[doc = "Bits 0:1 - Mode Select"]
160    #[inline(always)]
161    pub fn mode(&mut self) -> MODE_W {
162        MODE_W::new(self)
163    }
164    #[doc = "Bit 2 - Non-Quadrature Mode Counter Direction Control"]
165    #[inline(always)]
166    pub fn cntdir(&mut self) -> CNTDIR_W {
167        CNTDIR_W::new(self)
168    }
169    #[doc = "Bit 3 - Edge Select"]
170    #[inline(always)]
171    pub fn edge(&mut self) -> EDGE_W {
172        EDGE_W::new(self)
173    }
174    #[doc = "Bit 4 - Enable Digital Pulse Width Filter"]
175    #[inline(always)]
176    pub fn filt(&mut self) -> FILT_W {
177        FILT_W::new(self)
178    }
179    #[doc = "Bit 5 - Enable PCNT Clock Domain Reset"]
180    #[inline(always)]
181    pub fn rsten(&mut self) -> RSTEN_W {
182        RSTEN_W::new(self)
183    }
184    #[doc = "Writes raw bits to the register."]
185    #[inline(always)]
186    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
187        self.0.bits(bits);
188        self
189    }
190}
191#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
192pub struct CTRL_SPEC;
193impl crate::RegisterSpec for CTRL_SPEC {
194    type Ux = u32;
195}
196#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
197impl crate::Readable for CTRL_SPEC {
198    type Reader = R;
199}
200#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
201impl crate::Writable for CTRL_SPEC {
202    type Writer = W;
203}
204#[doc = "`reset()` method sets CTRL to value 0"]
205impl crate::Resettable for CTRL_SPEC {
206    #[inline(always)]
207    fn reset_value() -> Self::Ux {
208        0
209    }
210}
efm32g230_pac/pcnt0/ctrl.rs

efm32g230_pac/pcnt0/
ctrl.rs
