efm32g230_pac/msc/
readctrl.rs

1#[doc = "Register `READCTRL` reader"]
2pub struct R(crate::R<READCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<READCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<READCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<READCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `READCTRL` writer"]
17pub struct W(crate::W<READCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<READCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<READCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<READCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Read Mode\n\nValue on reset: 1"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum MODE_A {
41    #[doc = "0: Zero wait-states inserted in fetch or read transfers."]
42    WS0 = 0,
43    #[doc = "1: One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz."]
44    WS1 = 1,
45    #[doc = "2: Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex' conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty."]
46    WS0SCBTP = 2,
47    #[doc = "3: One wait-state access with SCBTP enabled."]
48    WS1SCBTP = 3,
49}
50impl From<MODE_A> for u8 {
51    #[inline(always)]
52    fn from(variant: MODE_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `MODE` reader - Read Mode"]
57pub type MODE_R = crate::FieldReader<u8, MODE_A>;
58impl MODE_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> Option<MODE_A> {
62        match self.bits {
63            0 => Some(MODE_A::WS0),
64            1 => Some(MODE_A::WS1),
65            2 => Some(MODE_A::WS0SCBTP),
66            3 => Some(MODE_A::WS1SCBTP),
67            _ => None,
68        }
69    }
70    #[doc = "Checks if the value of the field is `WS0`"]
71    #[inline(always)]
72    pub fn is_ws0(&self) -> bool {
73        *self == MODE_A::WS0
74    }
75    #[doc = "Checks if the value of the field is `WS1`"]
76    #[inline(always)]
77    pub fn is_ws1(&self) -> bool {
78        *self == MODE_A::WS1
79    }
80    #[doc = "Checks if the value of the field is `WS0SCBTP`"]
81    #[inline(always)]
82    pub fn is_ws0scbtp(&self) -> bool {
83        *self == MODE_A::WS0SCBTP
84    }
85    #[doc = "Checks if the value of the field is `WS1SCBTP`"]
86    #[inline(always)]
87    pub fn is_ws1scbtp(&self) -> bool {
88        *self == MODE_A::WS1SCBTP
89    }
90}
91#[doc = "Field `MODE` writer - Read Mode"]
92pub type MODE_W<'a> = crate::FieldWriter<'a, u32, READCTRL_SPEC, u8, MODE_A, 3, 0>;
93impl<'a> MODE_W<'a> {
94    #[doc = "Zero wait-states inserted in fetch or read transfers."]
95    #[inline(always)]
96    pub fn ws0(self) -> &'a mut W {
97        self.variant(MODE_A::WS0)
98    }
99    #[doc = "One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz."]
100    #[inline(always)]
101    pub fn ws1(self) -> &'a mut W {
102        self.variant(MODE_A::WS1)
103    }
104    #[doc = "Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex' conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty."]
105    #[inline(always)]
106    pub fn ws0scbtp(self) -> &'a mut W {
107        self.variant(MODE_A::WS0SCBTP)
108    }
109    #[doc = "One wait-state access with SCBTP enabled."]
110    #[inline(always)]
111    pub fn ws1scbtp(self) -> &'a mut W {
112        self.variant(MODE_A::WS1SCBTP)
113    }
114}
115impl R {
116    #[doc = "Bits 0:2 - Read Mode"]
117    #[inline(always)]
118    pub fn mode(&self) -> MODE_R {
119        MODE_R::new((self.bits & 7) as u8)
120    }
121}
122impl W {
123    #[doc = "Bits 0:2 - Read Mode"]
124    #[inline(always)]
125    pub fn mode(&mut self) -> MODE_W {
126        MODE_W::new(self)
127    }
128    #[doc = "Writes raw bits to the register."]
129    #[inline(always)]
130    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
131        self.0.bits(bits);
132        self
133    }
134}
135#[doc = "Read Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readctrl](index.html) module"]
136pub struct READCTRL_SPEC;
137impl crate::RegisterSpec for READCTRL_SPEC {
138    type Ux = u32;
139}
140#[doc = "`read()` method returns [readctrl::R](R) reader structure"]
141impl crate::Readable for READCTRL_SPEC {
142    type Reader = R;
143}
144#[doc = "`write(|w| ..)` method takes [readctrl::W](W) writer structure"]
145impl crate::Writable for READCTRL_SPEC {
146    type Writer = W;
147}
148#[doc = "`reset()` method sets READCTRL to value 0x01"]
149impl crate::Resettable for READCTRL_SPEC {
150    #[inline(always)]
151    fn reset_value() -> Self::Ux {
152        0x01
153    }
154}
efm32g230_pac/msc/readctrl.rs

efm32g230_pac/msc/
readctrl.rs
