efm32g230_pac/leuart1/
ien.rs1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<IEN_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<IEN_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<IEN_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<IEN_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TXC` reader - TX Complete Interrupt Enable"]
38pub type TXC_R = crate::BitReader<bool>;
39#[doc = "Field `TXC` writer - TX Complete Interrupt Enable"]
40pub type TXC_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 0>;
41#[doc = "Field `TXBL` reader - TX Buffer Level Interrupt Enable"]
42pub type TXBL_R = crate::BitReader<bool>;
43#[doc = "Field `TXBL` writer - TX Buffer Level Interrupt Enable"]
44pub type TXBL_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 1>;
45#[doc = "Field `RXDATAV` reader - RX Data Valid Interrupt Enable"]
46pub type RXDATAV_R = crate::BitReader<bool>;
47#[doc = "Field `RXDATAV` writer - RX Data Valid Interrupt Enable"]
48pub type RXDATAV_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 2>;
49#[doc = "Field `RXOF` reader - RX Overflow Interrupt Enable"]
50pub type RXOF_R = crate::BitReader<bool>;
51#[doc = "Field `RXOF` writer - RX Overflow Interrupt Enable"]
52pub type RXOF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 3>;
53#[doc = "Field `RXUF` reader - RX Underflow Interrupt Enable"]
54pub type RXUF_R = crate::BitReader<bool>;
55#[doc = "Field `RXUF` writer - RX Underflow Interrupt Enable"]
56pub type RXUF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 4>;
57#[doc = "Field `TXOF` reader - TX Overflow Interrupt Enable"]
58pub type TXOF_R = crate::BitReader<bool>;
59#[doc = "Field `TXOF` writer - TX Overflow Interrupt Enable"]
60pub type TXOF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 5>;
61#[doc = "Field `PERR` reader - Parity Error Interrupt Enable"]
62pub type PERR_R = crate::BitReader<bool>;
63#[doc = "Field `PERR` writer - Parity Error Interrupt Enable"]
64pub type PERR_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 6>;
65#[doc = "Field `FERR` reader - Framing Error Interrupt Enable"]
66pub type FERR_R = crate::BitReader<bool>;
67#[doc = "Field `FERR` writer - Framing Error Interrupt Enable"]
68pub type FERR_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 7>;
69#[doc = "Field `MPAF` reader - Multi-Processor Address Frame Interrupt Enable"]
70pub type MPAF_R = crate::BitReader<bool>;
71#[doc = "Field `MPAF` writer - Multi-Processor Address Frame Interrupt Enable"]
72pub type MPAF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 8>;
73#[doc = "Field `STARTF` reader - Start Frame Interrupt Enable"]
74pub type STARTF_R = crate::BitReader<bool>;
75#[doc = "Field `STARTF` writer - Start Frame Interrupt Enable"]
76pub type STARTF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 9>;
77#[doc = "Field `SIGF` reader - Signal Frame Interrupt Enable"]
78pub type SIGF_R = crate::BitReader<bool>;
79#[doc = "Field `SIGF` writer - Signal Frame Interrupt Enable"]
80pub type SIGF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 10>;
81impl R {
82 #[doc = "Bit 0 - TX Complete Interrupt Enable"]
83 #[inline(always)]
84 pub fn txc(&self) -> TXC_R {
85 TXC_R::new((self.bits & 1) != 0)
86 }
87 #[doc = "Bit 1 - TX Buffer Level Interrupt Enable"]
88 #[inline(always)]
89 pub fn txbl(&self) -> TXBL_R {
90 TXBL_R::new(((self.bits >> 1) & 1) != 0)
91 }
92 #[doc = "Bit 2 - RX Data Valid Interrupt Enable"]
93 #[inline(always)]
94 pub fn rxdatav(&self) -> RXDATAV_R {
95 RXDATAV_R::new(((self.bits >> 2) & 1) != 0)
96 }
97 #[doc = "Bit 3 - RX Overflow Interrupt Enable"]
98 #[inline(always)]
99 pub fn rxof(&self) -> RXOF_R {
100 RXOF_R::new(((self.bits >> 3) & 1) != 0)
101 }
102 #[doc = "Bit 4 - RX Underflow Interrupt Enable"]
103 #[inline(always)]
104 pub fn rxuf(&self) -> RXUF_R {
105 RXUF_R::new(((self.bits >> 4) & 1) != 0)
106 }
107 #[doc = "Bit 5 - TX Overflow Interrupt Enable"]
108 #[inline(always)]
109 pub fn txof(&self) -> TXOF_R {
110 TXOF_R::new(((self.bits >> 5) & 1) != 0)
111 }
112 #[doc = "Bit 6 - Parity Error Interrupt Enable"]
113 #[inline(always)]
114 pub fn perr(&self) -> PERR_R {
115 PERR_R::new(((self.bits >> 6) & 1) != 0)
116 }
117 #[doc = "Bit 7 - Framing Error Interrupt Enable"]
118 #[inline(always)]
119 pub fn ferr(&self) -> FERR_R {
120 FERR_R::new(((self.bits >> 7) & 1) != 0)
121 }
122 #[doc = "Bit 8 - Multi-Processor Address Frame Interrupt Enable"]
123 #[inline(always)]
124 pub fn mpaf(&self) -> MPAF_R {
125 MPAF_R::new(((self.bits >> 8) & 1) != 0)
126 }
127 #[doc = "Bit 9 - Start Frame Interrupt Enable"]
128 #[inline(always)]
129 pub fn startf(&self) -> STARTF_R {
130 STARTF_R::new(((self.bits >> 9) & 1) != 0)
131 }
132 #[doc = "Bit 10 - Signal Frame Interrupt Enable"]
133 #[inline(always)]
134 pub fn sigf(&self) -> SIGF_R {
135 SIGF_R::new(((self.bits >> 10) & 1) != 0)
136 }
137}
138impl W {
139 #[doc = "Bit 0 - TX Complete Interrupt Enable"]
140 #[inline(always)]
141 pub fn txc(&mut self) -> TXC_W {
142 TXC_W::new(self)
143 }
144 #[doc = "Bit 1 - TX Buffer Level Interrupt Enable"]
145 #[inline(always)]
146 pub fn txbl(&mut self) -> TXBL_W {
147 TXBL_W::new(self)
148 }
149 #[doc = "Bit 2 - RX Data Valid Interrupt Enable"]
150 #[inline(always)]
151 pub fn rxdatav(&mut self) -> RXDATAV_W {
152 RXDATAV_W::new(self)
153 }
154 #[doc = "Bit 3 - RX Overflow Interrupt Enable"]
155 #[inline(always)]
156 pub fn rxof(&mut self) -> RXOF_W {
157 RXOF_W::new(self)
158 }
159 #[doc = "Bit 4 - RX Underflow Interrupt Enable"]
160 #[inline(always)]
161 pub fn rxuf(&mut self) -> RXUF_W {
162 RXUF_W::new(self)
163 }
164 #[doc = "Bit 5 - TX Overflow Interrupt Enable"]
165 #[inline(always)]
166 pub fn txof(&mut self) -> TXOF_W {
167 TXOF_W::new(self)
168 }
169 #[doc = "Bit 6 - Parity Error Interrupt Enable"]
170 #[inline(always)]
171 pub fn perr(&mut self) -> PERR_W {
172 PERR_W::new(self)
173 }
174 #[doc = "Bit 7 - Framing Error Interrupt Enable"]
175 #[inline(always)]
176 pub fn ferr(&mut self) -> FERR_W {
177 FERR_W::new(self)
178 }
179 #[doc = "Bit 8 - Multi-Processor Address Frame Interrupt Enable"]
180 #[inline(always)]
181 pub fn mpaf(&mut self) -> MPAF_W {
182 MPAF_W::new(self)
183 }
184 #[doc = "Bit 9 - Start Frame Interrupt Enable"]
185 #[inline(always)]
186 pub fn startf(&mut self) -> STARTF_W {
187 STARTF_W::new(self)
188 }
189 #[doc = "Bit 10 - Signal Frame Interrupt Enable"]
190 #[inline(always)]
191 pub fn sigf(&mut self) -> SIGF_W {
192 SIGF_W::new(self)
193 }
194 #[doc = "Writes raw bits to the register."]
195 #[inline(always)]
196 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
197 self.0.bits(bits);
198 self
199 }
200}
201#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
202pub struct IEN_SPEC;
203impl crate::RegisterSpec for IEN_SPEC {
204 type Ux = u32;
205}
206#[doc = "`read()` method returns [ien::R](R) reader structure"]
207impl crate::Readable for IEN_SPEC {
208 type Reader = R;
209}
210#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
211impl crate::Writable for IEN_SPEC {
212 type Writer = W;
213}
214#[doc = "`reset()` method sets IEN to value 0"]
215impl crate::Resettable for IEN_SPEC {
216 #[inline(always)]
217 fn reset_value() -> Self::Ux {
218 0
219 }
220}