efm32g230_pac/i2c0/
ifc.rs

1#[doc = "Register `IFC` writer"]
2pub struct W(crate::W<IFC_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IFC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IFC_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IFC_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `START` writer - Clear START Interrupt Flag"]
23pub type START_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 0>;
24#[doc = "Field `RSTART` writer - Clear Repeated START Interrupt Flag"]
25pub type RSTART_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 1>;
26#[doc = "Field `ADDR` writer - Clear Address Interrupt Flag"]
27pub type ADDR_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 2>;
28#[doc = "Field `TXC` writer - Clear Transfer Completed Interrupt Flag"]
29pub type TXC_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 3>;
30#[doc = "Field `ACK` writer - Clear Acknowledge Received Interrupt Flag"]
31pub type ACK_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 6>;
32#[doc = "Field `NACK` writer - Clear Not Acknowledge Received Interrupt Flag"]
33pub type NACK_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 7>;
34#[doc = "Field `MSTOP` writer - Clear MSTOP Interrupt Flag"]
35pub type MSTOP_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 8>;
36#[doc = "Field `ARBLOST` writer - Clear Arbitration Lost Interrupt Flag"]
37pub type ARBLOST_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 9>;
38#[doc = "Field `BUSERR` writer - Clear Bus Error Interrupt Flag"]
39pub type BUSERR_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 10>;
40#[doc = "Field `BUSHOLD` writer - Clear Bus Held Interrupt Flag"]
41pub type BUSHOLD_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 11>;
42#[doc = "Field `TXOF` writer - Clear Transmit Buffer Overflow Interrupt Flag"]
43pub type TXOF_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 12>;
44#[doc = "Field `RXUF` writer - Clear Receive Buffer Underflow Interrupt Flag"]
45pub type RXUF_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 13>;
46#[doc = "Field `BITO` writer - Clear Bus Idle Timeout Interrupt Flag"]
47pub type BITO_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 14>;
48#[doc = "Field `CLTO` writer - Clear Clock Low Interrupt Flag"]
49pub type CLTO_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 15>;
50#[doc = "Field `SSTOP` writer - Clear SSTOP Interrupt Flag"]
51pub type SSTOP_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 16>;
52impl W {
53    #[doc = "Bit 0 - Clear START Interrupt Flag"]
54    #[inline(always)]
55    pub fn start(&mut self) -> START_W {
56        START_W::new(self)
57    }
58    #[doc = "Bit 1 - Clear Repeated START Interrupt Flag"]
59    #[inline(always)]
60    pub fn rstart(&mut self) -> RSTART_W {
61        RSTART_W::new(self)
62    }
63    #[doc = "Bit 2 - Clear Address Interrupt Flag"]
64    #[inline(always)]
65    pub fn addr(&mut self) -> ADDR_W {
66        ADDR_W::new(self)
67    }
68    #[doc = "Bit 3 - Clear Transfer Completed Interrupt Flag"]
69    #[inline(always)]
70    pub fn txc(&mut self) -> TXC_W {
71        TXC_W::new(self)
72    }
73    #[doc = "Bit 6 - Clear Acknowledge Received Interrupt Flag"]
74    #[inline(always)]
75    pub fn ack(&mut self) -> ACK_W {
76        ACK_W::new(self)
77    }
78    #[doc = "Bit 7 - Clear Not Acknowledge Received Interrupt Flag"]
79    #[inline(always)]
80    pub fn nack(&mut self) -> NACK_W {
81        NACK_W::new(self)
82    }
83    #[doc = "Bit 8 - Clear MSTOP Interrupt Flag"]
84    #[inline(always)]
85    pub fn mstop(&mut self) -> MSTOP_W {
86        MSTOP_W::new(self)
87    }
88    #[doc = "Bit 9 - Clear Arbitration Lost Interrupt Flag"]
89    #[inline(always)]
90    pub fn arblost(&mut self) -> ARBLOST_W {
91        ARBLOST_W::new(self)
92    }
93    #[doc = "Bit 10 - Clear Bus Error Interrupt Flag"]
94    #[inline(always)]
95    pub fn buserr(&mut self) -> BUSERR_W {
96        BUSERR_W::new(self)
97    }
98    #[doc = "Bit 11 - Clear Bus Held Interrupt Flag"]
99    #[inline(always)]
100    pub fn bushold(&mut self) -> BUSHOLD_W {
101        BUSHOLD_W::new(self)
102    }
103    #[doc = "Bit 12 - Clear Transmit Buffer Overflow Interrupt Flag"]
104    #[inline(always)]
105    pub fn txof(&mut self) -> TXOF_W {
106        TXOF_W::new(self)
107    }
108    #[doc = "Bit 13 - Clear Receive Buffer Underflow Interrupt Flag"]
109    #[inline(always)]
110    pub fn rxuf(&mut self) -> RXUF_W {
111        RXUF_W::new(self)
112    }
113    #[doc = "Bit 14 - Clear Bus Idle Timeout Interrupt Flag"]
114    #[inline(always)]
115    pub fn bito(&mut self) -> BITO_W {
116        BITO_W::new(self)
117    }
118    #[doc = "Bit 15 - Clear Clock Low Interrupt Flag"]
119    #[inline(always)]
120    pub fn clto(&mut self) -> CLTO_W {
121        CLTO_W::new(self)
122    }
123    #[doc = "Bit 16 - Clear SSTOP Interrupt Flag"]
124    #[inline(always)]
125    pub fn sstop(&mut self) -> SSTOP_W {
126        SSTOP_W::new(self)
127    }
128    #[doc = "Writes raw bits to the register."]
129    #[inline(always)]
130    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
131        self.0.bits(bits);
132        self
133    }
134}
135#[doc = "Interrupt Flag Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifc](index.html) module"]
136pub struct IFC_SPEC;
137impl crate::RegisterSpec for IFC_SPEC {
138    type Ux = u32;
139}
140#[doc = "`write(|w| ..)` method takes [ifc::W](W) writer structure"]
141impl crate::Writable for IFC_SPEC {
142    type Writer = W;
143}
144#[doc = "`reset()` method sets IFC to value 0"]
145impl crate::Resettable for IFC_SPEC {
146    #[inline(always)]
147    fn reset_value() -> Self::Ux {
148        0
149    }
150}
efm32g230_pac/i2c0/ifc.rs

efm32g230_pac/i2c0/
ifc.rs
