efm32g230_pac/i2c0/
ien.rs

1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `START` reader - START Condition Interrupt Enable"]
38pub type START_R = crate::BitReader<bool>;
39#[doc = "Field `START` writer - START Condition Interrupt Enable"]
40pub type START_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 0>;
41#[doc = "Field `RSTART` reader - Repeated START condition Interrupt Enable"]
42pub type RSTART_R = crate::BitReader<bool>;
43#[doc = "Field `RSTART` writer - Repeated START condition Interrupt Enable"]
44pub type RSTART_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 1>;
45#[doc = "Field `ADDR` reader - Address Interrupt Enable"]
46pub type ADDR_R = crate::BitReader<bool>;
47#[doc = "Field `ADDR` writer - Address Interrupt Enable"]
48pub type ADDR_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 2>;
49#[doc = "Field `TXC` reader - Transfer Completed Interrupt Enable"]
50pub type TXC_R = crate::BitReader<bool>;
51#[doc = "Field `TXC` writer - Transfer Completed Interrupt Enable"]
52pub type TXC_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 3>;
53#[doc = "Field `TXBL` reader - Transmit Buffer level Interrupt Enable"]
54pub type TXBL_R = crate::BitReader<bool>;
55#[doc = "Field `TXBL` writer - Transmit Buffer level Interrupt Enable"]
56pub type TXBL_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 4>;
57#[doc = "Field `RXDATAV` reader - Receive Data Valid Interrupt Enable"]
58pub type RXDATAV_R = crate::BitReader<bool>;
59#[doc = "Field `RXDATAV` writer - Receive Data Valid Interrupt Enable"]
60pub type RXDATAV_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 5>;
61#[doc = "Field `ACK` reader - Acknowledge Received Interrupt Enable"]
62pub type ACK_R = crate::BitReader<bool>;
63#[doc = "Field `ACK` writer - Acknowledge Received Interrupt Enable"]
64pub type ACK_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 6>;
65#[doc = "Field `NACK` reader - Not Acknowledge Received Interrupt Enable"]
66pub type NACK_R = crate::BitReader<bool>;
67#[doc = "Field `NACK` writer - Not Acknowledge Received Interrupt Enable"]
68pub type NACK_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 7>;
69#[doc = "Field `MSTOP` reader - MSTOP Interrupt Enable"]
70pub type MSTOP_R = crate::BitReader<bool>;
71#[doc = "Field `MSTOP` writer - MSTOP Interrupt Enable"]
72pub type MSTOP_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 8>;
73#[doc = "Field `ARBLOST` reader - Arbitration Lost Interrupt Enable"]
74pub type ARBLOST_R = crate::BitReader<bool>;
75#[doc = "Field `ARBLOST` writer - Arbitration Lost Interrupt Enable"]
76pub type ARBLOST_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 9>;
77#[doc = "Field `BUSERR` reader - Bus Error Interrupt Enable"]
78pub type BUSERR_R = crate::BitReader<bool>;
79#[doc = "Field `BUSERR` writer - Bus Error Interrupt Enable"]
80pub type BUSERR_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 10>;
81#[doc = "Field `BUSHOLD` reader - Bus Held Interrupt Enable"]
82pub type BUSHOLD_R = crate::BitReader<bool>;
83#[doc = "Field `BUSHOLD` writer - Bus Held Interrupt Enable"]
84pub type BUSHOLD_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 11>;
85#[doc = "Field `TXOF` reader - Transmit Buffer Overflow Interrupt Enable"]
86pub type TXOF_R = crate::BitReader<bool>;
87#[doc = "Field `TXOF` writer - Transmit Buffer Overflow Interrupt Enable"]
88pub type TXOF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 12>;
89#[doc = "Field `RXUF` reader - Receive Buffer Underflow Interrupt Enable"]
90pub type RXUF_R = crate::BitReader<bool>;
91#[doc = "Field `RXUF` writer - Receive Buffer Underflow Interrupt Enable"]
92pub type RXUF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 13>;
93#[doc = "Field `BITO` reader - Bus Idle Timeout Interrupt Enable"]
94pub type BITO_R = crate::BitReader<bool>;
95#[doc = "Field `BITO` writer - Bus Idle Timeout Interrupt Enable"]
96pub type BITO_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 14>;
97#[doc = "Field `CLTO` reader - Clock Low Interrupt Enable"]
98pub type CLTO_R = crate::BitReader<bool>;
99#[doc = "Field `CLTO` writer - Clock Low Interrupt Enable"]
100pub type CLTO_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 15>;
101#[doc = "Field `SSTOP` reader - SSTOP Interrupt Enable"]
102pub type SSTOP_R = crate::BitReader<bool>;
103#[doc = "Field `SSTOP` writer - SSTOP Interrupt Enable"]
104pub type SSTOP_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 16>;
105impl R {
106    #[doc = "Bit 0 - START Condition Interrupt Enable"]
107    #[inline(always)]
108    pub fn start(&self) -> START_R {
109        START_R::new((self.bits & 1) != 0)
110    }
111    #[doc = "Bit 1 - Repeated START condition Interrupt Enable"]
112    #[inline(always)]
113    pub fn rstart(&self) -> RSTART_R {
114        RSTART_R::new(((self.bits >> 1) & 1) != 0)
115    }
116    #[doc = "Bit 2 - Address Interrupt Enable"]
117    #[inline(always)]
118    pub fn addr(&self) -> ADDR_R {
119        ADDR_R::new(((self.bits >> 2) & 1) != 0)
120    }
121    #[doc = "Bit 3 - Transfer Completed Interrupt Enable"]
122    #[inline(always)]
123    pub fn txc(&self) -> TXC_R {
124        TXC_R::new(((self.bits >> 3) & 1) != 0)
125    }
126    #[doc = "Bit 4 - Transmit Buffer level Interrupt Enable"]
127    #[inline(always)]
128    pub fn txbl(&self) -> TXBL_R {
129        TXBL_R::new(((self.bits >> 4) & 1) != 0)
130    }
131    #[doc = "Bit 5 - Receive Data Valid Interrupt Enable"]
132    #[inline(always)]
133    pub fn rxdatav(&self) -> RXDATAV_R {
134        RXDATAV_R::new(((self.bits >> 5) & 1) != 0)
135    }
136    #[doc = "Bit 6 - Acknowledge Received Interrupt Enable"]
137    #[inline(always)]
138    pub fn ack(&self) -> ACK_R {
139        ACK_R::new(((self.bits >> 6) & 1) != 0)
140    }
141    #[doc = "Bit 7 - Not Acknowledge Received Interrupt Enable"]
142    #[inline(always)]
143    pub fn nack(&self) -> NACK_R {
144        NACK_R::new(((self.bits >> 7) & 1) != 0)
145    }
146    #[doc = "Bit 8 - MSTOP Interrupt Enable"]
147    #[inline(always)]
148    pub fn mstop(&self) -> MSTOP_R {
149        MSTOP_R::new(((self.bits >> 8) & 1) != 0)
150    }
151    #[doc = "Bit 9 - Arbitration Lost Interrupt Enable"]
152    #[inline(always)]
153    pub fn arblost(&self) -> ARBLOST_R {
154        ARBLOST_R::new(((self.bits >> 9) & 1) != 0)
155    }
156    #[doc = "Bit 10 - Bus Error Interrupt Enable"]
157    #[inline(always)]
158    pub fn buserr(&self) -> BUSERR_R {
159        BUSERR_R::new(((self.bits >> 10) & 1) != 0)
160    }
161    #[doc = "Bit 11 - Bus Held Interrupt Enable"]
162    #[inline(always)]
163    pub fn bushold(&self) -> BUSHOLD_R {
164        BUSHOLD_R::new(((self.bits >> 11) & 1) != 0)
165    }
166    #[doc = "Bit 12 - Transmit Buffer Overflow Interrupt Enable"]
167    #[inline(always)]
168    pub fn txof(&self) -> TXOF_R {
169        TXOF_R::new(((self.bits >> 12) & 1) != 0)
170    }
171    #[doc = "Bit 13 - Receive Buffer Underflow Interrupt Enable"]
172    #[inline(always)]
173    pub fn rxuf(&self) -> RXUF_R {
174        RXUF_R::new(((self.bits >> 13) & 1) != 0)
175    }
176    #[doc = "Bit 14 - Bus Idle Timeout Interrupt Enable"]
177    #[inline(always)]
178    pub fn bito(&self) -> BITO_R {
179        BITO_R::new(((self.bits >> 14) & 1) != 0)
180    }
181    #[doc = "Bit 15 - Clock Low Interrupt Enable"]
182    #[inline(always)]
183    pub fn clto(&self) -> CLTO_R {
184        CLTO_R::new(((self.bits >> 15) & 1) != 0)
185    }
186    #[doc = "Bit 16 - SSTOP Interrupt Enable"]
187    #[inline(always)]
188    pub fn sstop(&self) -> SSTOP_R {
189        SSTOP_R::new(((self.bits >> 16) & 1) != 0)
190    }
191}
192impl W {
193    #[doc = "Bit 0 - START Condition Interrupt Enable"]
194    #[inline(always)]
195    pub fn start(&mut self) -> START_W {
196        START_W::new(self)
197    }
198    #[doc = "Bit 1 - Repeated START condition Interrupt Enable"]
199    #[inline(always)]
200    pub fn rstart(&mut self) -> RSTART_W {
201        RSTART_W::new(self)
202    }
203    #[doc = "Bit 2 - Address Interrupt Enable"]
204    #[inline(always)]
205    pub fn addr(&mut self) -> ADDR_W {
206        ADDR_W::new(self)
207    }
208    #[doc = "Bit 3 - Transfer Completed Interrupt Enable"]
209    #[inline(always)]
210    pub fn txc(&mut self) -> TXC_W {
211        TXC_W::new(self)
212    }
213    #[doc = "Bit 4 - Transmit Buffer level Interrupt Enable"]
214    #[inline(always)]
215    pub fn txbl(&mut self) -> TXBL_W {
216        TXBL_W::new(self)
217    }
218    #[doc = "Bit 5 - Receive Data Valid Interrupt Enable"]
219    #[inline(always)]
220    pub fn rxdatav(&mut self) -> RXDATAV_W {
221        RXDATAV_W::new(self)
222    }
223    #[doc = "Bit 6 - Acknowledge Received Interrupt Enable"]
224    #[inline(always)]
225    pub fn ack(&mut self) -> ACK_W {
226        ACK_W::new(self)
227    }
228    #[doc = "Bit 7 - Not Acknowledge Received Interrupt Enable"]
229    #[inline(always)]
230    pub fn nack(&mut self) -> NACK_W {
231        NACK_W::new(self)
232    }
233    #[doc = "Bit 8 - MSTOP Interrupt Enable"]
234    #[inline(always)]
235    pub fn mstop(&mut self) -> MSTOP_W {
236        MSTOP_W::new(self)
237    }
238    #[doc = "Bit 9 - Arbitration Lost Interrupt Enable"]
239    #[inline(always)]
240    pub fn arblost(&mut self) -> ARBLOST_W {
241        ARBLOST_W::new(self)
242    }
243    #[doc = "Bit 10 - Bus Error Interrupt Enable"]
244    #[inline(always)]
245    pub fn buserr(&mut self) -> BUSERR_W {
246        BUSERR_W::new(self)
247    }
248    #[doc = "Bit 11 - Bus Held Interrupt Enable"]
249    #[inline(always)]
250    pub fn bushold(&mut self) -> BUSHOLD_W {
251        BUSHOLD_W::new(self)
252    }
253    #[doc = "Bit 12 - Transmit Buffer Overflow Interrupt Enable"]
254    #[inline(always)]
255    pub fn txof(&mut self) -> TXOF_W {
256        TXOF_W::new(self)
257    }
258    #[doc = "Bit 13 - Receive Buffer Underflow Interrupt Enable"]
259    #[inline(always)]
260    pub fn rxuf(&mut self) -> RXUF_W {
261        RXUF_W::new(self)
262    }
263    #[doc = "Bit 14 - Bus Idle Timeout Interrupt Enable"]
264    #[inline(always)]
265    pub fn bito(&mut self) -> BITO_W {
266        BITO_W::new(self)
267    }
268    #[doc = "Bit 15 - Clock Low Interrupt Enable"]
269    #[inline(always)]
270    pub fn clto(&mut self) -> CLTO_W {
271        CLTO_W::new(self)
272    }
273    #[doc = "Bit 16 - SSTOP Interrupt Enable"]
274    #[inline(always)]
275    pub fn sstop(&mut self) -> SSTOP_W {
276        SSTOP_W::new(self)
277    }
278    #[doc = "Writes raw bits to the register."]
279    #[inline(always)]
280    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
281        self.0.bits(bits);
282        self
283    }
284}
285#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
286pub struct IEN_SPEC;
287impl crate::RegisterSpec for IEN_SPEC {
288    type Ux = u32;
289}
290#[doc = "`read()` method returns [ien::R](R) reader structure"]
291impl crate::Readable for IEN_SPEC {
292    type Reader = R;
293}
294#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
295impl crate::Writable for IEN_SPEC {
296    type Writer = W;
297}
298#[doc = "`reset()` method sets IEN to value 0"]
299impl crate::Resettable for IEN_SPEC {
300    #[inline(always)]
301    fn reset_value() -> Self::Ux {
302        0
303    }
304}
efm32g230_pac/i2c0/ien.rs

efm32g230_pac/i2c0/
ien.rs
