efm32g230_pac/dma/
ien.rs

1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CH0DONE` reader - DMA Channel 0 Complete Interrupt Enable"]
38pub type CH0DONE_R = crate::BitReader<bool>;
39#[doc = "Field `CH0DONE` writer - DMA Channel 0 Complete Interrupt Enable"]
40pub type CH0DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 0>;
41#[doc = "Field `CH1DONE` reader - DMA Channel 1 Complete Interrupt Enable"]
42pub type CH1DONE_R = crate::BitReader<bool>;
43#[doc = "Field `CH1DONE` writer - DMA Channel 1 Complete Interrupt Enable"]
44pub type CH1DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 1>;
45#[doc = "Field `CH2DONE` reader - DMA Channel 2 Complete Interrupt Enable"]
46pub type CH2DONE_R = crate::BitReader<bool>;
47#[doc = "Field `CH2DONE` writer - DMA Channel 2 Complete Interrupt Enable"]
48pub type CH2DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 2>;
49#[doc = "Field `CH3DONE` reader - DMA Channel 3 Complete Interrupt Enable"]
50pub type CH3DONE_R = crate::BitReader<bool>;
51#[doc = "Field `CH3DONE` writer - DMA Channel 3 Complete Interrupt Enable"]
52pub type CH3DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 3>;
53#[doc = "Field `CH4DONE` reader - DMA Channel 4 Complete Interrupt Enable"]
54pub type CH4DONE_R = crate::BitReader<bool>;
55#[doc = "Field `CH4DONE` writer - DMA Channel 4 Complete Interrupt Enable"]
56pub type CH4DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 4>;
57#[doc = "Field `CH5DONE` reader - DMA Channel 5 Complete Interrupt Enable"]
58pub type CH5DONE_R = crate::BitReader<bool>;
59#[doc = "Field `CH5DONE` writer - DMA Channel 5 Complete Interrupt Enable"]
60pub type CH5DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 5>;
61#[doc = "Field `CH6DONE` reader - DMA Channel 6 Complete Interrupt Enable"]
62pub type CH6DONE_R = crate::BitReader<bool>;
63#[doc = "Field `CH6DONE` writer - DMA Channel 6 Complete Interrupt Enable"]
64pub type CH6DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 6>;
65#[doc = "Field `CH7DONE` reader - DMA Channel 7 Complete Interrupt Enable"]
66pub type CH7DONE_R = crate::BitReader<bool>;
67#[doc = "Field `CH7DONE` writer - DMA Channel 7 Complete Interrupt Enable"]
68pub type CH7DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 7>;
69#[doc = "Field `ERR` reader - DMA Error Interrupt Flag Enable"]
70pub type ERR_R = crate::BitReader<bool>;
71#[doc = "Field `ERR` writer - DMA Error Interrupt Flag Enable"]
72pub type ERR_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 31>;
73impl R {
74    #[doc = "Bit 0 - DMA Channel 0 Complete Interrupt Enable"]
75    #[inline(always)]
76    pub fn ch0done(&self) -> CH0DONE_R {
77        CH0DONE_R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1 - DMA Channel 1 Complete Interrupt Enable"]
80    #[inline(always)]
81    pub fn ch1done(&self) -> CH1DONE_R {
82        CH1DONE_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 2 - DMA Channel 2 Complete Interrupt Enable"]
85    #[inline(always)]
86    pub fn ch2done(&self) -> CH2DONE_R {
87        CH2DONE_R::new(((self.bits >> 2) & 1) != 0)
88    }
89    #[doc = "Bit 3 - DMA Channel 3 Complete Interrupt Enable"]
90    #[inline(always)]
91    pub fn ch3done(&self) -> CH3DONE_R {
92        CH3DONE_R::new(((self.bits >> 3) & 1) != 0)
93    }
94    #[doc = "Bit 4 - DMA Channel 4 Complete Interrupt Enable"]
95    #[inline(always)]
96    pub fn ch4done(&self) -> CH4DONE_R {
97        CH4DONE_R::new(((self.bits >> 4) & 1) != 0)
98    }
99    #[doc = "Bit 5 - DMA Channel 5 Complete Interrupt Enable"]
100    #[inline(always)]
101    pub fn ch5done(&self) -> CH5DONE_R {
102        CH5DONE_R::new(((self.bits >> 5) & 1) != 0)
103    }
104    #[doc = "Bit 6 - DMA Channel 6 Complete Interrupt Enable"]
105    #[inline(always)]
106    pub fn ch6done(&self) -> CH6DONE_R {
107        CH6DONE_R::new(((self.bits >> 6) & 1) != 0)
108    }
109    #[doc = "Bit 7 - DMA Channel 7 Complete Interrupt Enable"]
110    #[inline(always)]
111    pub fn ch7done(&self) -> CH7DONE_R {
112        CH7DONE_R::new(((self.bits >> 7) & 1) != 0)
113    }
114    #[doc = "Bit 31 - DMA Error Interrupt Flag Enable"]
115    #[inline(always)]
116    pub fn err(&self) -> ERR_R {
117        ERR_R::new(((self.bits >> 31) & 1) != 0)
118    }
119}
120impl W {
121    #[doc = "Bit 0 - DMA Channel 0 Complete Interrupt Enable"]
122    #[inline(always)]
123    pub fn ch0done(&mut self) -> CH0DONE_W {
124        CH0DONE_W::new(self)
125    }
126    #[doc = "Bit 1 - DMA Channel 1 Complete Interrupt Enable"]
127    #[inline(always)]
128    pub fn ch1done(&mut self) -> CH1DONE_W {
129        CH1DONE_W::new(self)
130    }
131    #[doc = "Bit 2 - DMA Channel 2 Complete Interrupt Enable"]
132    #[inline(always)]
133    pub fn ch2done(&mut self) -> CH2DONE_W {
134        CH2DONE_W::new(self)
135    }
136    #[doc = "Bit 3 - DMA Channel 3 Complete Interrupt Enable"]
137    #[inline(always)]
138    pub fn ch3done(&mut self) -> CH3DONE_W {
139        CH3DONE_W::new(self)
140    }
141    #[doc = "Bit 4 - DMA Channel 4 Complete Interrupt Enable"]
142    #[inline(always)]
143    pub fn ch4done(&mut self) -> CH4DONE_W {
144        CH4DONE_W::new(self)
145    }
146    #[doc = "Bit 5 - DMA Channel 5 Complete Interrupt Enable"]
147    #[inline(always)]
148    pub fn ch5done(&mut self) -> CH5DONE_W {
149        CH5DONE_W::new(self)
150    }
151    #[doc = "Bit 6 - DMA Channel 6 Complete Interrupt Enable"]
152    #[inline(always)]
153    pub fn ch6done(&mut self) -> CH6DONE_W {
154        CH6DONE_W::new(self)
155    }
156    #[doc = "Bit 7 - DMA Channel 7 Complete Interrupt Enable"]
157    #[inline(always)]
158    pub fn ch7done(&mut self) -> CH7DONE_W {
159        CH7DONE_W::new(self)
160    }
161    #[doc = "Bit 31 - DMA Error Interrupt Flag Enable"]
162    #[inline(always)]
163    pub fn err(&mut self) -> ERR_W {
164        ERR_W::new(self)
165    }
166    #[doc = "Writes raw bits to the register."]
167    #[inline(always)]
168    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
169        self.0.bits(bits);
170        self
171    }
172}
173#[doc = "Interrupt Enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
174pub struct IEN_SPEC;
175impl crate::RegisterSpec for IEN_SPEC {
176    type Ux = u32;
177}
178#[doc = "`read()` method returns [ien::R](R) reader structure"]
179impl crate::Readable for IEN_SPEC {
180    type Reader = R;
181}
182#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
183impl crate::Writable for IEN_SPEC {
184    type Writer = W;
185}
186#[doc = "`reset()` method sets IEN to value 0"]
187impl crate::Resettable for IEN_SPEC {
188    #[inline(always)]
189    fn reset_value() -> Self::Ux {
190        0
191    }
192}
efm32g230_pac/dma/ien.rs

efm32g230_pac/dma/
ien.rs
