efm32g230_pac/dma/
chens.rs

1#[doc = "Register `CHENS` writer"]
2pub struct W(crate::W<CHENS_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHENS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHENS_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHENS_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CH0ENS` writer - Channel 0 Enable Set"]
23pub type CH0ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 0>;
24#[doc = "Field `CH1ENS` writer - Channel 1 Enable Set"]
25pub type CH1ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 1>;
26#[doc = "Field `CH2ENS` writer - Channel 2 Enable Set"]
27pub type CH2ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 2>;
28#[doc = "Field `CH3ENS` writer - Channel 3 Enable Set"]
29pub type CH3ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 3>;
30#[doc = "Field `CH4ENS` writer - Channel 4 Enable Set"]
31pub type CH4ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 4>;
32#[doc = "Field `CH5ENS` writer - Channel 5 Enable Set"]
33pub type CH5ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 5>;
34#[doc = "Field `CH6ENS` writer - Channel 6 Enable Set"]
35pub type CH6ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 6>;
36#[doc = "Field `CH7ENS` writer - Channel 7 Enable Set"]
37pub type CH7ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 7>;
38impl W {
39    #[doc = "Bit 0 - Channel 0 Enable Set"]
40    #[inline(always)]
41    pub fn ch0ens(&mut self) -> CH0ENS_W {
42        CH0ENS_W::new(self)
43    }
44    #[doc = "Bit 1 - Channel 1 Enable Set"]
45    #[inline(always)]
46    pub fn ch1ens(&mut self) -> CH1ENS_W {
47        CH1ENS_W::new(self)
48    }
49    #[doc = "Bit 2 - Channel 2 Enable Set"]
50    #[inline(always)]
51    pub fn ch2ens(&mut self) -> CH2ENS_W {
52        CH2ENS_W::new(self)
53    }
54    #[doc = "Bit 3 - Channel 3 Enable Set"]
55    #[inline(always)]
56    pub fn ch3ens(&mut self) -> CH3ENS_W {
57        CH3ENS_W::new(self)
58    }
59    #[doc = "Bit 4 - Channel 4 Enable Set"]
60    #[inline(always)]
61    pub fn ch4ens(&mut self) -> CH4ENS_W {
62        CH4ENS_W::new(self)
63    }
64    #[doc = "Bit 5 - Channel 5 Enable Set"]
65    #[inline(always)]
66    pub fn ch5ens(&mut self) -> CH5ENS_W {
67        CH5ENS_W::new(self)
68    }
69    #[doc = "Bit 6 - Channel 6 Enable Set"]
70    #[inline(always)]
71    pub fn ch6ens(&mut self) -> CH6ENS_W {
72        CH6ENS_W::new(self)
73    }
74    #[doc = "Bit 7 - Channel 7 Enable Set"]
75    #[inline(always)]
76    pub fn ch7ens(&mut self) -> CH7ENS_W {
77        CH7ENS_W::new(self)
78    }
79    #[doc = "Writes raw bits to the register."]
80    #[inline(always)]
81    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
82        self.0.bits(bits);
83        self
84    }
85}
86#[doc = "Channel Enable Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chens](index.html) module"]
87pub struct CHENS_SPEC;
88impl crate::RegisterSpec for CHENS_SPEC {
89    type Ux = u32;
90}
91#[doc = "`write(|w| ..)` method takes [chens::W](W) writer structure"]
92impl crate::Writable for CHENS_SPEC {
93    type Writer = W;
94}
95#[doc = "`reset()` method sets CHENS to value 0"]
96impl crate::Resettable for CHENS_SPEC {
97    #[inline(always)]
98    fn reset_value() -> Self::Ux {
99        0
100    }
101}
efm32g230_pac/dma/chens.rs

efm32g230_pac/dma/
chens.rs
