efm32g230_pac/dma/
chenc.rs

1#[doc = "Register `CHENC` writer"]
2pub struct W(crate::W<CHENC_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHENC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHENC_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHENC_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CH0ENC` writer - Channel 0 Enable Clear"]
23pub type CH0ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 0>;
24#[doc = "Field `CH1ENC` writer - Channel 1 Enable Clear"]
25pub type CH1ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 1>;
26#[doc = "Field `CH2ENC` writer - Channel 2 Enable Clear"]
27pub type CH2ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 2>;
28#[doc = "Field `CH3ENC` writer - Channel 3 Enable Clear"]
29pub type CH3ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 3>;
30#[doc = "Field `CH4ENC` writer - Channel 4 Enable Clear"]
31pub type CH4ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 4>;
32#[doc = "Field `CH5ENC` writer - Channel 5 Enable Clear"]
33pub type CH5ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 5>;
34#[doc = "Field `CH6ENC` writer - Channel 6 Enable Clear"]
35pub type CH6ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 6>;
36#[doc = "Field `CH7ENC` writer - Channel 7 Enable Clear"]
37pub type CH7ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 7>;
38impl W {
39    #[doc = "Bit 0 - Channel 0 Enable Clear"]
40    #[inline(always)]
41    pub fn ch0enc(&mut self) -> CH0ENC_W {
42        CH0ENC_W::new(self)
43    }
44    #[doc = "Bit 1 - Channel 1 Enable Clear"]
45    #[inline(always)]
46    pub fn ch1enc(&mut self) -> CH1ENC_W {
47        CH1ENC_W::new(self)
48    }
49    #[doc = "Bit 2 - Channel 2 Enable Clear"]
50    #[inline(always)]
51    pub fn ch2enc(&mut self) -> CH2ENC_W {
52        CH2ENC_W::new(self)
53    }
54    #[doc = "Bit 3 - Channel 3 Enable Clear"]
55    #[inline(always)]
56    pub fn ch3enc(&mut self) -> CH3ENC_W {
57        CH3ENC_W::new(self)
58    }
59    #[doc = "Bit 4 - Channel 4 Enable Clear"]
60    #[inline(always)]
61    pub fn ch4enc(&mut self) -> CH4ENC_W {
62        CH4ENC_W::new(self)
63    }
64    #[doc = "Bit 5 - Channel 5 Enable Clear"]
65    #[inline(always)]
66    pub fn ch5enc(&mut self) -> CH5ENC_W {
67        CH5ENC_W::new(self)
68    }
69    #[doc = "Bit 6 - Channel 6 Enable Clear"]
70    #[inline(always)]
71    pub fn ch6enc(&mut self) -> CH6ENC_W {
72        CH6ENC_W::new(self)
73    }
74    #[doc = "Bit 7 - Channel 7 Enable Clear"]
75    #[inline(always)]
76    pub fn ch7enc(&mut self) -> CH7ENC_W {
77        CH7ENC_W::new(self)
78    }
79    #[doc = "Writes raw bits to the register."]
80    #[inline(always)]
81    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
82        self.0.bits(bits);
83        self
84    }
85}
86#[doc = "Channel Enable Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chenc](index.html) module"]
87pub struct CHENC_SPEC;
88impl crate::RegisterSpec for CHENC_SPEC {
89    type Ux = u32;
90}
91#[doc = "`write(|w| ..)` method takes [chenc::W](W) writer structure"]
92impl crate::Writable for CHENC_SPEC {
93    type Writer = W;
94}
95#[doc = "`reset()` method sets CHENC to value 0"]
96impl crate::Resettable for CHENC_SPEC {
97    #[inline(always)]
98    fn reset_value() -> Self::Ux {
99        0
100    }
101}
efm32g230_pac/dma/chenc.rs

efm32g230_pac/dma/
chenc.rs
