efm32g230_pac/dac0/
ch0ctrl.rs1#[doc = "Register `CH0CTRL` reader"]
2pub struct R(crate::R<CH0CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CH0CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CH0CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CH0CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CH0CTRL` writer"]
17pub struct W(crate::W<CH0CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CH0CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CH0CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CH0CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `EN` reader - Channel 0 Enable"]
38pub type EN_R = crate::BitReader<bool>;
39#[doc = "Field `EN` writer - Channel 0 Enable"]
40pub type EN_W<'a> = crate::BitWriter<'a, u32, CH0CTRL_SPEC, bool, 0>;
41#[doc = "Field `REFREN` reader - Channel 0 Automatic Refresh Enable"]
42pub type REFREN_R = crate::BitReader<bool>;
43#[doc = "Field `REFREN` writer - Channel 0 Automatic Refresh Enable"]
44pub type REFREN_W<'a> = crate::BitWriter<'a, u32, CH0CTRL_SPEC, bool, 1>;
45#[doc = "Field `PRSEN` reader - Channel 0 PRS Trigger Enable"]
46pub type PRSEN_R = crate::BitReader<bool>;
47#[doc = "Field `PRSEN` writer - Channel 0 PRS Trigger Enable"]
48pub type PRSEN_W<'a> = crate::BitWriter<'a, u32, CH0CTRL_SPEC, bool, 2>;
49#[doc = "Channel 0 PRS Trigger Select\n\nValue on reset: 0"]
50#[derive(Clone, Copy, Debug, PartialEq)]
51#[repr(u8)]
52pub enum PRSSEL_A {
53 #[doc = "0: PRS ch 0 triggers channel 0 conversion."]
54 PRSCH0 = 0,
55 #[doc = "1: PRS ch 1 triggers channel 0 conversion."]
56 PRSCH1 = 1,
57 #[doc = "2: PRS ch 2 triggers channel 0 conversion."]
58 PRSCH2 = 2,
59 #[doc = "3: PRS ch 3 triggers channel 0 conversion."]
60 PRSCH3 = 3,
61 #[doc = "4: PRS ch 4 triggers channel 0 conversion."]
62 PRSCH4 = 4,
63 #[doc = "5: PRS ch 5 triggers channel 0 conversion."]
64 PRSCH5 = 5,
65 #[doc = "6: PRS ch 6 triggers channel 0 conversion."]
66 PRSCH6 = 6,
67 #[doc = "7: PRS ch 7 triggers channel 0 conversion."]
68 PRSCH7 = 7,
69}
70impl From<PRSSEL_A> for u8 {
71 #[inline(always)]
72 fn from(variant: PRSSEL_A) -> Self {
73 variant as _
74 }
75}
76#[doc = "Field `PRSSEL` reader - Channel 0 PRS Trigger Select"]
77pub type PRSSEL_R = crate::FieldReader<u8, PRSSEL_A>;
78impl PRSSEL_R {
79 #[doc = "Get enumerated values variant"]
80 #[inline(always)]
81 pub fn variant(&self) -> PRSSEL_A {
82 match self.bits {
83 0 => PRSSEL_A::PRSCH0,
84 1 => PRSSEL_A::PRSCH1,
85 2 => PRSSEL_A::PRSCH2,
86 3 => PRSSEL_A::PRSCH3,
87 4 => PRSSEL_A::PRSCH4,
88 5 => PRSSEL_A::PRSCH5,
89 6 => PRSSEL_A::PRSCH6,
90 7 => PRSSEL_A::PRSCH7,
91 _ => unreachable!(),
92 }
93 }
94 #[doc = "Checks if the value of the field is `PRSCH0`"]
95 #[inline(always)]
96 pub fn is_prsch0(&self) -> bool {
97 *self == PRSSEL_A::PRSCH0
98 }
99 #[doc = "Checks if the value of the field is `PRSCH1`"]
100 #[inline(always)]
101 pub fn is_prsch1(&self) -> bool {
102 *self == PRSSEL_A::PRSCH1
103 }
104 #[doc = "Checks if the value of the field is `PRSCH2`"]
105 #[inline(always)]
106 pub fn is_prsch2(&self) -> bool {
107 *self == PRSSEL_A::PRSCH2
108 }
109 #[doc = "Checks if the value of the field is `PRSCH3`"]
110 #[inline(always)]
111 pub fn is_prsch3(&self) -> bool {
112 *self == PRSSEL_A::PRSCH3
113 }
114 #[doc = "Checks if the value of the field is `PRSCH4`"]
115 #[inline(always)]
116 pub fn is_prsch4(&self) -> bool {
117 *self == PRSSEL_A::PRSCH4
118 }
119 #[doc = "Checks if the value of the field is `PRSCH5`"]
120 #[inline(always)]
121 pub fn is_prsch5(&self) -> bool {
122 *self == PRSSEL_A::PRSCH5
123 }
124 #[doc = "Checks if the value of the field is `PRSCH6`"]
125 #[inline(always)]
126 pub fn is_prsch6(&self) -> bool {
127 *self == PRSSEL_A::PRSCH6
128 }
129 #[doc = "Checks if the value of the field is `PRSCH7`"]
130 #[inline(always)]
131 pub fn is_prsch7(&self) -> bool {
132 *self == PRSSEL_A::PRSCH7
133 }
134}
135#[doc = "Field `PRSSEL` writer - Channel 0 PRS Trigger Select"]
136pub type PRSSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH0CTRL_SPEC, u8, PRSSEL_A, 3, 4>;
137impl<'a> PRSSEL_W<'a> {
138 #[doc = "PRS ch 0 triggers channel 0 conversion."]
139 #[inline(always)]
140 pub fn prsch0(self) -> &'a mut W {
141 self.variant(PRSSEL_A::PRSCH0)
142 }
143 #[doc = "PRS ch 1 triggers channel 0 conversion."]
144 #[inline(always)]
145 pub fn prsch1(self) -> &'a mut W {
146 self.variant(PRSSEL_A::PRSCH1)
147 }
148 #[doc = "PRS ch 2 triggers channel 0 conversion."]
149 #[inline(always)]
150 pub fn prsch2(self) -> &'a mut W {
151 self.variant(PRSSEL_A::PRSCH2)
152 }
153 #[doc = "PRS ch 3 triggers channel 0 conversion."]
154 #[inline(always)]
155 pub fn prsch3(self) -> &'a mut W {
156 self.variant(PRSSEL_A::PRSCH3)
157 }
158 #[doc = "PRS ch 4 triggers channel 0 conversion."]
159 #[inline(always)]
160 pub fn prsch4(self) -> &'a mut W {
161 self.variant(PRSSEL_A::PRSCH4)
162 }
163 #[doc = "PRS ch 5 triggers channel 0 conversion."]
164 #[inline(always)]
165 pub fn prsch5(self) -> &'a mut W {
166 self.variant(PRSSEL_A::PRSCH5)
167 }
168 #[doc = "PRS ch 6 triggers channel 0 conversion."]
169 #[inline(always)]
170 pub fn prsch6(self) -> &'a mut W {
171 self.variant(PRSSEL_A::PRSCH6)
172 }
173 #[doc = "PRS ch 7 triggers channel 0 conversion."]
174 #[inline(always)]
175 pub fn prsch7(self) -> &'a mut W {
176 self.variant(PRSSEL_A::PRSCH7)
177 }
178}
179impl R {
180 #[doc = "Bit 0 - Channel 0 Enable"]
181 #[inline(always)]
182 pub fn en(&self) -> EN_R {
183 EN_R::new((self.bits & 1) != 0)
184 }
185 #[doc = "Bit 1 - Channel 0 Automatic Refresh Enable"]
186 #[inline(always)]
187 pub fn refren(&self) -> REFREN_R {
188 REFREN_R::new(((self.bits >> 1) & 1) != 0)
189 }
190 #[doc = "Bit 2 - Channel 0 PRS Trigger Enable"]
191 #[inline(always)]
192 pub fn prsen(&self) -> PRSEN_R {
193 PRSEN_R::new(((self.bits >> 2) & 1) != 0)
194 }
195 #[doc = "Bits 4:6 - Channel 0 PRS Trigger Select"]
196 #[inline(always)]
197 pub fn prssel(&self) -> PRSSEL_R {
198 PRSSEL_R::new(((self.bits >> 4) & 7) as u8)
199 }
200}
201impl W {
202 #[doc = "Bit 0 - Channel 0 Enable"]
203 #[inline(always)]
204 pub fn en(&mut self) -> EN_W {
205 EN_W::new(self)
206 }
207 #[doc = "Bit 1 - Channel 0 Automatic Refresh Enable"]
208 #[inline(always)]
209 pub fn refren(&mut self) -> REFREN_W {
210 REFREN_W::new(self)
211 }
212 #[doc = "Bit 2 - Channel 0 PRS Trigger Enable"]
213 #[inline(always)]
214 pub fn prsen(&mut self) -> PRSEN_W {
215 PRSEN_W::new(self)
216 }
217 #[doc = "Bits 4:6 - Channel 0 PRS Trigger Select"]
218 #[inline(always)]
219 pub fn prssel(&mut self) -> PRSSEL_W {
220 PRSSEL_W::new(self)
221 }
222 #[doc = "Writes raw bits to the register."]
223 #[inline(always)]
224 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
225 self.0.bits(bits);
226 self
227 }
228}
229#[doc = "Channel 0 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch0ctrl](index.html) module"]
230pub struct CH0CTRL_SPEC;
231impl crate::RegisterSpec for CH0CTRL_SPEC {
232 type Ux = u32;
233}
234#[doc = "`read()` method returns [ch0ctrl::R](R) reader structure"]
235impl crate::Readable for CH0CTRL_SPEC {
236 type Reader = R;
237}
238#[doc = "`write(|w| ..)` method takes [ch0ctrl::W](W) writer structure"]
239impl crate::Writable for CH0CTRL_SPEC {
240 type Writer = W;
241}
242#[doc = "`reset()` method sets CH0CTRL to value 0"]
243impl crate::Resettable for CH0CTRL_SPEC {
244 #[inline(always)]
245 fn reset_value() -> Self::Ux {
246 0
247 }
248}