efm32g230_pac/cmu/
lfclksel.rs

1#[doc = "Register `LFCLKSEL` reader"]
2pub struct R(crate::R<LFCLKSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<LFCLKSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<LFCLKSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<LFCLKSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `LFCLKSEL` writer"]
17pub struct W(crate::W<LFCLKSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<LFCLKSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<LFCLKSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<LFCLKSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Clock Select for LFA\n\nValue on reset: 1"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum LFA_A {
41    #[doc = "0: LFACLK is disabled"]
42    DISABLED = 0,
43    #[doc = "1: LFRCO selected as LFACLK"]
44    LFRCO = 1,
45    #[doc = "2: LFXO selected as LFACLK"]
46    LFXO = 2,
47    #[doc = "3: HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV."]
48    HFCORECLKLEDIV2 = 3,
49}
50impl From<LFA_A> for u8 {
51    #[inline(always)]
52    fn from(variant: LFA_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `LFA` reader - Clock Select for LFA"]
57pub type LFA_R = crate::FieldReader<u8, LFA_A>;
58impl LFA_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> LFA_A {
62        match self.bits {
63            0 => LFA_A::DISABLED,
64            1 => LFA_A::LFRCO,
65            2 => LFA_A::LFXO,
66            3 => LFA_A::HFCORECLKLEDIV2,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `DISABLED`"]
71    #[inline(always)]
72    pub fn is_disabled(&self) -> bool {
73        *self == LFA_A::DISABLED
74    }
75    #[doc = "Checks if the value of the field is `LFRCO`"]
76    #[inline(always)]
77    pub fn is_lfrco(&self) -> bool {
78        *self == LFA_A::LFRCO
79    }
80    #[doc = "Checks if the value of the field is `LFXO`"]
81    #[inline(always)]
82    pub fn is_lfxo(&self) -> bool {
83        *self == LFA_A::LFXO
84    }
85    #[doc = "Checks if the value of the field is `HFCORECLKLEDIV2`"]
86    #[inline(always)]
87    pub fn is_hfcoreclklediv2(&self) -> bool {
88        *self == LFA_A::HFCORECLKLEDIV2
89    }
90}
91#[doc = "Field `LFA` writer - Clock Select for LFA"]
92pub type LFA_W<'a> = crate::FieldWriterSafe<'a, u32, LFCLKSEL_SPEC, u8, LFA_A, 2, 0>;
93impl<'a> LFA_W<'a> {
94    #[doc = "LFACLK is disabled"]
95    #[inline(always)]
96    pub fn disabled(self) -> &'a mut W {
97        self.variant(LFA_A::DISABLED)
98    }
99    #[doc = "LFRCO selected as LFACLK"]
100    #[inline(always)]
101    pub fn lfrco(self) -> &'a mut W {
102        self.variant(LFA_A::LFRCO)
103    }
104    #[doc = "LFXO selected as LFACLK"]
105    #[inline(always)]
106    pub fn lfxo(self) -> &'a mut W {
107        self.variant(LFA_A::LFXO)
108    }
109    #[doc = "HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV."]
110    #[inline(always)]
111    pub fn hfcoreclklediv2(self) -> &'a mut W {
112        self.variant(LFA_A::HFCORECLKLEDIV2)
113    }
114}
115#[doc = "Clock Select for LFB\n\nValue on reset: 1"]
116#[derive(Clone, Copy, Debug, PartialEq)]
117#[repr(u8)]
118pub enum LFB_A {
119    #[doc = "0: LFBCLK is disabled"]
120    DISABLED = 0,
121    #[doc = "1: LFRCO selected as LFBCLK"]
122    LFRCO = 1,
123    #[doc = "2: LFXO selected as LFBCLK"]
124    LFXO = 2,
125    #[doc = "3: HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV."]
126    HFCORECLKLEDIV2 = 3,
127}
128impl From<LFB_A> for u8 {
129    #[inline(always)]
130    fn from(variant: LFB_A) -> Self {
131        variant as _
132    }
133}
134#[doc = "Field `LFB` reader - Clock Select for LFB"]
135pub type LFB_R = crate::FieldReader<u8, LFB_A>;
136impl LFB_R {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub fn variant(&self) -> LFB_A {
140        match self.bits {
141            0 => LFB_A::DISABLED,
142            1 => LFB_A::LFRCO,
143            2 => LFB_A::LFXO,
144            3 => LFB_A::HFCORECLKLEDIV2,
145            _ => unreachable!(),
146        }
147    }
148    #[doc = "Checks if the value of the field is `DISABLED`"]
149    #[inline(always)]
150    pub fn is_disabled(&self) -> bool {
151        *self == LFB_A::DISABLED
152    }
153    #[doc = "Checks if the value of the field is `LFRCO`"]
154    #[inline(always)]
155    pub fn is_lfrco(&self) -> bool {
156        *self == LFB_A::LFRCO
157    }
158    #[doc = "Checks if the value of the field is `LFXO`"]
159    #[inline(always)]
160    pub fn is_lfxo(&self) -> bool {
161        *self == LFB_A::LFXO
162    }
163    #[doc = "Checks if the value of the field is `HFCORECLKLEDIV2`"]
164    #[inline(always)]
165    pub fn is_hfcoreclklediv2(&self) -> bool {
166        *self == LFB_A::HFCORECLKLEDIV2
167    }
168}
169#[doc = "Field `LFB` writer - Clock Select for LFB"]
170pub type LFB_W<'a> = crate::FieldWriterSafe<'a, u32, LFCLKSEL_SPEC, u8, LFB_A, 2, 2>;
171impl<'a> LFB_W<'a> {
172    #[doc = "LFBCLK is disabled"]
173    #[inline(always)]
174    pub fn disabled(self) -> &'a mut W {
175        self.variant(LFB_A::DISABLED)
176    }
177    #[doc = "LFRCO selected as LFBCLK"]
178    #[inline(always)]
179    pub fn lfrco(self) -> &'a mut W {
180        self.variant(LFB_A::LFRCO)
181    }
182    #[doc = "LFXO selected as LFBCLK"]
183    #[inline(always)]
184    pub fn lfxo(self) -> &'a mut W {
185        self.variant(LFB_A::LFXO)
186    }
187    #[doc = "HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV."]
188    #[inline(always)]
189    pub fn hfcoreclklediv2(self) -> &'a mut W {
190        self.variant(LFB_A::HFCORECLKLEDIV2)
191    }
192}
193impl R {
194    #[doc = "Bits 0:1 - Clock Select for LFA"]
195    #[inline(always)]
196    pub fn lfa(&self) -> LFA_R {
197        LFA_R::new((self.bits & 3) as u8)
198    }
199    #[doc = "Bits 2:3 - Clock Select for LFB"]
200    #[inline(always)]
201    pub fn lfb(&self) -> LFB_R {
202        LFB_R::new(((self.bits >> 2) & 3) as u8)
203    }
204}
205impl W {
206    #[doc = "Bits 0:1 - Clock Select for LFA"]
207    #[inline(always)]
208    pub fn lfa(&mut self) -> LFA_W {
209        LFA_W::new(self)
210    }
211    #[doc = "Bits 2:3 - Clock Select for LFB"]
212    #[inline(always)]
213    pub fn lfb(&mut self) -> LFB_W {
214        LFB_W::new(self)
215    }
216    #[doc = "Writes raw bits to the register."]
217    #[inline(always)]
218    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
219        self.0.bits(bits);
220        self
221    }
222}
223#[doc = "Low Frequency Clock Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclksel](index.html) module"]
224pub struct LFCLKSEL_SPEC;
225impl crate::RegisterSpec for LFCLKSEL_SPEC {
226    type Ux = u32;
227}
228#[doc = "`read()` method returns [lfclksel::R](R) reader structure"]
229impl crate::Readable for LFCLKSEL_SPEC {
230    type Reader = R;
231}
232#[doc = "`write(|w| ..)` method takes [lfclksel::W](W) writer structure"]
233impl crate::Writable for LFCLKSEL_SPEC {
234    type Writer = W;
235}
236#[doc = "`reset()` method sets LFCLKSEL to value 0x05"]
237impl crate::Resettable for LFCLKSEL_SPEC {
238    #[inline(always)]
239    fn reset_value() -> Self::Ux {
240        0x05
241    }
242}
efm32g230_pac/cmu/lfclksel.rs

efm32g230_pac/cmu/
lfclksel.rs
