efm32g230_pac/cmu/
hfperclken0.rs1#[doc = "Register `HFPERCLKEN0` reader"]
2pub struct R(crate::R<HFPERCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HFPERCLKEN0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HFPERCLKEN0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HFPERCLKEN0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HFPERCLKEN0` writer"]
17pub struct W(crate::W<HFPERCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HFPERCLKEN0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HFPERCLKEN0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HFPERCLKEN0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
38pub type USART0_R = crate::BitReader<bool>;
39#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
40pub type USART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
42pub type USART1_R = crate::BitReader<bool>;
43#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
44pub type USART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
46pub type USART2_R = crate::BitReader<bool>;
47#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
48pub type USART2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `TIMER0` reader - Timer 0 Clock Enable"]
50pub type TIMER0_R = crate::BitReader<bool>;
51#[doc = "Field `TIMER0` writer - Timer 0 Clock Enable"]
52pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 4>;
53#[doc = "Field `TIMER1` reader - Timer 1 Clock Enable"]
54pub type TIMER1_R = crate::BitReader<bool>;
55#[doc = "Field `TIMER1` writer - Timer 1 Clock Enable"]
56pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 5>;
57#[doc = "Field `TIMER2` reader - Timer 2 Clock Enable"]
58pub type TIMER2_R = crate::BitReader<bool>;
59#[doc = "Field `TIMER2` writer - Timer 2 Clock Enable"]
60pub type TIMER2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 6>;
61#[doc = "Field `ACMP0` reader - Analog Comparator 0 Clock Enable"]
62pub type ACMP0_R = crate::BitReader<bool>;
63#[doc = "Field `ACMP0` writer - Analog Comparator 0 Clock Enable"]
64pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 7>;
65#[doc = "Field `ACMP1` reader - Analog Comparator 1 Clock Enable"]
66pub type ACMP1_R = crate::BitReader<bool>;
67#[doc = "Field `ACMP1` writer - Analog Comparator 1 Clock Enable"]
68pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 8>;
69#[doc = "Field `PRS` reader - Peripheral Reflex System Clock Enable"]
70pub type PRS_R = crate::BitReader<bool>;
71#[doc = "Field `PRS` writer - Peripheral Reflex System Clock Enable"]
72pub type PRS_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 10>;
73#[doc = "Field `DAC0` reader - Digital to Analog Converter 0 Clock Enable"]
74pub type DAC0_R = crate::BitReader<bool>;
75#[doc = "Field `DAC0` writer - Digital to Analog Converter 0 Clock Enable"]
76pub type DAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 11>;
77#[doc = "Field `GPIO` reader - General purpose Input/Output Clock Enable"]
78pub type GPIO_R = crate::BitReader<bool>;
79#[doc = "Field `GPIO` writer - General purpose Input/Output Clock Enable"]
80pub type GPIO_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 12>;
81#[doc = "Field `VCMP` reader - Voltage Comparator Clock Enable"]
82pub type VCMP_R = crate::BitReader<bool>;
83#[doc = "Field `VCMP` writer - Voltage Comparator Clock Enable"]
84pub type VCMP_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 13>;
85#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 Clock Enable"]
86pub type ADC0_R = crate::BitReader<bool>;
87#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 Clock Enable"]
88pub type ADC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 14>;
89#[doc = "Field `I2C0` reader - I2C 0 Clock Enable"]
90pub type I2C0_R = crate::BitReader<bool>;
91#[doc = "Field `I2C0` writer - I2C 0 Clock Enable"]
92pub type I2C0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 15>;
93impl R {
94 #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
95 #[inline(always)]
96 pub fn usart0(&self) -> USART0_R {
97 USART0_R::new((self.bits & 1) != 0)
98 }
99 #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
100 #[inline(always)]
101 pub fn usart1(&self) -> USART1_R {
102 USART1_R::new(((self.bits >> 1) & 1) != 0)
103 }
104 #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
105 #[inline(always)]
106 pub fn usart2(&self) -> USART2_R {
107 USART2_R::new(((self.bits >> 2) & 1) != 0)
108 }
109 #[doc = "Bit 4 - Timer 0 Clock Enable"]
110 #[inline(always)]
111 pub fn timer0(&self) -> TIMER0_R {
112 TIMER0_R::new(((self.bits >> 4) & 1) != 0)
113 }
114 #[doc = "Bit 5 - Timer 1 Clock Enable"]
115 #[inline(always)]
116 pub fn timer1(&self) -> TIMER1_R {
117 TIMER1_R::new(((self.bits >> 5) & 1) != 0)
118 }
119 #[doc = "Bit 6 - Timer 2 Clock Enable"]
120 #[inline(always)]
121 pub fn timer2(&self) -> TIMER2_R {
122 TIMER2_R::new(((self.bits >> 6) & 1) != 0)
123 }
124 #[doc = "Bit 7 - Analog Comparator 0 Clock Enable"]
125 #[inline(always)]
126 pub fn acmp0(&self) -> ACMP0_R {
127 ACMP0_R::new(((self.bits >> 7) & 1) != 0)
128 }
129 #[doc = "Bit 8 - Analog Comparator 1 Clock Enable"]
130 #[inline(always)]
131 pub fn acmp1(&self) -> ACMP1_R {
132 ACMP1_R::new(((self.bits >> 8) & 1) != 0)
133 }
134 #[doc = "Bit 10 - Peripheral Reflex System Clock Enable"]
135 #[inline(always)]
136 pub fn prs(&self) -> PRS_R {
137 PRS_R::new(((self.bits >> 10) & 1) != 0)
138 }
139 #[doc = "Bit 11 - Digital to Analog Converter 0 Clock Enable"]
140 #[inline(always)]
141 pub fn dac0(&self) -> DAC0_R {
142 DAC0_R::new(((self.bits >> 11) & 1) != 0)
143 }
144 #[doc = "Bit 12 - General purpose Input/Output Clock Enable"]
145 #[inline(always)]
146 pub fn gpio(&self) -> GPIO_R {
147 GPIO_R::new(((self.bits >> 12) & 1) != 0)
148 }
149 #[doc = "Bit 13 - Voltage Comparator Clock Enable"]
150 #[inline(always)]
151 pub fn vcmp(&self) -> VCMP_R {
152 VCMP_R::new(((self.bits >> 13) & 1) != 0)
153 }
154 #[doc = "Bit 14 - Analog to Digital Converter 0 Clock Enable"]
155 #[inline(always)]
156 pub fn adc0(&self) -> ADC0_R {
157 ADC0_R::new(((self.bits >> 14) & 1) != 0)
158 }
159 #[doc = "Bit 15 - I2C 0 Clock Enable"]
160 #[inline(always)]
161 pub fn i2c0(&self) -> I2C0_R {
162 I2C0_R::new(((self.bits >> 15) & 1) != 0)
163 }
164}
165impl W {
166 #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
167 #[inline(always)]
168 pub fn usart0(&mut self) -> USART0_W {
169 USART0_W::new(self)
170 }
171 #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
172 #[inline(always)]
173 pub fn usart1(&mut self) -> USART1_W {
174 USART1_W::new(self)
175 }
176 #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
177 #[inline(always)]
178 pub fn usart2(&mut self) -> USART2_W {
179 USART2_W::new(self)
180 }
181 #[doc = "Bit 4 - Timer 0 Clock Enable"]
182 #[inline(always)]
183 pub fn timer0(&mut self) -> TIMER0_W {
184 TIMER0_W::new(self)
185 }
186 #[doc = "Bit 5 - Timer 1 Clock Enable"]
187 #[inline(always)]
188 pub fn timer1(&mut self) -> TIMER1_W {
189 TIMER1_W::new(self)
190 }
191 #[doc = "Bit 6 - Timer 2 Clock Enable"]
192 #[inline(always)]
193 pub fn timer2(&mut self) -> TIMER2_W {
194 TIMER2_W::new(self)
195 }
196 #[doc = "Bit 7 - Analog Comparator 0 Clock Enable"]
197 #[inline(always)]
198 pub fn acmp0(&mut self) -> ACMP0_W {
199 ACMP0_W::new(self)
200 }
201 #[doc = "Bit 8 - Analog Comparator 1 Clock Enable"]
202 #[inline(always)]
203 pub fn acmp1(&mut self) -> ACMP1_W {
204 ACMP1_W::new(self)
205 }
206 #[doc = "Bit 10 - Peripheral Reflex System Clock Enable"]
207 #[inline(always)]
208 pub fn prs(&mut self) -> PRS_W {
209 PRS_W::new(self)
210 }
211 #[doc = "Bit 11 - Digital to Analog Converter 0 Clock Enable"]
212 #[inline(always)]
213 pub fn dac0(&mut self) -> DAC0_W {
214 DAC0_W::new(self)
215 }
216 #[doc = "Bit 12 - General purpose Input/Output Clock Enable"]
217 #[inline(always)]
218 pub fn gpio(&mut self) -> GPIO_W {
219 GPIO_W::new(self)
220 }
221 #[doc = "Bit 13 - Voltage Comparator Clock Enable"]
222 #[inline(always)]
223 pub fn vcmp(&mut self) -> VCMP_W {
224 VCMP_W::new(self)
225 }
226 #[doc = "Bit 14 - Analog to Digital Converter 0 Clock Enable"]
227 #[inline(always)]
228 pub fn adc0(&mut self) -> ADC0_W {
229 ADC0_W::new(self)
230 }
231 #[doc = "Bit 15 - I2C 0 Clock Enable"]
232 #[inline(always)]
233 pub fn i2c0(&mut self) -> I2C0_W {
234 I2C0_W::new(self)
235 }
236 #[doc = "Writes raw bits to the register."]
237 #[inline(always)]
238 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
239 self.0.bits(bits);
240 self
241 }
242}
243#[doc = "High Frequency Peripheral Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken0](index.html) module"]
244pub struct HFPERCLKEN0_SPEC;
245impl crate::RegisterSpec for HFPERCLKEN0_SPEC {
246 type Ux = u32;
247}
248#[doc = "`read()` method returns [hfperclken0::R](R) reader structure"]
249impl crate::Readable for HFPERCLKEN0_SPEC {
250 type Reader = R;
251}
252#[doc = "`write(|w| ..)` method takes [hfperclken0::W](W) writer structure"]
253impl crate::Writable for HFPERCLKEN0_SPEC {
254 type Writer = W;
255}
256#[doc = "`reset()` method sets HFPERCLKEN0 to value 0"]
257impl crate::Resettable for HFPERCLKEN0_SPEC {
258 #[inline(always)]
259 fn reset_value() -> Self::Ux {
260 0
261 }
262}