efm32g230_pac/cmu/
hfcoreclkdiv.rs

1#[doc = "Register `HFCORECLKDIV` reader"]
2pub struct R(crate::R<HFCORECLKDIV_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFCORECLKDIV_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFCORECLKDIV_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFCORECLKDIV_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFCORECLKDIV` writer"]
17pub struct W(crate::W<HFCORECLKDIV_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFCORECLKDIV_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFCORECLKDIV_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFCORECLKDIV_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "HFCORECLK Divider\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum HFCORECLKDIV_A {
41    #[doc = "0: HFCORECLK = HFCLK."]
42    HFCLK = 0,
43    #[doc = "1: HFCORECLK = HFCLK/2."]
44    HFCLK2 = 1,
45    #[doc = "2: HFCORECLK = HFCLK/4."]
46    HFCLK4 = 2,
47    #[doc = "3: HFCORECLK = HFCLK/8."]
48    HFCLK8 = 3,
49    #[doc = "4: HFCORECLK = HFCLK/16."]
50    HFCLK16 = 4,
51    #[doc = "5: HFCORECLK = HFCLK/32."]
52    HFCLK32 = 5,
53    #[doc = "6: HFCORECLK = HFCLK/64."]
54    HFCLK64 = 6,
55    #[doc = "7: HFCORECLK = HFCLK/128."]
56    HFCLK128 = 7,
57    #[doc = "8: HFCORECLK = HFCLK/256."]
58    HFCLK256 = 8,
59    #[doc = "9: HFCORECLK = HFCLK/512."]
60    HFCLK512 = 9,
61}
62impl From<HFCORECLKDIV_A> for u8 {
63    #[inline(always)]
64    fn from(variant: HFCORECLKDIV_A) -> Self {
65        variant as _
66    }
67}
68#[doc = "Field `HFCORECLKDIV` reader - HFCORECLK Divider"]
69pub type HFCORECLKDIV_R = crate::FieldReader<u8, HFCORECLKDIV_A>;
70impl HFCORECLKDIV_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> Option<HFCORECLKDIV_A> {
74        match self.bits {
75            0 => Some(HFCORECLKDIV_A::HFCLK),
76            1 => Some(HFCORECLKDIV_A::HFCLK2),
77            2 => Some(HFCORECLKDIV_A::HFCLK4),
78            3 => Some(HFCORECLKDIV_A::HFCLK8),
79            4 => Some(HFCORECLKDIV_A::HFCLK16),
80            5 => Some(HFCORECLKDIV_A::HFCLK32),
81            6 => Some(HFCORECLKDIV_A::HFCLK64),
82            7 => Some(HFCORECLKDIV_A::HFCLK128),
83            8 => Some(HFCORECLKDIV_A::HFCLK256),
84            9 => Some(HFCORECLKDIV_A::HFCLK512),
85            _ => None,
86        }
87    }
88    #[doc = "Checks if the value of the field is `HFCLK`"]
89    #[inline(always)]
90    pub fn is_hfclk(&self) -> bool {
91        *self == HFCORECLKDIV_A::HFCLK
92    }
93    #[doc = "Checks if the value of the field is `HFCLK2`"]
94    #[inline(always)]
95    pub fn is_hfclk2(&self) -> bool {
96        *self == HFCORECLKDIV_A::HFCLK2
97    }
98    #[doc = "Checks if the value of the field is `HFCLK4`"]
99    #[inline(always)]
100    pub fn is_hfclk4(&self) -> bool {
101        *self == HFCORECLKDIV_A::HFCLK4
102    }
103    #[doc = "Checks if the value of the field is `HFCLK8`"]
104    #[inline(always)]
105    pub fn is_hfclk8(&self) -> bool {
106        *self == HFCORECLKDIV_A::HFCLK8
107    }
108    #[doc = "Checks if the value of the field is `HFCLK16`"]
109    #[inline(always)]
110    pub fn is_hfclk16(&self) -> bool {
111        *self == HFCORECLKDIV_A::HFCLK16
112    }
113    #[doc = "Checks if the value of the field is `HFCLK32`"]
114    #[inline(always)]
115    pub fn is_hfclk32(&self) -> bool {
116        *self == HFCORECLKDIV_A::HFCLK32
117    }
118    #[doc = "Checks if the value of the field is `HFCLK64`"]
119    #[inline(always)]
120    pub fn is_hfclk64(&self) -> bool {
121        *self == HFCORECLKDIV_A::HFCLK64
122    }
123    #[doc = "Checks if the value of the field is `HFCLK128`"]
124    #[inline(always)]
125    pub fn is_hfclk128(&self) -> bool {
126        *self == HFCORECLKDIV_A::HFCLK128
127    }
128    #[doc = "Checks if the value of the field is `HFCLK256`"]
129    #[inline(always)]
130    pub fn is_hfclk256(&self) -> bool {
131        *self == HFCORECLKDIV_A::HFCLK256
132    }
133    #[doc = "Checks if the value of the field is `HFCLK512`"]
134    #[inline(always)]
135    pub fn is_hfclk512(&self) -> bool {
136        *self == HFCORECLKDIV_A::HFCLK512
137    }
138}
139#[doc = "Field `HFCORECLKDIV` writer - HFCORECLK Divider"]
140pub type HFCORECLKDIV_W<'a> =
141    crate::FieldWriter<'a, u32, HFCORECLKDIV_SPEC, u8, HFCORECLKDIV_A, 4, 0>;
142impl<'a> HFCORECLKDIV_W<'a> {
143    #[doc = "HFCORECLK = HFCLK."]
144    #[inline(always)]
145    pub fn hfclk(self) -> &'a mut W {
146        self.variant(HFCORECLKDIV_A::HFCLK)
147    }
148    #[doc = "HFCORECLK = HFCLK/2."]
149    #[inline(always)]
150    pub fn hfclk2(self) -> &'a mut W {
151        self.variant(HFCORECLKDIV_A::HFCLK2)
152    }
153    #[doc = "HFCORECLK = HFCLK/4."]
154    #[inline(always)]
155    pub fn hfclk4(self) -> &'a mut W {
156        self.variant(HFCORECLKDIV_A::HFCLK4)
157    }
158    #[doc = "HFCORECLK = HFCLK/8."]
159    #[inline(always)]
160    pub fn hfclk8(self) -> &'a mut W {
161        self.variant(HFCORECLKDIV_A::HFCLK8)
162    }
163    #[doc = "HFCORECLK = HFCLK/16."]
164    #[inline(always)]
165    pub fn hfclk16(self) -> &'a mut W {
166        self.variant(HFCORECLKDIV_A::HFCLK16)
167    }
168    #[doc = "HFCORECLK = HFCLK/32."]
169    #[inline(always)]
170    pub fn hfclk32(self) -> &'a mut W {
171        self.variant(HFCORECLKDIV_A::HFCLK32)
172    }
173    #[doc = "HFCORECLK = HFCLK/64."]
174    #[inline(always)]
175    pub fn hfclk64(self) -> &'a mut W {
176        self.variant(HFCORECLKDIV_A::HFCLK64)
177    }
178    #[doc = "HFCORECLK = HFCLK/128."]
179    #[inline(always)]
180    pub fn hfclk128(self) -> &'a mut W {
181        self.variant(HFCORECLKDIV_A::HFCLK128)
182    }
183    #[doc = "HFCORECLK = HFCLK/256."]
184    #[inline(always)]
185    pub fn hfclk256(self) -> &'a mut W {
186        self.variant(HFCORECLKDIV_A::HFCLK256)
187    }
188    #[doc = "HFCORECLK = HFCLK/512."]
189    #[inline(always)]
190    pub fn hfclk512(self) -> &'a mut W {
191        self.variant(HFCORECLKDIV_A::HFCLK512)
192    }
193}
194impl R {
195    #[doc = "Bits 0:3 - HFCORECLK Divider"]
196    #[inline(always)]
197    pub fn hfcoreclkdiv(&self) -> HFCORECLKDIV_R {
198        HFCORECLKDIV_R::new((self.bits & 0x0f) as u8)
199    }
200}
201impl W {
202    #[doc = "Bits 0:3 - HFCORECLK Divider"]
203    #[inline(always)]
204    pub fn hfcoreclkdiv(&mut self) -> HFCORECLKDIV_W {
205        HFCORECLKDIV_W::new(self)
206    }
207    #[doc = "Writes raw bits to the register."]
208    #[inline(always)]
209    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
210        self.0.bits(bits);
211        self
212    }
213}
214#[doc = "High Frequency Core Clock Division Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfcoreclkdiv](index.html) module"]
215pub struct HFCORECLKDIV_SPEC;
216impl crate::RegisterSpec for HFCORECLKDIV_SPEC {
217    type Ux = u32;
218}
219#[doc = "`read()` method returns [hfcoreclkdiv::R](R) reader structure"]
220impl crate::Readable for HFCORECLKDIV_SPEC {
221    type Reader = R;
222}
223#[doc = "`write(|w| ..)` method takes [hfcoreclkdiv::W](W) writer structure"]
224impl crate::Writable for HFCORECLKDIV_SPEC {
225    type Writer = W;
226}
227#[doc = "`reset()` method sets HFCORECLKDIV to value 0"]
228impl crate::Resettable for HFCORECLKDIV_SPEC {
229    #[inline(always)]
230    fn reset_value() -> Self::Ux {
231        0
232    }
233}
efm32g230_pac/cmu/hfcoreclkdiv.rs

efm32g230_pac/cmu/
hfcoreclkdiv.rs
