efm32g230_pac/msc/
ifc.rs

1#[doc = "Register `IFC` writer"]
2pub struct W(crate::W<IFC_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IFC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IFC_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IFC_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `ERASE` writer - Erase Done Interrupt Clear"]
23pub type ERASE_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 0>;
24#[doc = "Field `WRITE` writer - Write Done Interrupt Clear"]
25pub type WRITE_W<'a> = crate::BitWriter<'a, u32, IFC_SPEC, bool, 1>;
26impl W {
27    #[doc = "Bit 0 - Erase Done Interrupt Clear"]
28    #[inline(always)]
29    pub fn erase(&mut self) -> ERASE_W {
30        ERASE_W::new(self)
31    }
32    #[doc = "Bit 1 - Write Done Interrupt Clear"]
33    #[inline(always)]
34    pub fn write(&mut self) -> WRITE_W {
35        WRITE_W::new(self)
36    }
37    #[doc = "Writes raw bits to the register."]
38    #[inline(always)]
39    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
40        self.0.bits(bits);
41        self
42    }
43}
44#[doc = "Interrupt Flag Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifc](index.html) module"]
45pub struct IFC_SPEC;
46impl crate::RegisterSpec for IFC_SPEC {
47    type Ux = u32;
48}
49#[doc = "`write(|w| ..)` method takes [ifc::W](W) writer structure"]
50impl crate::Writable for IFC_SPEC {
51    type Writer = W;
52}
53#[doc = "`reset()` method sets IFC to value 0"]
54impl crate::Resettable for IFC_SPEC {
55    #[inline(always)]
56    fn reset_value() -> Self::Ux {
57        0
58    }
59}
efm32g230_pac/msc/ifc.rs

efm32g230_pac/msc/
ifc.rs
