efm32g230_pac/dma/
ch3_ctrl.rs

1#[doc = "Register `CH3_CTRL` reader"]
2pub struct R(crate::R<CH3_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH3_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH3_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH3_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH3_CTRL` writer"]
17pub struct W(crate::W<CH3_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH3_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH3_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH3_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH3_CTRL_SPEC, u8, u8, 4, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "8: Analog to Digital Converter 0"]
48    ADC0 = 8,
49    #[doc = "10: Digital to Analog Converter 0"]
50    DAC0 = 10,
51    #[doc = "12: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
52    USART0 = 12,
53    #[doc = "13: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
54    USART1 = 13,
55    #[doc = "14: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
56    USART2 = 14,
57    #[doc = "16: Low Energy UART 0"]
58    LEUART0 = 16,
59    #[doc = "17: Low Energy UART 1"]
60    LEUART1 = 17,
61    #[doc = "20: I2C 0"]
62    I2C0 = 20,
63    #[doc = "24: Timer 0"]
64    TIMER0 = 24,
65    #[doc = "25: Timer 1"]
66    TIMER1 = 25,
67    #[doc = "26: Timer 2"]
68    TIMER2 = 26,
69    #[doc = "48: `110000`"]
70    MSC = 48,
71    #[doc = "49: Advanced Encryption Standard Accelerator"]
72    AES = 49,
73}
74impl From<SOURCESEL_A> for u8 {
75    #[inline(always)]
76    fn from(variant: SOURCESEL_A) -> Self {
77        variant as _
78    }
79}
80#[doc = "Field `SOURCESEL` reader - Source Select"]
81pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
82impl SOURCESEL_R {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub fn variant(&self) -> Option<SOURCESEL_A> {
86        match self.bits {
87            0 => Some(SOURCESEL_A::NONE),
88            8 => Some(SOURCESEL_A::ADC0),
89            10 => Some(SOURCESEL_A::DAC0),
90            12 => Some(SOURCESEL_A::USART0),
91            13 => Some(SOURCESEL_A::USART1),
92            14 => Some(SOURCESEL_A::USART2),
93            16 => Some(SOURCESEL_A::LEUART0),
94            17 => Some(SOURCESEL_A::LEUART1),
95            20 => Some(SOURCESEL_A::I2C0),
96            24 => Some(SOURCESEL_A::TIMER0),
97            25 => Some(SOURCESEL_A::TIMER1),
98            26 => Some(SOURCESEL_A::TIMER2),
99            48 => Some(SOURCESEL_A::MSC),
100            49 => Some(SOURCESEL_A::AES),
101            _ => None,
102        }
103    }
104    #[doc = "Checks if the value of the field is `NONE`"]
105    #[inline(always)]
106    pub fn is_none(&self) -> bool {
107        *self == SOURCESEL_A::NONE
108    }
109    #[doc = "Checks if the value of the field is `ADC0`"]
110    #[inline(always)]
111    pub fn is_adc0(&self) -> bool {
112        *self == SOURCESEL_A::ADC0
113    }
114    #[doc = "Checks if the value of the field is `DAC0`"]
115    #[inline(always)]
116    pub fn is_dac0(&self) -> bool {
117        *self == SOURCESEL_A::DAC0
118    }
119    #[doc = "Checks if the value of the field is `USART0`"]
120    #[inline(always)]
121    pub fn is_usart0(&self) -> bool {
122        *self == SOURCESEL_A::USART0
123    }
124    #[doc = "Checks if the value of the field is `USART1`"]
125    #[inline(always)]
126    pub fn is_usart1(&self) -> bool {
127        *self == SOURCESEL_A::USART1
128    }
129    #[doc = "Checks if the value of the field is `USART2`"]
130    #[inline(always)]
131    pub fn is_usart2(&self) -> bool {
132        *self == SOURCESEL_A::USART2
133    }
134    #[doc = "Checks if the value of the field is `LEUART0`"]
135    #[inline(always)]
136    pub fn is_leuart0(&self) -> bool {
137        *self == SOURCESEL_A::LEUART0
138    }
139    #[doc = "Checks if the value of the field is `LEUART1`"]
140    #[inline(always)]
141    pub fn is_leuart1(&self) -> bool {
142        *self == SOURCESEL_A::LEUART1
143    }
144    #[doc = "Checks if the value of the field is `I2C0`"]
145    #[inline(always)]
146    pub fn is_i2c0(&self) -> bool {
147        *self == SOURCESEL_A::I2C0
148    }
149    #[doc = "Checks if the value of the field is `TIMER0`"]
150    #[inline(always)]
151    pub fn is_timer0(&self) -> bool {
152        *self == SOURCESEL_A::TIMER0
153    }
154    #[doc = "Checks if the value of the field is `TIMER1`"]
155    #[inline(always)]
156    pub fn is_timer1(&self) -> bool {
157        *self == SOURCESEL_A::TIMER1
158    }
159    #[doc = "Checks if the value of the field is `TIMER2`"]
160    #[inline(always)]
161    pub fn is_timer2(&self) -> bool {
162        *self == SOURCESEL_A::TIMER2
163    }
164    #[doc = "Checks if the value of the field is `MSC`"]
165    #[inline(always)]
166    pub fn is_msc(&self) -> bool {
167        *self == SOURCESEL_A::MSC
168    }
169    #[doc = "Checks if the value of the field is `AES`"]
170    #[inline(always)]
171    pub fn is_aes(&self) -> bool {
172        *self == SOURCESEL_A::AES
173    }
174}
175#[doc = "Field `SOURCESEL` writer - Source Select"]
176pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH3_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
177impl<'a> SOURCESEL_W<'a> {
178    #[doc = "No source selected"]
179    #[inline(always)]
180    pub fn none(self) -> &'a mut W {
181        self.variant(SOURCESEL_A::NONE)
182    }
183    #[doc = "Analog to Digital Converter 0"]
184    #[inline(always)]
185    pub fn adc0(self) -> &'a mut W {
186        self.variant(SOURCESEL_A::ADC0)
187    }
188    #[doc = "Digital to Analog Converter 0"]
189    #[inline(always)]
190    pub fn dac0(self) -> &'a mut W {
191        self.variant(SOURCESEL_A::DAC0)
192    }
193    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
194    #[inline(always)]
195    pub fn usart0(self) -> &'a mut W {
196        self.variant(SOURCESEL_A::USART0)
197    }
198    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
199    #[inline(always)]
200    pub fn usart1(self) -> &'a mut W {
201        self.variant(SOURCESEL_A::USART1)
202    }
203    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
204    #[inline(always)]
205    pub fn usart2(self) -> &'a mut W {
206        self.variant(SOURCESEL_A::USART2)
207    }
208    #[doc = "Low Energy UART 0"]
209    #[inline(always)]
210    pub fn leuart0(self) -> &'a mut W {
211        self.variant(SOURCESEL_A::LEUART0)
212    }
213    #[doc = "Low Energy UART 1"]
214    #[inline(always)]
215    pub fn leuart1(self) -> &'a mut W {
216        self.variant(SOURCESEL_A::LEUART1)
217    }
218    #[doc = "I2C 0"]
219    #[inline(always)]
220    pub fn i2c0(self) -> &'a mut W {
221        self.variant(SOURCESEL_A::I2C0)
222    }
223    #[doc = "Timer 0"]
224    #[inline(always)]
225    pub fn timer0(self) -> &'a mut W {
226        self.variant(SOURCESEL_A::TIMER0)
227    }
228    #[doc = "Timer 1"]
229    #[inline(always)]
230    pub fn timer1(self) -> &'a mut W {
231        self.variant(SOURCESEL_A::TIMER1)
232    }
233    #[doc = "Timer 2"]
234    #[inline(always)]
235    pub fn timer2(self) -> &'a mut W {
236        self.variant(SOURCESEL_A::TIMER2)
237    }
238    #[doc = "`110000`"]
239    #[inline(always)]
240    pub fn msc(self) -> &'a mut W {
241        self.variant(SOURCESEL_A::MSC)
242    }
243    #[doc = "Advanced Encryption Standard Accelerator"]
244    #[inline(always)]
245    pub fn aes(self) -> &'a mut W {
246        self.variant(SOURCESEL_A::AES)
247    }
248}
249impl R {
250    #[doc = "Bits 0:3 - Signal Select"]
251    #[inline(always)]
252    pub fn sigsel(&self) -> SIGSEL_R {
253        SIGSEL_R::new((self.bits & 0x0f) as u8)
254    }
255    #[doc = "Bits 16:21 - Source Select"]
256    #[inline(always)]
257    pub fn sourcesel(&self) -> SOURCESEL_R {
258        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
259    }
260}
261impl W {
262    #[doc = "Bits 0:3 - Signal Select"]
263    #[inline(always)]
264    pub fn sigsel(&mut self) -> SIGSEL_W {
265        SIGSEL_W::new(self)
266    }
267    #[doc = "Bits 16:21 - Source Select"]
268    #[inline(always)]
269    pub fn sourcesel(&mut self) -> SOURCESEL_W {
270        SOURCESEL_W::new(self)
271    }
272    #[doc = "Writes raw bits to the register."]
273    #[inline(always)]
274    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
275        self.0.bits(bits);
276        self
277    }
278}
279#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch3_ctrl](index.html) module"]
280pub struct CH3_CTRL_SPEC;
281impl crate::RegisterSpec for CH3_CTRL_SPEC {
282    type Ux = u32;
283}
284#[doc = "`read()` method returns [ch3_ctrl::R](R) reader structure"]
285impl crate::Readable for CH3_CTRL_SPEC {
286    type Reader = R;
287}
288#[doc = "`write(|w| ..)` method takes [ch3_ctrl::W](W) writer structure"]
289impl crate::Writable for CH3_CTRL_SPEC {
290    type Writer = W;
291}
292#[doc = "`reset()` method sets CH3_CTRL to value 0"]
293impl crate::Resettable for CH3_CTRL_SPEC {
294    #[inline(always)]
295    fn reset_value() -> Self::Ux {
296        0
297    }
298}
efm32g230_pac/dma/ch3_ctrl.rs

efm32g230_pac/dma/
ch3_ctrl.rs
