1mod data;
2mod operand;
3
4use std::{ascii, cmp::Ordering, collections::HashMap};
5
6use eeric_core::{
7 fuse,
8 prelude::{format::*, *},
9};
10use operand::{csr, float, integer, vector};
11use Instruction::*;
12
13pub struct Decoder;
14
15#[derive(Clone)]
16pub enum Section {
17 Data,
18 Text,
19}
20
21pub enum Data {
22 Byte(Vec<u8>),
23 Half(Vec<u16>),
24 Word(Vec<u32>),
25 Quad(Vec<u64>),
26 Float(Vec<f32>),
27 Double(Vec<f64>),
28 Ascii(Vec<ascii::Char>),
29 Zero(usize),
30}
31
32impl From<Data> for Vec<u8> {
33 fn from(val: Data) -> Self {
34 match val {
35 Data::Byte(bytes) => bytes,
36 Data::Half(halves) => halves.into_iter().flat_map(u16::to_le_bytes).collect(),
37 Data::Word(words) => words.into_iter().flat_map(u32::to_le_bytes).collect(),
38 Data::Quad(quads) => quads.into_iter().flat_map(u64::to_le_bytes).collect(),
39 Data::Float(floats) => floats.into_iter().flat_map(f32::to_le_bytes).collect(),
40 Data::Double(doubles) => doubles.into_iter().flat_map(f64::to_le_bytes).collect(),
41 Data::Ascii(string) => string.into_iter().map(|char| char as u8).collect(),
42 Data::Zero(length) => std::iter::repeat(0).take(length).collect(),
43 }
44 }
45}
46
47pub enum AssemblerDirective {
48 Section(Section),
49 Data(Data),
50}
51pub enum PreprocDirective {
52 Define(String, String),
53}
54
55pub enum LineClassification {
56 AssemblerDirective(AssemblerDirective),
57 PreprocDirective(PreprocDirective),
58 Instruction(String),
59 Label(String),
60 Empty,
61}
62
63impl Decoder {
64 pub fn classify(line: &str) -> Result<LineClassification, String> {
65 let trimmed_line = line.split('#').next().unwrap_or("").trim();
66
67 Ok(if trimmed_line.is_empty() {
68 LineClassification::Empty
69 } else if trimmed_line.starts_with('#') {
70 match trimmed_line {
71 "#define" => return Err("#define directive not supported yet".to_owned()),
72 _ => {
73 return Err(format!(
74 "Unrecognized preprocessor directive: {}",
75 trimmed_line
76 ))
77 }
78 }
79 } else if let Some(label) = trimmed_line.strip_suffix(':') {
80 if !label.contains(' ') {
81 LineClassification::Label(label.to_string())
82 } else {
83 return Err(format!("Label {} cannot have whitespaces", label));
84 }
85 } else if trimmed_line.starts_with('.') {
86 match trimmed_line {
87 ".section .data" | ".data" => LineClassification::AssemblerDirective(
88 AssemblerDirective::Section(Section::Data),
89 ),
90 ".section .text" | ".text" => LineClassification::AssemblerDirective(
91 AssemblerDirective::Section(Section::Text),
92 ),
93 _ => LineClassification::AssemblerDirective(AssemblerDirective::Data(
94 Self::decode_data_section(trimmed_line)?,
95 )),
96 }
97 } else {
98 LineClassification::Instruction(trimmed_line.to_string())
99 })
100 }
101
102 pub fn decode_text_section(
103 instruction_line: &str,
104 instruction_labels: &HashMap<String, usize>,
105 memory_labels: &HashMap<String, usize>,
106 current_address: usize,
107 ) -> Result<Instruction, String> {
108 let (mnemonic, op) = Self::split_instruction(instruction_line);
109
110 use integer::{
111 parse_branch_format as b, parse_i_format as i, parse_load_format as l,
112 parse_r_format as r, parse_s_format as s, parse_u_format as u,
113 };
114
115 use csr::{parse_csri_format as csri, parse_csrr_format as csrr};
116
117 use float::{
118 parse_load_format as fl, parse_r4_format as r4, parse_r_format as fr,
119 parse_r_single_reg_format as frs, parse_r_single_reg_to_f_format as frs_to_f,
120 parse_r_single_reg_to_x_format as frs_to_x, parse_r_to_x_format as frx,
121 parse_store_format as fs,
122 };
123
124 use vector::{
125 parse_opfvf_fma_format as opfvf_fma, parse_opfvf_format as opfvf,
126 parse_opfvv_fma_format as opfvv_fma, parse_opfvv_format as opfvv,
127 parse_opivi_format as opivi, parse_opivi_maskless_format as opivi_maskless,
128 parse_opivi_v0_format as opivi_v0, parse_opivi_vmv_format as opivi_vmv,
129 parse_opivv_format as opivv, parse_opivv_maskless_format as opivv_maskless,
130 parse_opivv_v0_format as opivv_v0, parse_opivv_vmv_format as opivv_vmv,
131 parse_opivx_format as opivx, parse_opivx_maskless_format as opivx_maskless,
132 parse_opivx_v0_format as opivx_v0, parse_opivx_vmv_format as opivx_vmv,
133 parse_opmvv_fma_format as opmvv_fma, parse_opmvv_format as opmvv,
134 parse_opmvv_maskless_format as opmvv_maskless, parse_opmvx_fma_format as opmvx_fma,
135 parse_opmvx_format as opmvx, parse_vfunary0_format as vfunary0,
136 parse_vfunary1_format as vfunary1, parse_vl_format as vl, parse_vlm_format as vlm,
137 parse_vlr_format as vlr, parse_vls_format as vls, parse_vlx_format as vlx,
138 parse_vmunary0_format as vmunary0, parse_vmunary0_vidv_format as vidv,
139 parse_vrfunary0_format as vrfunary0, parse_vrxunary0_format as vrxunary0,
140 parse_vs_format as vs, parse_vsetivli_format as vsetivli,
141 parse_vsetvl_format as vsetvl, parse_vsetvli_format as vsetvli,
142 parse_vsm_format as vsm, parse_vsr_format as vsr, parse_vss_format as vss,
143 parse_vsx_format as vsx, parse_vwfunary0_format as vwfunary0,
144 parse_vwxunary0_format as vwxunary0, parse_vwxunary0_vmvxs_format as vmvxs,
145 parse_vxunary0_format as vxunary0,
146 };
147
148 let instruction = match Self::rename(mnemonic) {
149 "add" => Add(r(op)?),
150 "addw" => Addw(r(op)?),
151 "sub" => Sub(r(op)?),
152 "subw" => Subw(r(op)?),
153 "addi" => Addi(i(op)?),
154 "addiw" => Addiw(i(op)?),
155 "slt" => Slt(r(op)?),
156 "slti" => Slti(i(op)?),
157 "sltu" => Sltu(r(op)?),
158 "sltiu" => Sltiu(i(op)?),
159 "lui" => Lui(u(op)?),
160 "auipc" => Auipc(u(op)?),
161
162 "and" => And(r(op)?),
163 "or" => Or(r(op)?),
164 "xor" => Xor(r(op)?),
165 "andi" => Andi(i(op)?),
166 "ori" => Ori(i(op)?),
167 "xori" => Xori(i(op)?),
168 "sll" => Sll(r(op)?),
169 "sllw" => Sllw(r(op)?),
170 "srl" => Srl(r(op)?),
171 "srlw" => Srlw(r(op)?),
172 "sra" => Sra(r(op)?),
173 "sraw" => Sraw(r(op)?),
174 "slli" => Slli(i(op)?),
175 "slliw" => Slliw(i(op)?),
176 "srli" => Srli(i(op)?),
177 "srliw" => Srliw(i(op)?),
178 "srai" => Srai(i(op)?),
179 "sraiw" => Sraiw(i(op)?),
180
181 "ld" => Ld(l(op, memory_labels)?),
182 "lw" => Lw(l(op, memory_labels)?),
183 "lh" => Lh(l(op, memory_labels)?),
184 "lb" => Lb(l(op, memory_labels)?),
185 "lwu" => Lwu(l(op, memory_labels)?),
186 "lhu" => Lhu(l(op, memory_labels)?),
187 "lbu" => Lbu(l(op, memory_labels)?),
188 "sd" => Sd(s(op, memory_labels)?),
189 "sw" => Sw(s(op, memory_labels)?),
190 "sh" => Sh(s(op, memory_labels)?),
191 "sb" => Sb(s(op, memory_labels)?),
192
193 "beq" => Beq(b(op, instruction_labels, current_address)?),
194 "bne" => Bne(b(op, instruction_labels, current_address)?),
195 "bge" => Bge(b(op, instruction_labels, current_address)?),
196 "bgeu" => Bgeu(b(op, instruction_labels, current_address)?),
197 "blt" => Blt(b(op, instruction_labels, current_address)?),
198 "bltu" => Bltu(b(op, instruction_labels, current_address)?),
199 "jal" => match u(op) {
200 Ok(instruction) => Jal(instruction),
201 Err(fst_err) => {
202 match integer::pseudo::parse_label_format(
203 op,
204 instruction_labels,
205 current_address,
206 ) {
207 Ok(diff) => Jal(U { rd: 1, imm20: diff }),
208 Err(snd_err) => return Err(format!("{} or {}", fst_err, snd_err)),
209 }
210 }
211 },
212 "jalr" => match l(op, memory_labels) {
213 Ok(instruction) => Jalr(instruction),
214 Err(fst_err) => match integer::pseudo::parse_op_format(op) {
215 Ok(rs1) => Jalr(I {
216 rd: 1,
217 rs1,
218 imm12: 0,
219 }),
220 Err(snd_err) => return Err(format!("{} or {}", fst_err, snd_err)),
221 },
222 },
223
224 "csrrw" => Csrrw(csrr(op)?),
225 "csrrs" => Csrrs(csrr(op)?),
226 "csrrc" => Csrrc(csrr(op)?),
227 "csrrwi" => Csrrwi(csri(op)?),
228 "csrrsi" => Csrrsi(csri(op)?),
229 "csrrci" => Csrrci(csri(op)?),
230
231 "mul" => Mul(r(op)?),
232 "mulh" => Mulh(r(op)?),
233 "mulhsu" => Mulhsu(r(op)?),
234 "mulhu" => Mulhu(r(op)?),
235 "div" => Div(r(op)?),
236 "divu" => Divu(r(op)?),
237 "rem" => Rem(r(op)?),
238 "remu" => Remu(r(op)?),
239 "mulw" => Mulw(r(op)?),
240 "divw" => Divw(r(op)?),
241 "divuw" => Divuw(r(op)?),
242 "remw" => Remw(r(op)?),
243 "remuw" => Remuw(r(op)?),
244
245 "flw" => Flw(fl(op, memory_labels)?),
246 "fsw" => Fsw(fs(op, memory_labels)?),
247 "fmadd.s" => Fmadds(r4(op)?),
248 "fmsub.s" => Fmsubs(r4(op)?),
249 "fnmsub.s" => Fnmsubs(r4(op)?),
250 "fnmadd.s" => Fnmadds(r4(op)?),
251 "fadd.s" => Fadds(fr(op)?),
252 "fsub.s" => Fsubs(fr(op)?),
253 "fmul.s" => Fmuls(fr(op)?),
254 "fdiv.s" => Fdivs(frs(op)?),
255 "fsqrt.s" => Fsqrts(fr(op)?),
256 "fsgnj.s" => Fsgnjs(fr(op)?),
257 "fsgnjn.s" => Fsgnjns(fr(op)?),
258 "fsgnjx.s" => Fsgnjxs(fr(op)?),
259 "fmin.s" => Fmins(fr(op)?),
260 "fmax.s" => Fmaxs(fr(op)?),
261 "fcvt.w.s" => Fcvtws(frs_to_x(op)?),
262 "fcvt.wu.s" => Fcvtwus(frs_to_x(op)?),
263 "fmv.x.w" => Fmvxw(frs_to_x(op)?),
264 "feq.s" => Feqs(frx(op)?),
265 "flt.s" => Flts(frx(op)?),
266 "fle.s" => Fles(frx(op)?),
267 "fclass.s" => Fclasss(frs_to_x(op)?),
268 "fcvt.s.w" => Fcvtsw(frs_to_f(op)?),
269 "fcvt.s.wu" => Fcvtswu(frs_to_f(op)?),
270 "fmv.w.x" => Fmvwx(frs_to_f(op)?),
271 "fcvt.l.s" => Fcvtls(frs_to_x(op)?),
272 "fcvt.lu.s" => Fcvtlus(frs_to_x(op)?),
273 "fcvt.s.l" => Fcvtsl(frs_to_f(op)?),
274 "fcvt.s.lu" => Fcvtslu(frs_to_f(op)?),
275
276 "fld" => Fld(fl(op, memory_labels)?),
277 "fsd" => Fsd(fs(op, memory_labels)?),
278 "fmadd.d" => Fmaddd(r4(op)?),
279 "fmsub.d" => Fmsubd(r4(op)?),
280 "fnmsub.d" => Fnmsubd(r4(op)?),
281 "fnmadd.d" => Fnmaddd(r4(op)?),
282 "fadd.d" => Faddd(fr(op)?),
283 "fsub.d" => Fsubd(fr(op)?),
284 "fmul.d" => Fmuld(fr(op)?),
285 "fdiv.d" => Fdivd(frs(op)?),
286 "fsqrt.d" => Fsqrtd(fr(op)?),
287 "fsgnj.d" => Fsgnjd(fr(op)?),
288 "fsgnjn.d" => Fsgnjnd(fr(op)?),
289 "fsgnjx.d" => Fsgnjxd(fr(op)?),
290 "fmin.d" => Fmind(fr(op)?),
291 "fmax.d" => Fmaxd(fr(op)?),
292 "fcvt.s.d" => Fcvtsd(fr(op)?),
293 "fcvt.d.s" => Fcvtds(fr(op)?),
294 "feq.d" => Feqd(frx(op)?),
295 "flt.d" => Fltd(frx(op)?),
296 "fle.d" => Fled(frx(op)?),
297 "fclass.d" => Fclassd(frs_to_x(op)?),
298 "fcvt.w.d" => Fcvtwd(frs_to_x(op)?),
299 "fcvt.wu.d" => Fcvtwud(frs_to_x(op)?),
300 "fcvt.d.w" => Fcvtdw(frs_to_f(op)?),
301 "fcvt.d.wu" => Fcvtdwu(frs_to_f(op)?),
302 "fcvt.l.d" => Fcvtld(frs_to_x(op)?),
303 "fcvt.lu.d" => Fcvtlud(frs_to_x(op)?),
304 "fmv.x.d" => Fmvxd(frs_to_x(op)?),
305 "fcvt.d.l" => Fcvtdl(frs_to_f(op)?),
306 "fcvt.d.lu" => Fcvtdlu(frs_to_f(op)?),
307 "fmv.d.x" => Fmvdx(frs_to_f(op)?),
308
309 "vsetvli" => Vsetvli(vsetvli(op)?),
310 "vsetivli" => Vsetivli(vsetivli(op)?),
311 "vsetvl" => Vsetvl(vsetvl(op)?),
312
313 "vle8.v" => Vlv {
314 eew: BaseSew::E8,
315 data: vl(op)?,
316 },
317 "vle16.v" => Vlv {
318 eew: BaseSew::E16,
319 data: vl(op)?,
320 },
321 "vle32.v" => Vlv {
322 eew: BaseSew::E32,
323 data: vl(op)?,
324 },
325 "vle64.v" => Vlv {
326 eew: BaseSew::E64,
327 data: vl(op)?,
328 },
329
330 "vse8.v" => Vsv {
331 eew: BaseSew::E8,
332 data: vs(op)?,
333 },
334 "vse16.v" => Vsv {
335 eew: BaseSew::E16,
336 data: vs(op)?,
337 },
338 "vse32.v" => Vsv {
339 eew: BaseSew::E32,
340 data: vs(op)?,
341 },
342 "vse64.v" => Vsv {
343 eew: BaseSew::E64,
344 data: vs(op)?,
345 },
346
347 "vlm.v" => Vlmv(vlm(op)?),
348 "vsm.v" => Vsmv(vsm(op)?),
349
350 "vlse8.v" => Vlsv {
351 eew: BaseSew::E8,
352 data: vls(op)?,
353 },
354 "vlse16.v" => Vlsv {
355 eew: BaseSew::E16,
356 data: vls(op)?,
357 },
358 "vlse32.v" => Vlsv {
359 eew: BaseSew::E32,
360 data: vls(op)?,
361 },
362 "vlse64.v" => Vlsv {
363 eew: BaseSew::E64,
364 data: vls(op)?,
365 },
366
367 "vsse8.v" => Vssv {
368 eew: BaseSew::E8,
369 data: vss(op)?,
370 },
371 "vsse16.v" => Vssv {
372 eew: BaseSew::E16,
373 data: vss(op)?,
374 },
375 "vsse32.v" => Vssv {
376 eew: BaseSew::E32,
377 data: vss(op)?,
378 },
379 "vsse64.v" => Vssv {
380 eew: BaseSew::E64,
381 data: vss(op)?,
382 },
383
384 "vluxei8.v" => Vluxv {
385 eew: BaseSew::E8,
386 data: vlx(op)?,
387 },
388 "vluxei16.v" => Vluxv {
389 eew: BaseSew::E16,
390 data: vlx(op)?,
391 },
392 "vluxei32.v" => Vluxv {
393 eew: BaseSew::E32,
394 data: vlx(op)?,
395 },
396 "vluxei64.v" => Vluxv {
397 eew: BaseSew::E64,
398 data: vlx(op)?,
399 },
400
401 "vloxei8.v" => Vloxv {
402 eew: BaseSew::E8,
403 data: vlx(op)?,
404 },
405 "vloxei16.v" => Vloxv {
406 eew: BaseSew::E16,
407 data: vlx(op)?,
408 },
409 "vloxei32.v" => Vloxv {
410 eew: BaseSew::E32,
411 data: vlx(op)?,
412 },
413 "vloxei64.v" => Vloxv {
414 eew: BaseSew::E64,
415 data: vlx(op)?,
416 },
417
418 "vsuxei8.v" => Vsuxv {
419 eew: BaseSew::E8,
420 data: vsx(op)?,
421 },
422 "vsuxei16.v" => Vsuxv {
423 eew: BaseSew::E16,
424 data: vsx(op)?,
425 },
426 "vsuxei32.v" => Vsuxv {
427 eew: BaseSew::E32,
428 data: vsx(op)?,
429 },
430 "vsuxei64.v" => Vsuxv {
431 eew: BaseSew::E64,
432 data: vsx(op)?,
433 },
434
435 "vsuxeix8.v" => Vsuxv {
436 eew: BaseSew::E8,
437 data: vsx(op)?,
438 },
439 "vsuxeix16.v" => Vsuxv {
440 eew: BaseSew::E16,
441 data: vsx(op)?,
442 },
443 "vsuxeix32.v" => Vsuxv {
444 eew: BaseSew::E32,
445 data: vsx(op)?,
446 },
447 "vsuxeix64.v" => Vsuxv {
448 eew: BaseSew::E64,
449 data: vsx(op)?,
450 },
451
452 "vle8ff.v" => Vlffv {
453 eew: BaseSew::E8,
454 data: vl(op)?,
455 },
456 "vle16ff.v" => Vlffv {
457 eew: BaseSew::E16,
458 data: vl(op)?,
459 },
460 "vle32ff.v" => Vlffv {
461 eew: BaseSew::E32,
462 data: vl(op)?,
463 },
464 "vle64ff.v" => Vlffv {
465 eew: BaseSew::E64,
466 data: vl(op)?,
467 },
468
469 "vlseg1e8.v" => Vlsegv {
471 nf: 1,
472 eew: BaseSew::E8,
473 data: vl(op)?,
474 },
475 "vlseg1e16.v" => Vlsegv {
476 nf: 1,
477 eew: BaseSew::E16,
478 data: vl(op)?,
479 },
480 "vlseg1e32.v" => Vlsegv {
481 nf: 1,
482 eew: BaseSew::E32,
483 data: vl(op)?,
484 },
485 "vlseg1e64.v" => Vlsegv {
486 nf: 1,
487 eew: BaseSew::E64,
488 data: vl(op)?,
489 },
490 "vlseg2e8.v" => Vlsegv {
491 nf: 2,
492 eew: BaseSew::E8,
493 data: vl(op)?,
494 },
495 "vlseg2e16.v" => Vlsegv {
496 nf: 2,
497 eew: BaseSew::E16,
498 data: vl(op)?,
499 },
500 "vlseg2e32.v" => Vlsegv {
501 nf: 2,
502 eew: BaseSew::E32,
503 data: vl(op)?,
504 },
505 "vlseg2e64.v" => Vlsegv {
506 nf: 2,
507 eew: BaseSew::E64,
508 data: vl(op)?,
509 },
510 "vlseg3e8.v" => Vlsegv {
511 nf: 3,
512 eew: BaseSew::E8,
513 data: vl(op)?,
514 },
515 "vlseg3e16.v" => Vlsegv {
516 nf: 3,
517 eew: BaseSew::E16,
518 data: vl(op)?,
519 },
520 "vlseg3e32.v" => Vlsegv {
521 nf: 3,
522 eew: BaseSew::E32,
523 data: vl(op)?,
524 },
525 "vlseg3e64.v" => Vlsegv {
526 nf: 3,
527 eew: BaseSew::E64,
528 data: vl(op)?,
529 },
530 "vlseg4e8.v" => Vlsegv {
531 nf: 4,
532 eew: BaseSew::E8,
533 data: vl(op)?,
534 },
535 "vlseg4e16.v" => Vlsegv {
536 nf: 4,
537 eew: BaseSew::E16,
538 data: vl(op)?,
539 },
540 "vlseg4e32.v" => Vlsegv {
541 nf: 4,
542 eew: BaseSew::E32,
543 data: vl(op)?,
544 },
545 "vlseg4e64.v" => Vlsegv {
546 nf: 4,
547 eew: BaseSew::E64,
548 data: vl(op)?,
549 },
550 "vlseg5e8.v" => Vlsegv {
551 nf: 5,
552 eew: BaseSew::E8,
553 data: vl(op)?,
554 },
555 "vlseg5e16.v" => Vlsegv {
556 nf: 5,
557 eew: BaseSew::E16,
558 data: vl(op)?,
559 },
560 "vlseg5e32.v" => Vlsegv {
561 nf: 5,
562 eew: BaseSew::E32,
563 data: vl(op)?,
564 },
565 "vlseg5e64.v" => Vlsegv {
566 nf: 5,
567 eew: BaseSew::E64,
568 data: vl(op)?,
569 },
570 "vlseg6e8.v" => Vlsegv {
571 nf: 6,
572 eew: BaseSew::E8,
573 data: vl(op)?,
574 },
575 "vlseg6e16.v" => Vlsegv {
576 nf: 6,
577 eew: BaseSew::E16,
578 data: vl(op)?,
579 },
580 "vlseg6e32.v" => Vlsegv {
581 nf: 6,
582 eew: BaseSew::E32,
583 data: vl(op)?,
584 },
585 "vlseg6e64.v" => Vlsegv {
586 nf: 6,
587 eew: BaseSew::E64,
588 data: vl(op)?,
589 },
590 "vlseg7e8.v" => Vlsegv {
591 nf: 7,
592 eew: BaseSew::E8,
593 data: vl(op)?,
594 },
595 "vlseg7e16.v" => Vlsegv {
596 nf: 7,
597 eew: BaseSew::E16,
598 data: vl(op)?,
599 },
600 "vlseg7e32.v" => Vlsegv {
601 nf: 7,
602 eew: BaseSew::E32,
603 data: vl(op)?,
604 },
605 "vlseg7e64.v" => Vlsegv {
606 nf: 7,
607 eew: BaseSew::E64,
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1322 eew: BaseSew::E16,
1323 data: vlx(op)?,
1324 },
1325 "vloxseg3ei32.v" => Vloxsegv {
1326 nf: 3,
1327 eew: BaseSew::E32,
1328 data: vlx(op)?,
1329 },
1330 "vloxseg3ei64.v" => Vloxsegv {
1331 nf: 3,
1332 eew: BaseSew::E64,
1333 data: vlx(op)?,
1334 },
1335 "vloxseg4ei8.v" => Vloxsegv {
1336 nf: 4,
1337 eew: BaseSew::E8,
1338 data: vlx(op)?,
1339 },
1340 "vloxseg4ei16.v" => Vloxsegv {
1341 nf: 4,
1342 eew: BaseSew::E16,
1343 data: vlx(op)?,
1344 },
1345 "vloxseg4ei32.v" => Vloxsegv {
1346 nf: 4,
1347 eew: BaseSew::E32,
1348 data: vlx(op)?,
1349 },
1350 "vloxseg4ei64.v" => Vloxsegv {
1351 nf: 4,
1352 eew: BaseSew::E64,
1353 data: vlx(op)?,
1354 },
1355 "vloxseg5ei8.v" => Vloxsegv {
1356 nf: 5,
1357 eew: BaseSew::E8,
1358 data: vlx(op)?,
1359 },
1360 "vloxseg5ei16.v" => Vloxsegv {
1361 nf: 5,
1362 eew: BaseSew::E16,
1363 data: vlx(op)?,
1364 },
1365 "vloxseg5ei32.v" => Vloxsegv {
1366 nf: 5,
1367 eew: BaseSew::E32,
1368 data: vlx(op)?,
1369 },
1370 "vloxseg5ei64.v" => Vloxsegv {
1371 nf: 5,
1372 eew: BaseSew::E64,
1373 data: vlx(op)?,
1374 },
1375 "vloxseg6ei8.v" => Vloxsegv {
1376 nf: 6,
1377 eew: BaseSew::E8,
1378 data: vlx(op)?,
1379 },
1380 "vloxseg6ei16.v" => Vloxsegv {
1381 nf: 6,
1382 eew: BaseSew::E16,
1383 data: vlx(op)?,
1384 },
1385 "vloxseg6ei32.v" => Vloxsegv {
1386 nf: 6,
1387 eew: BaseSew::E32,
1388 data: vlx(op)?,
1389 },
1390 "vloxseg6ei64.v" => Vloxsegv {
1391 nf: 6,
1392 eew: BaseSew::E64,
1393 data: vlx(op)?,
1394 },
1395 "vloxseg7ei8.v" => Vloxsegv {
1396 nf: 7,
1397 eew: BaseSew::E8,
1398 data: vlx(op)?,
1399 },
1400 "vloxseg7ei16.v" => Vloxsegv {
1401 nf: 7,
1402 eew: BaseSew::E16,
1403 data: vlx(op)?,
1404 },
1405 "vloxseg7ei32.v" => Vloxsegv {
1406 nf: 7,
1407 eew: BaseSew::E32,
1408 data: vlx(op)?,
1409 },
1410 "vloxseg7ei64.v" => Vloxsegv {
1411 nf: 7,
1412 eew: BaseSew::E64,
1413 data: vlx(op)?,
1414 },
1415 "vloxseg8ei8.v" => Vloxsegv {
1416 nf: 8,
1417 eew: BaseSew::E8,
1418 data: vlx(op)?,
1419 },
1420 "vloxseg8ei16.v" => Vloxsegv {
1421 nf: 8,
1422 eew: BaseSew::E16,
1423 data: vlx(op)?,
1424 },
1425 "vloxseg8ei32.v" => Vloxsegv {
1426 nf: 8,
1427 eew: BaseSew::E32,
1428 data: vlx(op)?,
1429 },
1430 "vloxseg8ei64.v" => Vloxsegv {
1431 nf: 8,
1432 eew: BaseSew::E64,
1433 data: vlx(op)?,
1434 },
1435
1436 "vsuxseg1ei8.v" => Vsuxsegv {
1437 nf: 1,
1438 eew: BaseSew::E8,
1439 data: vsx(op)?,
1440 },
1441 "vsuxseg1ei16.v" => Vsuxsegv {
1442 nf: 1,
1443 eew: BaseSew::E16,
1444 data: vsx(op)?,
1445 },
1446 "vsuxseg1ei32.v" => Vsuxsegv {
1447 nf: 1,
1448 eew: BaseSew::E32,
1449 data: vsx(op)?,
1450 },
1451 "vsuxseg1ei64.v" => Vsuxsegv {
1452 nf: 1,
1453 eew: BaseSew::E64,
1454 data: vsx(op)?,
1455 },
1456 "vsuxseg2ei8.v" => Vsuxsegv {
1457 nf: 2,
1458 eew: BaseSew::E8,
1459 data: vsx(op)?,
1460 },
1461 "vsuxseg2ei16.v" => Vsuxsegv {
1462 nf: 2,
1463 eew: BaseSew::E16,
1464 data: vsx(op)?,
1465 },
1466 "vsuxseg2ei32.v" => Vsuxsegv {
1467 nf: 2,
1468 eew: BaseSew::E32,
1469 data: vsx(op)?,
1470 },
1471 "vsuxseg2ei64.v" => Vsuxsegv {
1472 nf: 2,
1473 eew: BaseSew::E64,
1474 data: vsx(op)?,
1475 },
1476 "vsuxseg3ei8.v" => Vsuxsegv {
1477 nf: 3,
1478 eew: BaseSew::E8,
1479 data: vsx(op)?,
1480 },
1481 "vsuxseg3ei16.v" => Vsuxsegv {
1482 nf: 3,
1483 eew: BaseSew::E16,
1484 data: vsx(op)?,
1485 },
1486 "vsuxseg3ei32.v" => Vsuxsegv {
1487 nf: 3,
1488 eew: BaseSew::E32,
1489 data: vsx(op)?,
1490 },
1491 "vsuxseg3ei64.v" => Vsuxsegv {
1492 nf: 3,
1493 eew: BaseSew::E64,
1494 data: vsx(op)?,
1495 },
1496 "vsuxseg4ei8.v" => Vsuxsegv {
1497 nf: 4,
1498 eew: BaseSew::E8,
1499 data: vsx(op)?,
1500 },
1501 "vsuxseg4ei16.v" => Vsuxsegv {
1502 nf: 4,
1503 eew: BaseSew::E16,
1504 data: vsx(op)?,
1505 },
1506 "vsuxseg4ei32.v" => Vsuxsegv {
1507 nf: 4,
1508 eew: BaseSew::E32,
1509 data: vsx(op)?,
1510 },
1511 "vsuxseg4ei64.v" => Vsuxsegv {
1512 nf: 4,
1513 eew: BaseSew::E64,
1514 data: vsx(op)?,
1515 },
1516 "vsuxseg5ei8.v" => Vsuxsegv {
1517 nf: 5,
1518 eew: BaseSew::E8,
1519 data: vsx(op)?,
1520 },
1521 "vsuxseg5ei16.v" => Vsuxsegv {
1522 nf: 5,
1523 eew: BaseSew::E16,
1524 data: vsx(op)?,
1525 },
1526 "vsuxseg5ei32.v" => Vsuxsegv {
1527 nf: 5,
1528 eew: BaseSew::E32,
1529 data: vsx(op)?,
1530 },
1531 "vsuxseg5ei64.v" => Vsuxsegv {
1532 nf: 5,
1533 eew: BaseSew::E64,
1534 data: vsx(op)?,
1535 },
1536 "vsuxseg6ei8.v" => Vsuxsegv {
1537 nf: 6,
1538 eew: BaseSew::E8,
1539 data: vsx(op)?,
1540 },
1541 "vsuxseg6ei16.v" => Vsuxsegv {
1542 nf: 6,
1543 eew: BaseSew::E16,
1544 data: vsx(op)?,
1545 },
1546 "vsuxseg6ei32.v" => Vsuxsegv {
1547 nf: 6,
1548 eew: BaseSew::E32,
1549 data: vsx(op)?,
1550 },
1551 "vsuxseg6ei64.v" => Vsuxsegv {
1552 nf: 6,
1553 eew: BaseSew::E64,
1554 data: vsx(op)?,
1555 },
1556 "vsuxseg7ei8.v" => Vsuxsegv {
1557 nf: 7,
1558 eew: BaseSew::E8,
1559 data: vsx(op)?,
1560 },
1561 "vsuxseg7ei16.v" => Vsuxsegv {
1562 nf: 7,
1563 eew: BaseSew::E16,
1564 data: vsx(op)?,
1565 },
1566 "vsuxseg7ei32.v" => Vsuxsegv {
1567 nf: 7,
1568 eew: BaseSew::E32,
1569 data: vsx(op)?,
1570 },
1571 "vsuxseg7ei64.v" => Vsuxsegv {
1572 nf: 7,
1573 eew: BaseSew::E64,
1574 data: vsx(op)?,
1575 },
1576 "vsuxseg8ei8.v" => Vsuxsegv {
1577 nf: 8,
1578 eew: BaseSew::E8,
1579 data: vsx(op)?,
1580 },
1581 "vsuxseg8ei16.v" => Vsuxsegv {
1582 nf: 8,
1583 eew: BaseSew::E16,
1584 data: vsx(op)?,
1585 },
1586 "vsuxseg8ei32.v" => Vsuxsegv {
1587 nf: 8,
1588 eew: BaseSew::E32,
1589 data: vsx(op)?,
1590 },
1591 "vsuxseg8ei64.v" => Vsuxsegv {
1592 nf: 8,
1593 eew: BaseSew::E64,
1594 data: vsx(op)?,
1595 },
1596
1597 "vsoxseg1ei8.v" => Vsoxsegv {
1598 nf: 1,
1599 eew: BaseSew::E8,
1600 data: vsx(op)?,
1601 },
1602 "vsoxseg1ei16.v" => Vsoxsegv {
1603 nf: 1,
1604 eew: BaseSew::E16,
1605 data: vsx(op)?,
1606 },
1607 "vsoxseg1ei32.v" => Vsoxsegv {
1608 nf: 1,
1609 eew: BaseSew::E32,
1610 data: vsx(op)?,
1611 },
1612 "vsoxseg1ei64.v" => Vsoxsegv {
1613 nf: 1,
1614 eew: BaseSew::E64,
1615 data: vsx(op)?,
1616 },
1617 "vsoxseg2ei8.v" => Vsoxsegv {
1618 nf: 2,
1619 eew: BaseSew::E8,
1620 data: vsx(op)?,
1621 },
1622 "vsoxseg2ei16.v" => Vsoxsegv {
1623 nf: 2,
1624 eew: BaseSew::E16,
1625 data: vsx(op)?,
1626 },
1627 "vsoxseg2ei32.v" => Vsoxsegv {
1628 nf: 2,
1629 eew: BaseSew::E32,
1630 data: vsx(op)?,
1631 },
1632 "vsoxseg2ei64.v" => Vsoxsegv {
1633 nf: 2,
1634 eew: BaseSew::E64,
1635 data: vsx(op)?,
1636 },
1637 "vsoxseg3ei8.v" => Vsoxsegv {
1638 nf: 3,
1639 eew: BaseSew::E8,
1640 data: vsx(op)?,
1641 },
1642 "vsoxseg3ei16.v" => Vsoxsegv {
1643 nf: 3,
1644 eew: BaseSew::E16,
1645 data: vsx(op)?,
1646 },
1647 "vsoxseg3ei32.v" => Vsoxsegv {
1648 nf: 3,
1649 eew: BaseSew::E32,
1650 data: vsx(op)?,
1651 },
1652 "vsoxseg3ei64.v" => Vsoxsegv {
1653 nf: 3,
1654 eew: BaseSew::E64,
1655 data: vsx(op)?,
1656 },
1657 "vsoxseg4ei8.v" => Vsoxsegv {
1658 nf: 4,
1659 eew: BaseSew::E8,
1660 data: vsx(op)?,
1661 },
1662 "vsoxseg4ei16.v" => Vsoxsegv {
1663 nf: 4,
1664 eew: BaseSew::E16,
1665 data: vsx(op)?,
1666 },
1667 "vsoxseg4ei32.v" => Vsoxsegv {
1668 nf: 4,
1669 eew: BaseSew::E32,
1670 data: vsx(op)?,
1671 },
1672 "vsoxseg4ei64.v" => Vsoxsegv {
1673 nf: 4,
1674 eew: BaseSew::E64,
1675 data: vsx(op)?,
1676 },
1677 "vsoxseg5ei8.v" => Vsoxsegv {
1678 nf: 5,
1679 eew: BaseSew::E8,
1680 data: vsx(op)?,
1681 },
1682 "vsoxseg5ei16.v" => Vsoxsegv {
1683 nf: 5,
1684 eew: BaseSew::E16,
1685 data: vsx(op)?,
1686 },
1687 "vsoxseg5ei32.v" => Vsoxsegv {
1688 nf: 5,
1689 eew: BaseSew::E32,
1690 data: vsx(op)?,
1691 },
1692 "vsoxseg5ei64.v" => Vsoxsegv {
1693 nf: 5,
1694 eew: BaseSew::E64,
1695 data: vsx(op)?,
1696 },
1697 "vsoxseg6ei8.v" => Vsoxsegv {
1698 nf: 6,
1699 eew: BaseSew::E8,
1700 data: vsx(op)?,
1701 },
1702 "vsoxseg6ei16.v" => Vsoxsegv {
1703 nf: 6,
1704 eew: BaseSew::E16,
1705 data: vsx(op)?,
1706 },
1707 "vsoxseg6ei32.v" => Vsoxsegv {
1708 nf: 6,
1709 eew: BaseSew::E32,
1710 data: vsx(op)?,
1711 },
1712 "vsoxseg6ei64.v" => Vsoxsegv {
1713 nf: 6,
1714 eew: BaseSew::E64,
1715 data: vsx(op)?,
1716 },
1717 "vsoxseg7ei8.v" => Vsoxsegv {
1718 nf: 7,
1719 eew: BaseSew::E8,
1720 data: vsx(op)?,
1721 },
1722 "vsoxseg7ei16.v" => Vsoxsegv {
1723 nf: 7,
1724 eew: BaseSew::E16,
1725 data: vsx(op)?,
1726 },
1727 "vsoxseg7ei32.v" => Vsoxsegv {
1728 nf: 7,
1729 eew: BaseSew::E32,
1730 data: vsx(op)?,
1731 },
1732 "vsoxseg7ei64.v" => Vsoxsegv {
1733 nf: 7,
1734 eew: BaseSew::E64,
1735 data: vsx(op)?,
1736 },
1737 "vsoxseg8ei8.v" => Vsoxsegv {
1738 nf: 8,
1739 eew: BaseSew::E8,
1740 data: vsx(op)?,
1741 },
1742 "vsoxseg8ei16.v" => Vsoxsegv {
1743 nf: 8,
1744 eew: BaseSew::E16,
1745 data: vsx(op)?,
1746 },
1747 "vsoxseg8ei32.v" => Vsoxsegv {
1748 nf: 8,
1749 eew: BaseSew::E32,
1750 data: vsx(op)?,
1751 },
1752 "vsoxseg8ei64.v" => Vsoxsegv {
1753 nf: 8,
1754 eew: BaseSew::E64,
1755 data: vsx(op)?,
1756 },
1757
1758 "vl1re8.v" => Vlrv {
1759 nf: 1,
1760 eew: BaseSew::E8,
1761 data: vlr(op)?,
1762 },
1763 "vl1re16.v" => Vlrv {
1764 nf: 1,
1765 eew: BaseSew::E16,
1766 data: vlr(op)?,
1767 },
1768 "vl1re32.v" => Vlrv {
1769 nf: 1,
1770 eew: BaseSew::E32,
1771 data: vlr(op)?,
1772 },
1773 "vl1re64.v" => Vlrv {
1774 nf: 1,
1775 eew: BaseSew::E64,
1776 data: vlr(op)?,
1777 },
1778 "vl2re8.v" => Vlrv {
1779 nf: 2,
1780 eew: BaseSew::E8,
1781 data: vlr(op)?,
1782 },
1783 "vl2re16.v" => Vlrv {
1784 nf: 2,
1785 eew: BaseSew::E16,
1786 data: vlr(op)?,
1787 },
1788 "vl2re32.v" => Vlrv {
1789 nf: 2,
1790 eew: BaseSew::E32,
1791 data: vlr(op)?,
1792 },
1793 "vl2re64.v" => Vlrv {
1794 nf: 2,
1795 eew: BaseSew::E64,
1796 data: vlr(op)?,
1797 },
1798 "vl4re8.v" => Vlrv {
1799 nf: 4,
1800 eew: BaseSew::E8,
1801 data: vlr(op)?,
1802 },
1803 "vl4re16.v" => Vlrv {
1804 nf: 4,
1805 eew: BaseSew::E16,
1806 data: vlr(op)?,
1807 },
1808 "vl4re32.v" => Vlrv {
1809 nf: 4,
1810 eew: BaseSew::E32,
1811 data: vlr(op)?,
1812 },
1813 "vl4re64.v" => Vlrv {
1814 nf: 4,
1815 eew: BaseSew::E64,
1816 data: vlr(op)?,
1817 },
1818 "vl8re8.v" => Vlrv {
1819 nf: 8,
1820 eew: BaseSew::E8,
1821 data: vlr(op)?,
1822 },
1823 "vl8re16.v" => Vlrv {
1824 nf: 8,
1825 eew: BaseSew::E16,
1826 data: vlr(op)?,
1827 },
1828 "vl8re32.v" => Vlrv {
1829 nf: 8,
1830 eew: BaseSew::E32,
1831 data: vlr(op)?,
1832 },
1833 "vl8re64.v" => Vlrv {
1834 nf: 8,
1835 eew: BaseSew::E64,
1836 data: vlr(op)?,
1837 },
1838
1839 "vs1r.v" => Vsrv {
1840 nf: 1,
1841 data: vsr(op)?,
1842 },
1843 "vs2r.v" => Vsrv {
1844 nf: 2,
1845 data: vsr(op)?,
1846 },
1847 "vs4r.v" => Vsrv {
1848 nf: 4,
1849 data: vsr(op)?,
1850 },
1851 "vs8r.v" => Vsrv {
1852 nf: 8,
1853 data: vsr(op)?,
1854 },
1855
1856 "vadd.vv" => Vaddvv(opivv(op)?),
1857 "vadd.vx" => Vaddvx(opivx(op)?),
1858 "vadd.vi" => Vaddvi(opivi(op)?),
1859
1860 "vsub.vv" => Vsubvv(opivv(op)?),
1861 "vsub.vx" => Vsubvx(opivx(op)?),
1862
1863 "vrsub.vx" => Vrsubvx(opivx(op)?),
1864 "vrsub.vi" => Vrsubvi(opivi(op)?),
1865
1866 "vminu.vv" => Vminuvv(opivv(op)?),
1867 "vminu.vx" => Vminuvx(opivx(op)?),
1868
1869 "vmin.vv" => Vminvv(opivv(op)?),
1870 "vmin.vx" => Vminvx(opivx(op)?),
1871
1872 "vmaxu.vv" => Vmaxuvv(opivv(op)?),
1873 "vmaxu.vx" => Vmaxuvx(opivx(op)?),
1874
1875 "vmax.vv" => Vmaxvv(opivv(op)?),
1876 "vmax.vx" => Vmaxvx(opivx(op)?),
1877
1878 "vand.vv" => Vandvv(opivv(op)?),
1879 "vand.vx" => Vandvx(opivx(op)?),
1880 "vand.vi" => Vandvi(opivi(op)?),
1881
1882 "vor.vv" => Vorvv(opivv(op)?),
1883 "vor.vx" => Vorvx(opivx(op)?),
1884 "vor.vi" => Vorvi(opivi(op)?),
1885
1886 "vxor.vv" => Vxorvv(opivv(op)?),
1887 "vxor.vx" => Vxorvx(opivx(op)?),
1888 "vxor.vi" => Vxorvi(opivi(op)?),
1889
1890 "vrgather.vv" => Vrgathervv(opivv(op)?),
1891 "vrgather.vx" => Vrgathervx(opivx(op)?),
1892 "vrgather.vi" => Vrgathervi(opivi(op)?),
1893
1894 "vrgatherei16.v" => Vrgatherei16vv(opivv(op)?),
1895
1896 "vslideup.vx" => Vslideupvx(opivx(op)?),
1897 "vslideup.vi" => Vslideupvi(opivi(op)?),
1898
1899 "vslidedown.vx" => Vslidedownvx(opivx(op)?),
1900 "vslidedown.vi" => Vslidedownvi(opivi(op)?),
1901
1902 "vadc.vvm" => Vadcvvm(opivv_v0(op)?),
1903 "vadc.vxm" => Vadcvxm(opivx_v0(op)?),
1904 "vadc.vim" => Vadcvim(opivi_v0(op)?),
1905
1906 "vmadc.vvm" => Vmadcvvm(opivv_v0(op)?),
1907 "vmadc.vxm" => Vmadcvxm(opivx_v0(op)?),
1908 "vmadc.vim" => Vmadcvim(opivi_v0(op)?),
1909 "vmadc.vv" => Vmadcvv(opivv_maskless(op)?),
1910 "vmadc.vx" => Vmadcvx(opivx_maskless(op)?),
1911 "vmadc.vi" => Vmadcvi(opivi_maskless(op)?),
1912
1913 "vsbc.vvm" => Vsbcvvm(opivv(op)?),
1914 "vsbc.vxm" => Vsbcvxm(opivx(op)?),
1915
1916 "vmsbc.vv" => Vmsbcvv(opivv(op)?),
1917 "vmsbc.vx" => Vmsbcvx(opivx(op)?),
1918
1919 "vmerge.vvm" => Vmergevvm(opivv(op)?),
1920 "vmerge.vxm" => Vmergevxm(opivx(op)?),
1921 "vmerge.vim" => Vmergevim(opivi(op)?),
1922
1923 "vmv.v.v" => Vmvvv(opivv_vmv(op)?),
1924 "vmv.v.x" => Vmvvx(opivx_vmv(op)?),
1925 "vmv.v.i" => Vmvvi(opivi_vmv(op)?),
1926
1927 "vmseq.vv" => Vmseqvv(opivv(op)?),
1928 "vmseq.vx" => Vmseqvx(opivx(op)?),
1929 "vmseq.vi" => Vmseqvi(opivi(op)?),
1930
1931 "vmsne.vv" => Vmsnevv(opivv(op)?),
1932 "vmsne.vx" => Vmsnevx(opivx(op)?),
1933 "vmsne.vi" => Vmsnevi(opivi(op)?),
1934
1935 "vmsltu.vv" => Vmsltuvv(opivv(op)?),
1936 "vmsltu.vx" => Vmsltuvx(opivx(op)?),
1937
1938 "vmslt.vv" => Vmsltvv(opivv(op)?),
1939 "vmslt.vx" => Vmsltvx(opivx(op)?),
1940
1941 "vmsleu.vv" => Vmsleuvv(opivv(op)?),
1942 "vmsleu.vx" => Vmsleuvx(opivx(op)?),
1943 "vmsleu.vi" => Vmsleuvi(opivi(op)?),
1944
1945 "vmsle.vv" => Vmslevv(opivv(op)?),
1946 "vmsle.vx" => Vmslevx(opivx(op)?),
1947 "vmsle.vi" => Vmslevi(opivi(op)?),
1948
1949 "vmsgtu.vx" => Vmsgtuvx(opivx(op)?),
1950 "vmsgtu.vi" => Vmsgtuvi(opivi(op)?),
1951
1952 "vmsgt.vx" => Vmsgtvx(opivx(op)?),
1953 "vmsgt.vi" => Vmsgtvi(opivi(op)?),
1954
1955 "vsaddu.vv" => Vsadduvv(opivv(op)?),
1956 "vsaddu.vx" => Vsadduvx(opivx(op)?),
1957 "vsaddu.vi" => Vsadduvi(opivi(op)?),
1958
1959 "vsadd.vv" => Vsaddvv(opivv(op)?),
1960 "vsadd.vx" => Vsaddvx(opivx(op)?),
1961 "vsadd.vi" => Vsaddvi(opivi(op)?),
1962
1963 "vssubu.vv" => Vssubuvv(opivv(op)?),
1964 "vssubu.vx" => Vssubuvx(opivx(op)?),
1965
1966 "vssub.vv" => Vssubvv(opivv(op)?),
1967 "vssub.vx" => Vssubvx(opivx(op)?),
1968
1969 "vsll.vv" => Vsllvv(opivv(op)?),
1970 "vsll.vx" => Vsllvx(opivx(op)?),
1971 "vsll.vi" => Vsllvi(opivi(op)?),
1972
1973 "vsmul.vv" => Vsmulvv(opivv(op)?),
1974 "vsmul.vx" => Vsmulvx(opivx(op)?),
1975
1976 "vmv1r.v" => Vmv1rv(opivi(op)?),
1977 "vmv2r.v" => Vmv2rv(opivi(op)?),
1978 "vmv4r.v" => Vmv4rv(opivi(op)?),
1979 "vmv8r.v" => Vmv8rv(opivi(op)?),
1980
1981 "vsrl.vv" => Vsrlvv(opivv(op)?),
1982 "vsrl.vx" => Vsrlvx(opivx(op)?),
1983 "vsrl.vi" => Vsrlvi(opivi(op)?),
1984
1985 "vsra.vv" => Vsravv(opivv(op)?),
1986 "vsra.vx" => Vsravx(opivx(op)?),
1987 "vsra.vi" => Vsravi(opivi(op)?),
1988
1989 "vssrl.vv" => Vssrlvv(opivv(op)?),
1990 "vssrl.vx" => Vssrlvx(opivx(op)?),
1991 "vssrl.vi" => Vssrlvi(opivi(op)?),
1992
1993 "vssra.vv" => Vssravv(opivv(op)?),
1994 "vssra.vx" => Vssravx(opivx(op)?),
1995 "vssra.vi" => Vssravi(opivi(op)?),
1996
1997 "vnsrl.wv" => Vnsrlwv(opivv(op)?),
1998 "vnsrl.wx" => Vnsrlwx(opivx(op)?),
1999 "vnsrl.wi" => Vnsrlwi(opivi(op)?),
2000
2001 "vnsra.wv" => Vnsrawv(opivv(op)?),
2002 "vnsra.wx" => Vnsrawx(opivx(op)?),
2003 "vnsra.wi" => Vnsrawi(opivi(op)?),
2004
2005 "vnclipu.wv" => Vnclipuwv(opivv(op)?),
2006 "vnclipu.wx" => Vnclipuwx(opivx(op)?),
2007 "vnclipu.wi" => Vnclipuwi(opivi(op)?),
2008
2009 "vnclip.wv" => Vnclipwv(opivv(op)?),
2010 "vnclip.wx" => Vnclipwx(opivx(op)?),
2011 "vnclip.wi" => Vnclipwi(opivi(op)?),
2012
2013 "vwredsumu.vs" => Vwredsumuvs(opivv(op)?),
2014 "vwredsum.vs" => Vwredsumvs(opivv(op)?),
2015
2016 "vredsum.vs" => Vredsumvs(opmvv(op)?),
2017 "vredand.vs" => Vredandvs(opmvv(op)?),
2018 "vredor.vs" => Vredorvs(opmvv(op)?),
2019 "vredxor.vs" => Vredxorvs(opmvv(op)?),
2020 "vredminu.vs" => Vredminuvs(opmvv(op)?),
2021 "vredmin.vs" => Vredminvs(opmvv(op)?),
2022 "vredmaxu.vs" => Vredmaxuvs(opmvv(op)?),
2023 "vredmax.vs" => Vredmaxvs(opmvv(op)?),
2024
2025 "vaaddu.vv" => Vaadduvv(opmvv(op)?),
2026 "vaaddu.vx" => Vaadduvx(opmvx(op)?),
2027
2028 "vaadd.vv" => Vaaddvv(opmvv(op)?),
2029 "vaadd.vx" => Vaaddvx(opmvx(op)?),
2030
2031 "vasubu.vv" => Vasubuvv(opmvv(op)?),
2032 "vasubu.vx" => Vasubuvx(opmvx(op)?),
2033
2034 "vasub.vv" => Vasubvv(opmvv(op)?),
2035 "vasub.vx" => Vasubvx(opmvx(op)?),
2036
2037 "vslide1up.vx" => Vslide1upvx(opmvx(op)?),
2038
2039 "vslide1down.vx" => Vslide1downvx(opmvx(op)?),
2040
2041 "vmv.x.s" => Vmvxs(vmvxs(op)?),
2042 "vcpop.m" => Vcpopm(vwxunary0(op)?),
2043 "vfirst.m" => Vfirstm(vwxunary0(op)?),
2044
2045 "vmv.s.x" => Vmvsx(vrxunary0(op)?),
2046
2047 "vsext.vf2" => Vsextvf2(vxunary0(op)?),
2048 "vsext.vf4" => Vsextvf4(vxunary0(op)?),
2049 "vsext.vf8" => Vsextvf8(vxunary0(op)?),
2050
2051 "vzext.vf2" => Vzextvf2(vxunary0(op)?),
2052 "vzext.vf4" => Vzextvf4(vxunary0(op)?),
2053 "vzext.vf8" => Vzextvf8(vxunary0(op)?),
2054
2055 "vmsbf.m" => Vmsbfm(vmunary0(op)?),
2056 "vmsof.m" => Vmsofm(vmunary0(op)?),
2057 "vmsif.m" => Vmsifm(vmunary0(op)?),
2058 "viota.m" => Viotam(vmunary0(op)?),
2059 "vid.v" => Vidv(vidv(op)?),
2060
2061 "vcompress.vm" => Vcompressvm(opmvv_maskless(op)?),
2062
2063 "vmandn.mm" => Vmandnmm(opmvv_maskless(op)?),
2064 "vmand.mm" => Vmandmm(opmvv_maskless(op)?),
2065 "vmor.mm" => Vmormm(opmvv_maskless(op)?),
2066 "vmxor.mm" => Vmxormm(opmvv_maskless(op)?),
2067 "vmorn.mm" => Vmornmm(opmvv_maskless(op)?),
2068 "vmnand.mm" => Vmnandmm(opmvv_maskless(op)?),
2069 "vmnor.mm" => Vmnormm(opmvv_maskless(op)?),
2070 "vmxnor.mm" => Vmxnormm(opmvv_maskless(op)?),
2071
2072 "vdivu.vv" => Vdivuvv(opmvv(op)?),
2073 "vdivu.vx" => Vdivuvx(opmvx(op)?),
2074
2075 "vdiv.vv" => Vdivvv(opmvv(op)?),
2076 "vdiv.vx" => Vdivvx(opmvx(op)?),
2077
2078 "vremu.vv" => Vremuvv(opmvv(op)?),
2079 "vremu.vx" => Vremuvx(opmvx(op)?),
2080
2081 "vrem.vv" => Vremvv(opmvv(op)?),
2082 "vrem.vx" => Vremvx(opmvx(op)?),
2083
2084 "vmulhu.vv" => Vmulhuvv(opmvv(op)?),
2085 "vmulhu.vx" => Vmulhuvx(opmvx(op)?),
2086
2087 "vmul.vv" => Vmulvv(opmvv(op)?),
2088 "vmul.vx" => Vmulvx(opmvx(op)?),
2089
2090 "vmulhsu.vv" => Vmulhsuvv(opmvv(op)?),
2091 "vmulhsu.vx" => Vmulhsuvx(opmvx(op)?),
2092
2093 "vmulh.vv" => Vmulhvv(opmvv(op)?),
2094 "vmulh.vx" => Vmulhvx(opmvx(op)?),
2095
2096 "vmadd.vv" => Vmaddvv(opmvv_fma(op)?),
2097 "vmadd.vx" => Vmaddvx(opmvx_fma(op)?),
2098
2099 "vnmsub.vv" => Vnmsubvv(opmvv_fma(op)?),
2100 "vnmsub.vx" => Vnmsubvx(opmvx_fma(op)?),
2101
2102 "vmacc.vv" => Vmaccvv(opmvv_fma(op)?),
2103 "vmacc.vx" => Vmaccvx(opmvx_fma(op)?),
2104
2105 "vnmsac.vv" => Vnmsacvv(opmvv_fma(op)?),
2106 "vnmsac.vx" => Vnmsacvx(opmvx_fma(op)?),
2107
2108 "vwaddu.vv" => Vwadduvv(opmvv(op)?),
2109 "vwaddu.vx" => Vwadduvx(opmvx(op)?),
2110
2111 "vwadd.vv" => Vwaddvv(opmvv(op)?),
2112 "vwadd.vx" => Vwaddvx(opmvx(op)?),
2113
2114 "vwsubu.vv" => Vwsubuvv(opmvv(op)?),
2115 "vwsubu.vx" => Vwsubuvx(opmvx(op)?),
2116
2117 "vwsub.vv" => Vwsubvv(opmvv(op)?),
2118 "vwsub.vx" => Vwsubvx(opmvx(op)?),
2119
2120 "vwaddu.wv" => Vwadduwv(opmvv(op)?),
2121 "vwaddu.wx" => Vwadduwx(opmvx(op)?),
2122
2123 "vwadd.wv" => Vwaddwv(opmvv(op)?),
2124 "vwadd.wx" => Vwaddwx(opmvx(op)?),
2125
2126 "vwsubu.wv" => Vwsubuwv(opmvv(op)?),
2127 "vwsubu.wx" => Vwsubuwx(opmvx(op)?),
2128
2129 "vwsub.wv" => Vwsubwv(opmvv(op)?),
2130 "vwsub.wx" => Vwsubwx(opmvx(op)?),
2131
2132 "vwmulu.vv" => Vwmuluvv(opmvv(op)?),
2133 "vwmulu.vx" => Vwmuluvx(opmvx(op)?),
2134
2135 "vwmulsu.vv" => Vwmulsuvv(opmvv(op)?),
2136 "vwmulsu.vx" => Vwmulsuvx(opmvx(op)?),
2137
2138 "vwmul.vv" => Vwmulvv(opmvv(op)?),
2139 "vwmul.vx" => Vwmulvx(opmvx(op)?),
2140
2141 "vwmaccu.vv" => Vwmaccuvv(opmvv_fma(op)?),
2142 "vwmaccu.vx" => Vwmaccuvx(opmvx_fma(op)?),
2143
2144 "vwmacc.vv" => Vwmaccvv(opmvv_fma(op)?),
2145 "vwmacc.vx" => Vwmaccvx(opmvx_fma(op)?),
2146
2147 "vwmaccus.vx" => Vwmaccusvx(opmvx_fma(op)?),
2148
2149 "vwmaccsu.vv" => Vwmaccsuvv(opmvv_fma(op)?),
2150 "vwmaccsu.vx" => Vwmaccsuvx(opmvx_fma(op)?),
2151
2152 "vfadd.vv" => Vfaddvv(opfvv(op)?),
2153 "vfadd.vf" => Vfaddvf(opfvf(op)?),
2154
2155 "vfredusum.vs" => Vfredusumvs(opfvv(op)?),
2156
2157 "vfsub.vv" => Vfsubvv(opfvv(op)?),
2158 "vfsub.vf" => Vfsubvf(opfvf(op)?),
2159
2160 "vfredosum.vs" => Vfredosumvs(opfvv(op)?),
2161
2162 "vfmin.vv" => Vfminvv(opfvv(op)?),
2163 "vfmin.vf" => Vfminvf(opfvf(op)?),
2164
2165 "vfredmin.vs" => Vfredminvs(opfvv(op)?),
2166
2167 "vfmax.vv" => Vfmaxvv(opfvv(op)?),
2168 "vfmax.vf" => Vfmaxvf(opfvf(op)?),
2169
2170 "vfredmax.vs" => Vfredmaxvs(opfvv(op)?),
2171
2172 "vfsgnj.vv" => Vfsgnjvv(opfvv(op)?),
2173 "vfsgnj.vf" => Vfsgnjvf(opfvf(op)?),
2174
2175 "vfsgnjn.vv" => Vfsgnjnvv(opfvv(op)?),
2176 "vfsgnjn.vf" => Vfsgnjnvf(opfvf(op)?),
2177
2178 "vfsgnjx.vv" => Vfsgnjxvv(opfvv(op)?),
2179 "vfsgnjx.vf" => Vfsgnjxvf(opfvf(op)?),
2180
2181 "vfslide1up.vf" => Vfslide1upvf(opfvf(op)?),
2182
2183 "vfslide1down.vf" => Vfslide1downvf(opfvf(op)?),
2184
2185 "vfmv.f.s" => Vfmvfs(vwfunary0(op)?),
2186
2187 "vfmv.s.f" => Vfmvsf(vrfunary0(op)?),
2188
2189 "vfcvt.xu.f.v" => Vfcvtxufv(vfunary0(op)?),
2190 "vfcvt.x.f.v" => Vfcvtxfv(vfunary0(op)?),
2191 "vfcvt.f.xu.v" => Vfcvtfxuv(vfunary0(op)?),
2192 "vfcvt.f.x.v" => Vfcvtfxv(vfunary0(op)?),
2193 "vfcvt.rtz.xu.f.v" => VfcvtRtzxufv(vfunary0(op)?),
2194 "vfcvt.rtz.x.f.v" => VfcvtRtzxfv(vfunary0(op)?),
2195
2196 "vfwcvt.xu.f.v" => Vfwcvtxufv(vfunary0(op)?),
2197 "vfwcvt.x.f.v" => Vfwcvtxfv(vfunary0(op)?),
2198 "vfwcvt.f.xu.v" => Vfwcvtfxuv(vfunary0(op)?),
2199 "vfwcvt.f.x.v" => Vfwcvtfxv(vfunary0(op)?),
2200 "vfwcvt.f.f.v" => Vfwcvtffv(vfunary0(op)?),
2201 "vfwcvt.rtz.xu.f.v" => VfwcvtRtzxufv(vfunary0(op)?),
2202 "vfwcvt.rtz.x.f.v" => VfwcvtRtzxfv(vfunary0(op)?),
2203
2204 "vfncvt.xu.f.w" => Vfncvtxufw(vfunary0(op)?),
2205 "vfncvt.x.f.w" => Vfncvtxfw(vfunary0(op)?),
2206 "vfncvt.f.xu.w" => Vfncvtfxuw(vfunary0(op)?),
2207 "vfncvt.f.x.w" => Vfncvtfxw(vfunary0(op)?),
2208 "vfncvt.f.f.w" => Vfncvtffw(vfunary0(op)?),
2209 "vfncvt.rod.f.f.w" => VfncvtRodffw(vfunary0(op)?),
2210 "vfncvt.rtz.xu.f.w" => VfncvtRtzxufw(vfunary0(op)?),
2211 "vfncvt.rtz.x.f.w" => VfncvtRtzxfw(vfunary0(op)?),
2212
2213 "vfsqrt.v" => Vfsqrtv(vfunary1(op)?),
2214 "vfrsqrt7.v" => Vfrsqrt7v(vfunary1(op)?),
2215 "vfrec7.v" => Vfrec7v(vfunary1(op)?),
2216 "vfclass.v" => Vfclassv(vfunary1(op)?),
2217
2218 "vfmerge.vfm" => Vfmergevfm(opfvf(op)?),
2219 "vfmv.v.f" => Vfmvvf(opfvf(op)?),
2220
2221 "vmfeq.vv" => Vmfeqvv(opfvv(op)?),
2222 "vmfeq.vf" => Vmfeqvf(opfvf(op)?),
2223
2224 "vmfle.vv" => Vmflevv(opfvv(op)?),
2225 "vmfle.vf" => Vmflevf(opfvf(op)?),
2226
2227 "vmflt.vv" => Vmfltvv(opfvv(op)?),
2228 "vmflt.vf" => Vmfltvf(opfvf(op)?),
2229
2230 "vmfne.vv" => Vmfnevv(opfvv(op)?),
2231 "vmfne.vf" => Vmfnevf(opfvf(op)?),
2232
2233 "vmfgt.vf" => Vmfgtvf(opfvf(op)?),
2234
2235 "vmfge.vf" => Vmfgevf(opfvf(op)?),
2236
2237 "vfdiv.vv" => Vfdivvv(opfvv(op)?),
2238 "vfdiv.vf" => Vfdivvf(opfvf(op)?),
2239
2240 "vfrdiv.vf" => Vfrdivvf(opfvf(op)?),
2241
2242 "vfmul.vv" => Vfmulvv(opfvv(op)?),
2243 "vfmul.vf" => Vfmulvf(opfvf(op)?),
2244
2245 "vfrsub.vf" => Vfrsubvf(opfvf(op)?),
2246
2247 "vfmadd.vv" => Vfmaddvv(opfvv_fma(op)?),
2248 "vfmadd.vf" => Vfmaddvf(opfvf_fma(op)?),
2249
2250 "vfnmadd.vv" => Vfnmaddvv(opfvv_fma(op)?),
2251 "vfnmadd.vf" => Vfnmaddvf(opfvf_fma(op)?),
2252
2253 "vfmsub.vv" => Vfmsubvv(opfvv_fma(op)?),
2254 "vfmsub.vf" => Vfmsubvf(opfvf_fma(op)?),
2255
2256 "vfnmsub.vv" => Vfnmsubvv(opfvv_fma(op)?),
2257 "vfnmsub.vf" => Vfnmsubvf(opfvf_fma(op)?),
2258
2259 "vfmacc.vv" => Vfmaccvv(opfvv_fma(op)?),
2260 "vfmacc.vf" => Vfmaccvf(opfvf_fma(op)?),
2261
2262 "vfnmacc.vv" => Vfnmaccvv(opfvv_fma(op)?),
2263 "vfnmacc.vf" => Vfnmaccvf(opfvf_fma(op)?),
2264
2265 "vfmsac.vv" => Vfmsacvv(opfvv_fma(op)?),
2266 "vfmsac.vf" => Vfmsacvf(opfvf_fma(op)?),
2267
2268 "vfnmsac.vv" => Vfnmsacvv(opfvv_fma(op)?),
2269 "vfnmsac.vf" => Vfnmsacvf(opfvf_fma(op)?),
2270
2271 "vfwadd.vv" => Vfwaddvv(opfvv(op)?),
2272 "vfwadd.vf" => Vfwaddvf(opfvf(op)?),
2273
2274 "vfwredusum.vs" => Vfwredusumvs(opfvv(op)?),
2275
2276 "vfwsub.vv" => Vfwsubvv(opfvv(op)?),
2277 "vfwsub.vf" => Vfwsubvf(opfvf(op)?),
2278
2279 "vfwredosum.vs" => Vfwredosumvs(opfvv(op)?),
2280
2281 "vfwadd.wv" => Vfwaddwv(opfvv(op)?),
2282 "vfwadd.wf" => Vfwaddwf(opfvf(op)?),
2283
2284 "vfwsub.wv" => Vfwsubwv(opfvv(op)?),
2285 "vfwsub.wf" => Vfwsubwf(opfvf(op)?),
2286
2287 "vfwmul.vv" => Vfwmulvv(opfvv(op)?),
2288 "vfwmul.vf" => Vfwmulvf(opfvf(op)?),
2289
2290 "vfwmacc.vv" => Vfwmaccvv(opfvv_fma(op)?),
2291 "vfwmacc.vf" => Vfwmaccvf(opfvf_fma(op)?),
2292
2293 "vfwnmacc.vv" => Vfwnmaccvv(opfvv_fma(op)?),
2294 "vfwnmacc.vf" => Vfwnmaccvf(opfvf_fma(op)?),
2295
2296 "vfwmsac.vv" => Vfwmsacvv(opfvv_fma(op)?),
2297 "vfwmsac.vf" => Vfwmsacvf(opfvf_fma(op)?),
2298
2299 "vfwnmsac.vv" => Vfwnmsacvv(opfvv_fma(op)?),
2300 "vfwnmsac.vf" => Vfwnmsacvf(opfvf_fma(op)?),
2301
2302 "la" => {
2304 let (rd, mem_addr) =
2305 integer::pseudo::parse_op_memory_label_format(op, memory_labels)?;
2306
2307 Addi(I {
2308 rd,
2309 rs1: 0,
2310 imm12: mem_addr,
2311 })
2312 }
2313 "nop" => Addi(I {
2314 rd: 0,
2315 rs1: 0,
2316 imm12: 0,
2317 }),
2318 "li" => {
2319 let (reg, imm) = integer::pseudo::parse_op_imm_format(op)?;
2320
2321 match imm.cmp(&4096) {
2322 Ordering::Less => Addi(I {
2323 rd: reg,
2324 rs1: 0,
2325 imm12: imm,
2326 }),
2327 Ordering::Equal => Lui(U {
2328 rd: reg,
2329 imm20: imm,
2330 }),
2331 Ordering::Greater => fuse![
2332 Lui(U {
2333 rd: reg,
2334 imm20: imm >> 12,
2335 }),
2336 Addi(I {
2337 rd: reg,
2338 rs1: reg,
2339 imm12: imm & 0xfff,
2340 }),
2341 ],
2342 }
2343 }
2344 "mv" => {
2345 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2346 Addi(I { rd, rs1, imm12: 0 })
2347 }
2348 "not" => {
2349 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2350 Xori(I { rd, rs1, imm12: -1 })
2351 }
2352 "neg" => {
2353 let (rd, rs2) = integer::pseudo::parse_op_op_format(op)?;
2354 Sub(R { rd, rs1: 0, rs2 })
2355 }
2356 "negw" => {
2357 let (rd, rs2) = integer::pseudo::parse_op_op_format(op)?;
2358 Subw(R { rd, rs1: 0, rs2 })
2359 }
2360 "sext.b" => {
2361 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2362
2363 fuse![
2364 Slli(I {
2365 rd,
2366 rs1,
2367 imm12: 64 - 8,
2368 }),
2369 Srai(I {
2370 rd,
2371 rs1,
2372 imm12: 64 - 8,
2373 }),
2374 ]
2375 }
2376 "sext.h" => {
2377 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2378 fuse![
2379 Slli(I {
2380 rd,
2381 rs1,
2382 imm12: 64 - 16,
2383 }),
2384 Srai(I {
2385 rd,
2386 rs1,
2387 imm12: 64 - 16,
2388 }),
2389 ]
2390 }
2391 "sext.w" => {
2392 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2393 Addiw(I { rd, rs1, imm12: 0 })
2394 }
2395 "zext.b" => {
2396 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2397 Andi(I {
2398 rd,
2399 rs1,
2400 imm12: 0xff,
2401 })
2402 }
2403 "zext.h" => {
2404 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2405
2406 fuse![
2407 Slli(I {
2408 rd,
2409 rs1,
2410 imm12: 64 - 16,
2411 }),
2412 Srli(I {
2413 rd,
2414 rs1: rd,
2415 imm12: 64 - 16,
2416 }),
2417 ]
2418 }
2419 "zext.w" => {
2420 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2421
2422 fuse![
2423 Slli(I {
2424 rd,
2425 rs1,
2426 imm12: 64 - 32,
2427 }),
2428 Srli(I {
2429 rd,
2430 rs1: rd,
2431 imm12: 64 - 32,
2432 }),
2433 ]
2434 }
2435 "seqz" => {
2436 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2437 Sltiu(I { rd, rs1, imm12: 1 })
2438 }
2439 "snez" => {
2440 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2441 Sltu(R { rd, rs1, rs2: 0 })
2442 }
2443 "sltz" => {
2444 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2445 Slt(R { rd, rs1, rs2: 0 })
2446 }
2447 "sgtz" => {
2448 let (rd, rs1) = integer::pseudo::parse_op_op_format(op)?;
2449 Slt(R {
2450 rd,
2451 rs1: 0,
2452 rs2: rs1,
2453 })
2454 }
2455 "fmv.s" => {
2456 let (rd, rs1) = float::pseudo::parse_op_op_format(op)?;
2457 Fsgnjs(R { rd, rs1, rs2: rs1 })
2458 }
2459 "fabs.s" => {
2460 let (rd, rs1) = float::pseudo::parse_op_op_format(op)?;
2461 Fsgnjxs(R { rd, rs1, rs2: rs1 })
2462 }
2463 "fneg.s" => {
2464 let (rd, rs1) = float::pseudo::parse_op_op_format(op)?;
2465 Fsgnjns(R { rd, rs1, rs2: rs1 })
2466 }
2467 "fmv.d" => {
2468 let (rd, rs1) = float::pseudo::parse_op_op_format(op)?;
2469 Fsgnjd(R { rd, rs1, rs2: rs1 })
2470 }
2471 "fabs.d" => {
2472 let (rd, rs1) = float::pseudo::parse_op_op_format(op)?;
2473 Fsgnjxd(R { rd, rs1, rs2: rs1 })
2474 }
2475 "fneg.d" => {
2476 let (rd, rs1) = float::pseudo::parse_op_op_format(op)?;
2477 Fsgnjnd(R { rd, rs1, rs2: rs1 })
2478 }
2479 "beqz" => {
2480 let (rs1, diff) = integer::pseudo::parse_op_label_format(
2481 op,
2482 instruction_labels,
2483 current_address,
2484 )?;
2485 Beq(S {
2486 rs1,
2487 rs2: 0,
2488 imm12: diff,
2489 })
2490 }
2491 "bnez" => {
2492 let (rs1, diff) = integer::pseudo::parse_op_label_format(
2493 op,
2494 instruction_labels,
2495 current_address,
2496 )?;
2497 Bne(S {
2498 rs1,
2499 rs2: 0,
2500 imm12: diff,
2501 })
2502 }
2503 "blez" => {
2504 let (rs1, diff) = integer::pseudo::parse_op_label_format(
2505 op,
2506 instruction_labels,
2507 current_address,
2508 )?;
2509 Bge(S {
2510 rs1,
2511 rs2: 0,
2512 imm12: diff,
2513 })
2514 }
2515 "bgez" => {
2516 let (rs1, diff) = integer::pseudo::parse_op_label_format(
2517 op,
2518 instruction_labels,
2519 current_address,
2520 )?;
2521 Bge(S {
2522 rs1,
2523 rs2: 0,
2524 imm12: diff,
2525 })
2526 }
2527 "bltz" => {
2528 let (rs1, diff) = integer::pseudo::parse_op_label_format(
2529 op,
2530 instruction_labels,
2531 current_address,
2532 )?;
2533 Blt(S {
2534 rs1,
2535 rs2: 0,
2536 imm12: diff,
2537 })
2538 }
2539 "bgtz" => {
2540 let (rs1, diff) = integer::pseudo::parse_op_label_format(
2541 op,
2542 instruction_labels,
2543 current_address,
2544 )?;
2545 Blt(S {
2546 rs1,
2547 rs2: 0,
2548 imm12: diff,
2549 })
2550 }
2551 "bgt" => {
2552 let (rs1, rs2, diff) = integer::pseudo::parse_op_op_label_format(
2553 op,
2554 instruction_labels,
2555 current_address,
2556 )?;
2557 Blt(S {
2558 rs1: rs2,
2559 rs2: rs1,
2560 imm12: diff,
2561 })
2562 }
2563 "ble" => {
2564 let (rs1, rs2, diff) = integer::pseudo::parse_op_op_label_format(
2565 op,
2566 instruction_labels,
2567 current_address,
2568 )?;
2569 Bge(S {
2570 rs1: rs2,
2571 rs2: rs1,
2572 imm12: diff,
2573 })
2574 }
2575 "bgtu" => {
2576 let (rs1, rs2, diff) = integer::pseudo::parse_op_op_label_format(
2577 op,
2578 instruction_labels,
2579 current_address,
2580 )?;
2581 Bltu(S {
2582 rs1: rs2,
2583 rs2: rs1,
2584 imm12: diff,
2585 })
2586 }
2587 "bleu" => {
2588 let (rs1, rs2, diff) = integer::pseudo::parse_op_op_label_format(
2589 op,
2590 instruction_labels,
2591 current_address,
2592 )?;
2593 Bgeu(S {
2594 rs1: rs2,
2595 rs2: rs1,
2596 imm12: diff,
2597 })
2598 }
2599 "j" => {
2600 let diff =
2601 integer::pseudo::parse_label_format(op, instruction_labels, current_address)?;
2602 Jal(U { rd: 0, imm20: diff })
2603 }
2604 "jr" => {
2605 let rs1 = integer::pseudo::parse_op_format(op)?;
2606 Jalr(I {
2607 rd: 0,
2608 rs1,
2609 imm12: 0,
2610 })
2611 }
2612 "ret" => Jalr(I {
2613 rd: 0,
2614 rs1: 1,
2615 imm12: 0,
2616 }),
2617 "call" => {
2618 let diff =
2619 integer::pseudo::parse_label_format(op, instruction_labels, current_address)?;
2620
2621 fuse![
2622 Auipc(U {
2623 rd: 1,
2624 imm20: diff >> 12,
2625 }),
2626 Jalr(I {
2627 rd: 1,
2628 rs1: 1,
2629 imm12: diff & 0xfff,
2630 }),
2631 ]
2632 }
2633 "tail" => {
2634 let diff =
2635 integer::pseudo::parse_label_format(op, instruction_labels, current_address)?;
2636
2637 fuse![
2638 Auipc(U {
2639 rd: 6,
2640 imm20: diff >> 12,
2641 }),
2642 Jalr(I {
2643 rd: 0,
2644 rs1: 6,
2645 imm12: diff & 0xfff,
2646 }),
2647 ]
2648 }
2649 "rdinstret" => {
2650 let rd = integer::pseudo::parse_op_format(op)?;
2651 Csrrs(Csrr {
2652 rd,
2653 csr: alias::INSTRET,
2654 rs1: 0,
2655 })
2656 }
2657 "rdcycle" => {
2658 let rd = integer::pseudo::parse_op_format(op)?;
2659 Csrrs(Csrr {
2660 rd,
2661 csr: alias::CYCLE,
2662 rs1: 0,
2663 })
2664 }
2665 "rdtime" => {
2666 let rd = integer::pseudo::parse_op_format(op)?;
2667 Csrrs(Csrr {
2668 rd,
2669 csr: alias::TIME,
2670 rs1: 0,
2671 })
2672 }
2673 "csrr" => {
2674 let (rd, csr) = csr::pseudo::parse_op_csr_format(op)?;
2675 Csrrs(Csrr { rd, csr, rs1: 0 })
2676 }
2677 "csrw" => {
2678 let (csr, rs1) = csr::pseudo::parse_csr_op_format(op)?;
2679 Csrrw(Csrr { rd: 0, csr, rs1 })
2680 }
2681 "csrs" => {
2682 let (csr, rs1) = csr::pseudo::parse_csr_op_format(op)?;
2683 Csrrs(Csrr { rd: 0, csr, rs1 })
2684 }
2685 "csrc" => {
2686 let (csr, rs1) = csr::pseudo::parse_csr_op_format(op)?;
2687 Csrrc(Csrr { rd: 0, csr, rs1 })
2688 }
2689 "frcsr" => {
2690 let rd = integer::pseudo::parse_op_format(op)?;
2691 Csrrs(Csrr {
2692 rd,
2693 csr: alias::FCSR,
2694 rs1: 0,
2695 })
2696 }
2697 "fscsr" => match integer::pseudo::parse_op_op_format(op) {
2698 Ok((rd, rs1)) => Csrrw(Csrr {
2699 rd,
2700 csr: alias::FCSR,
2701 rs1,
2702 }),
2703 Err(fst_err) => match integer::pseudo::parse_op_format(op) {
2704 Ok(rs) => Csrrw(Csrr {
2705 rd: 0,
2706 csr: alias::FCSR,
2707 rs1: rs,
2708 }),
2709 Err(snd_err) => return Err(format!("{} or {}", fst_err, snd_err)),
2710 },
2711 },
2712 "frrm" => {
2713 let rd = integer::pseudo::parse_op_format(op)?;
2714 Csrrs(Csrr {
2715 rd,
2716 csr: alias::FRM,
2717 rs1: 0,
2718 })
2719 }
2720 "fsrm" => match integer::pseudo::parse_op_op_format(op) {
2721 Ok((rd, rs1)) => Csrrw(Csrr {
2722 rd,
2723 csr: alias::FRM,
2724 rs1,
2725 }),
2726 Err(fst_err) => match integer::pseudo::parse_op_format(op) {
2727 Ok(rs) => Csrrw(Csrr {
2728 rd: 0,
2729 csr: alias::FRM,
2730 rs1: rs,
2731 }),
2732 Err(snd_err) => return Err(format!("{} or {}", fst_err, snd_err)),
2733 },
2734 },
2735 "fsrmi" => match integer::pseudo::parse_op_imm_format(op) {
2736 Ok((rd, imm)) => Csrrwi(Csri {
2737 rd,
2738 csr: alias::FRM,
2739 uimm: imm as u32 as usize,
2740 }),
2741 Err(fst_err) => match integer::pseudo::parse_imm_format(op) {
2742 Ok(imm) => Csrrwi(Csri {
2743 rd: 0,
2744 csr: alias::FRM,
2745 uimm: imm as u32 as usize,
2746 }),
2747 Err(snd_err) => return Err(format!("{} or {}", fst_err, snd_err)),
2748 },
2749 },
2750 "frflags" => {
2751 let rd = integer::pseudo::parse_op_format(op)?;
2752 Csrrs(Csrr {
2753 rd,
2754 csr: alias::FFLAGS,
2755 rs1: 0,
2756 })
2757 }
2758 "fsflags" => match integer::pseudo::parse_op_op_format(op) {
2759 Ok((rd, rs1)) => Csrrw(Csrr {
2760 rd,
2761 csr: alias::FFLAGS,
2762 rs1,
2763 }),
2764 Err(fst_err) => match integer::pseudo::parse_op_format(op) {
2765 Ok(rs1) => Csrrw(Csrr {
2766 rd: 0,
2767 csr: alias::FFLAGS,
2768 rs1,
2769 }),
2770 Err(snd_err) => return Err(format!("{} or {}", fst_err, snd_err)),
2771 },
2772 },
2773 "fsflagsi" => match integer::pseudo::parse_op_imm_format(op) {
2774 Ok((rd, imm)) => Csrrwi(Csri {
2775 rd,
2776 csr: alias::FFLAGS,
2777 uimm: imm as u32 as usize,
2778 }),
2779 Err(fst_err) => match integer::pseudo::parse_imm_format(op) {
2780 Ok(imm) => Csrrwi(Csri {
2781 rd: 0,
2782 csr: alias::FFLAGS,
2783 uimm: imm as u32 as usize,
2784 }),
2785 Err(snd_err) => return Err(format!("{} or {}", fst_err, snd_err)),
2786 },
2787 },
2788
2789 "vneg.v" => {
2790 let (vd, vs2, vm) = vector::pseudo::parse_op_op_mask_format(op)?;
2791 Vrsubvx(Opivx {
2792 vd,
2793 rs1: alias::ZERO,
2794 vs2,
2795 vm,
2796 })
2797 }
2798 "vwcvt.x.x.v" => {
2799 let (vd, vs2, vm) = vector::pseudo::parse_op_op_mask_format(op)?;
2800 Vwaddvx(Opmvx {
2801 dest: vd,
2802 rs1: alias::ZERO,
2803 vs2,
2804 vm,
2805 })
2806 }
2807 "vwcvtu.x.x.v" => {
2808 let (vd, vs2, vm) = vector::pseudo::parse_op_op_mask_format(op)?;
2809 Vwadduvx(Opmvx {
2810 dest: vd,
2811 rs1: alias::ZERO,
2812 vs2,
2813 vm,
2814 })
2815 }
2816 "vnot.v" => {
2817 let (vd, vs2, vm) = vector::pseudo::parse_op_op_mask_format(op)?;
2818 Vxorvi(Opivi {
2819 vd,
2820 imm5: -1,
2821 vs2,
2822 vm,
2823 })
2824 }
2825 "vncvt.x.x.w" => {
2826 let (vd, vs2, vm) = vector::pseudo::parse_op_op_mask_format(op)?;
2827 Vnsrlwx(Opivx {
2828 vd,
2829 rs1: alias::ZERO,
2830 vs2,
2831 vm,
2832 })
2833 }
2834 "vmsgt.vv" => {
2835 let (vd, vs2, vs1, vm) = vector::pseudo::parse_op_op_op_mask_format(op)?;
2836 Vmsltvv(Opivv {
2837 vd,
2838 vs1: vs2,
2839 vs2: vs1,
2840 vm,
2841 })
2842 }
2843 "vmsgtu.vv" => {
2844 let (vd, vs2, vs1, vm) = vector::pseudo::parse_op_op_op_mask_format(op)?;
2845 Vmsltuvv(Opivv {
2846 vd,
2847 vs1: vs2,
2848 vs2: vs1,
2849 vm,
2850 })
2851 }
2852 "vmsge.vv" => {
2853 let (vd, vs2, vs1, vm) = vector::pseudo::parse_op_op_op_mask_format(op)?;
2854 Vmslevv(Opivv {
2855 vd,
2856 vs1: vs2,
2857 vs2: vs1,
2858 vm,
2859 })
2860 }
2861 "vmsgeu.vv" => {
2862 let (vd, vs2, vs1, vm) = vector::pseudo::parse_op_op_op_mask_format(op)?;
2863 Vmsleuvv(Opivv {
2864 vd,
2865 vs1: vs2,
2866 vs2: vs1,
2867 vm,
2868 })
2869 }
2870 "vmslt.vi" => {
2871 let (vd, vs2, imm, vm) = vector::pseudo::parse_op_op_imm_mask_format(op)?;
2872 Vmslevi(Opivi {
2873 vd,
2874 imm5: imm - 1,
2875 vs2,
2876 vm,
2877 })
2878 }
2879 "vmsltu.vi" => {
2880 let (vd, vs2, imm, vm) = vector::pseudo::parse_op_op_imm_mask_format(op)?;
2881 Vmsleuvi(Opivi {
2882 vd,
2883 imm5: imm - 1,
2884 vs2,
2885 vm,
2886 })
2887 }
2888 "vmsge.vi" => {
2889 let (vd, vs2, imm, vm) = vector::pseudo::parse_op_op_imm_mask_format(op)?;
2890 Vmsgtvi(Opivi {
2891 vd,
2892 imm5: imm - 1,
2893 vs2,
2894 vm,
2895 })
2896 }
2897 "vmsgeu.vi" => {
2898 let (vd, vs2, imm, vm) = vector::pseudo::parse_op_op_imm_mask_format(op)?;
2899 Vmsgtuvi(Opivi {
2900 vd,
2901 imm5: imm - 1,
2902 vs2,
2903 vm,
2904 })
2905 }
2906 "vmsge.vx" => match vector::pseudo::parse_op_op_xreg_format(op) {
2907 Ok((vd, vs2, rs1)) => fuse![
2908 Vmsltvx(Opivx {
2909 vd,
2910 rs1,
2911 vs2,
2912 vm: false,
2913 }),
2914 Vmnandmm(Opmvv {
2915 dest: vd,
2916 vs1: vd,
2917 vs2: vd,
2918 vm: false,
2919 }),
2920 ],
2921 Err(fst_err) => match vector::pseudo::parse_op_op_xreg_mask_vd_nonzero_format(op) {
2922 Ok((vd, vs2, rs1)) => fuse![
2923 Vmsltvx(Opivx {
2924 vd,
2925 rs1,
2926 vs2,
2927 vm: true,
2928 }),
2929 Vmxormm(Opmvv {
2930 dest: vd,
2931 vs1: 0,
2932 vs2: vd,
2933 vm: false,
2934 }),
2935 ],
2936 Err(snd_err) => match vector::pseudo::parse_op_op_xreg_mask_temp_format(op) {
2937 Ok((vd, vs2, rs1, vt)) => {
2938 if vd == 0 {
2939 fuse![
2940 Vmsltvx(Opivx {
2941 vd: vt,
2942 rs1,
2943 vs2,
2944 vm: false,
2945 }),
2946 Vmandnmm(Opmvv {
2947 dest: vd,
2948 vs1: vt,
2949 vs2: vd,
2950 vm: false,
2951 }),
2952 ]
2953 } else {
2954 fuse![
2955 Vmsltvx(Opivx {
2956 vd: vt,
2957 rs1,
2958 vs2,
2959 vm: false,
2960 }),
2961 Vmandnmm(Opmvv {
2962 dest: vt,
2963 vs1: vt,
2964 vs2: 0,
2965 vm: false,
2966 }),
2967 Vmandnmm(Opmvv {
2968 dest: vd,
2969 vs1: 0,
2970 vs2: vd,
2971 vm: false,
2972 }),
2973 Vmormm(Opmvv {
2974 dest: vd,
2975 vs1: vd,
2976 vs2: vt,
2977 vm: false,
2978 }),
2979 ]
2980 }
2981 }
2982 Err(trd_err) => {
2983 return Err(format!("{}, {} or {}", fst_err, snd_err, trd_err))
2984 }
2985 },
2986 },
2987 },
2988 "vmsgeu.vx" => match vector::pseudo::parse_op_op_xreg_format(op) {
2989 Ok((vd, vs2, rs1)) => fuse![
2990 Vmsltuvx(Opivx {
2991 vd,
2992 rs1,
2993 vs2,
2994 vm: false,
2995 }),
2996 Vmnandmm(Opmvv {
2997 dest: vd,
2998 vs1: vd,
2999 vs2: vd,
3000 vm: false,
3001 })
3002 ],
3003 Err(fst_err) => match vector::pseudo::parse_op_op_xreg_mask_vd_nonzero_format(op) {
3004 Ok((vd, vs2, rs1)) => fuse![
3005 Vmsltuvx(Opivx {
3006 vd,
3007 rs1,
3008 vs2,
3009 vm: true,
3010 }),
3011 Vmxormm(Opmvv {
3012 dest: vd,
3013 vs1: 0,
3014 vs2: vd,
3015 vm: false,
3016 })
3017 ],
3018 Err(snd_err) => match vector::pseudo::parse_op_op_xreg_mask_temp_format(op) {
3019 Ok((vd, vs2, rs1, vt)) => {
3020 if vd == 0 {
3021 fuse![
3022 Vmsltuvx(Opivx {
3023 vd: vt,
3024 rs1,
3025 vs2,
3026 vm: false,
3027 }),
3028 Vmandnmm(Opmvv {
3029 dest: vd,
3030 vs1: vt,
3031 vs2: vd,
3032 vm: false,
3033 }),
3034 ]
3035 } else {
3036 fuse![
3037 Vmsltuvx(Opivx {
3038 vd: vt,
3039 rs1,
3040 vs2,
3041 vm: false,
3042 }),
3043 Vmandnmm(Opmvv {
3044 dest: vt,
3045 vs1: vt,
3046 vs2: 0,
3047 vm: false,
3048 }),
3049 Vmandnmm(Opmvv {
3050 dest: vd,
3051 vs1: 0,
3052 vs2: vd,
3053 vm: false,
3054 }),
3055 Vmormm(Opmvv {
3056 dest: vd,
3057 vs1: vd,
3058 vs2: vt,
3059 vm: false,
3060 })
3061 ]
3062 }
3063 }
3064 Err(trd_err) => {
3065 return Err(format!("{}, {} or {}", fst_err, snd_err, trd_err))
3066 }
3067 },
3068 },
3069 },
3070 "vfneg.v" => {
3071 let (vd, vs2, vm) = vector::pseudo::parse_op_op_mask_format(op)?;
3072 Vfsgnjnvv(Opfvv {
3073 dest: vd,
3074 vs1: vs2,
3075 vs2,
3076 vm,
3077 })
3078 }
3079 "vfabs.v" => {
3080 let (vd, vs2, vm) = vector::pseudo::parse_op_op_mask_format(op)?;
3081 Vfsgnjxvv(Opfvv {
3082 dest: vd,
3083 vs1: vs2,
3084 vs2,
3085 vm,
3086 })
3087 }
3088 "vmfgt.vv" => {
3089 let (vd, vs2, vs1, vm) = vector::pseudo::parse_op_op_op_mask_format(op)?;
3090 Vmfltvv(Opfvv {
3091 dest: vd,
3092 vs1: vs2,
3093 vs2: vs1,
3094 vm,
3095 })
3096 }
3097 "vmfge.vv" => {
3098 let (vd, vs2, vs1, vm) = vector::pseudo::parse_op_op_op_mask_format(op)?;
3099 Vmflevv(Opfvv {
3100 dest: vd,
3101 vs1: vs2,
3102 vs2: vs1,
3103 vm,
3104 })
3105 }
3106 "vmmv.m" => {
3107 let (vd, vs2) = vector::pseudo::parse_op_op_format(op)?;
3108 Vmandmm(Opmvv {
3109 dest: vd,
3110 vs1: vs2,
3111 vs2,
3112 vm: false,
3113 })
3114 }
3115 "vmclr.m" => {
3116 let vd = vector::pseudo::parse_op_format(op)?;
3117 Vmxormm(Opmvv {
3118 dest: vd,
3119 vs1: vd,
3120 vs2: vd,
3121 vm: false,
3122 })
3123 }
3124 "vmset.m" => {
3125 let vd = vector::pseudo::parse_op_format(op)?;
3126 Vmxnormm(Opmvv {
3127 dest: vd,
3128 vs1: vd,
3129 vs2: vd,
3130 vm: false,
3131 })
3132 }
3133 "vmnot.m" => {
3134 let (vd, vs2) = vector::pseudo::parse_op_op_format(op)?;
3135 Vmnandmm(Opmvv {
3136 dest: vd,
3137 vs1: vs2,
3138 vs2,
3139 vm: false,
3140 })
3141 }
3142 _ => return Err(format!("Unknown mnemonic: {}", mnemonic)),
3143 };
3144
3145 Ok(instruction)
3146 }
3147
3148 pub fn decode_data_section(data_line: &str) -> Result<Data, String> {
3149 let (data_type, values) = Self::split_instruction(data_line);
3150
3151 match data_type {
3152 ".byte" => data::parse_bytes(values),
3153 ".2byte" | ".half" | ".short" => data::parse_halves(values),
3154 ".4byte" | ".word" | ".long" => data::parse_words(values),
3155 ".8byte" | ".dword" | ".quad" => data::parse_quads(values),
3156 ".float" => data::parse_floats(values),
3157 ".double" => data::parse_doubles(values),
3158 ".string" => data::parse_string(values),
3159 ".asciz" => data::parse_asciz(values),
3160 ".zero" => data::parse_zero(values),
3161 _ => Err(format!("Unknown data type: {}", data_type)),
3162 }
3163 }
3164
3165 fn rename(old: &str) -> &str {
3166 match old {
3167 "vle1.v" => "vlm.v",
3168 "vse1.v" => "vsm.v",
3169 "vfredsum.vs" => "vfredusum.vs",
3170 "vfwredsum.vs" => "vfwredusum.vs",
3171 "vmandnot.mm" => "vmandn.mm",
3172 "vmornot.mm" => "vmorn.mm",
3173 "vpopc.m" => "vcpop.m",
3174 "vfrsqrte7.v" => "vfrsqrt7.v",
3175 "vfrece7.v" => "vfrec7.v",
3176 "vmcpy.m" => "vmmv.m",
3177
3178 "vl1r.v" => "vl1re8.v",
3180 "vl2r.v" => "vl2re8.v",
3181 "vl4r.v" => "vl4re8.v",
3182 "vl8r.v" => "vl8re8.v",
3183
3184 _ => old,
3185 }
3186 }
3187
3188 fn split_instruction(instruction_line: &str) -> (&str, &str) {
3189 let mut lane = instruction_line.splitn(2, char::is_whitespace);
3190 let mnemonic = lane.next().unwrap_or_default().trim();
3191 let operands = lane.next().unwrap_or_default().trim();
3192 (mnemonic, operands)
3193 }
3194}
3195
3196#[cfg(test)]
3197mod tests {
3198 use super::*;
3199
3200 #[test]
3201 fn rename_correctly() {
3202 let old_mnemonics = [
3203 "vle1.v",
3204 "vse1.v",
3205 "vfredsum.vs",
3206 "vfwredsum.vs",
3207 "vmandnot.mm",
3208 "vmornot.mm",
3209 "vpopc.m",
3210 "vfrsqrte7.v",
3211 "vfrece7.v",
3212 "vmcpy.m",
3213 ];
3214
3215 old_mnemonics
3216 .map(|mnemonic| (mnemonic, Decoder::rename(mnemonic)))
3217 .iter()
3218 .for_each(|(old, new)| assert_ne!(old, new));
3219 }
3220
3221 #[test]
3222 fn la_works() {
3223 let mut memory_labels = HashMap::new();
3224
3225 memory_labels.insert("to_copy".to_owned(), 12);
3226
3227 let instruction =
3228 Decoder::decode_text_section("la x1, to_copy", &HashMap::new(), &memory_labels, 0);
3229
3230 assert_eq!(
3231 instruction,
3232 Ok(fuse![
3233 Auipc(U { rd: 1, imm20: 0 }),
3234 Addi(I {
3235 rd: 1,
3236 rs1: 1,
3237 imm12: 12
3238 })
3239 ])
3240 );
3241 }
3242
3243 #[test]
3244 fn la_works_far() {
3245 let mut memory_labels = HashMap::new();
3246
3247 memory_labels.insert("to_copy".to_owned(), 5000);
3248
3249 let instruction =
3250 Decoder::decode_text_section("la x1, to_copy", &HashMap::new(), &memory_labels, 0);
3251
3252 assert_eq!(
3253 instruction,
3254 Ok(fuse![
3255 Auipc(U { rd: 1, imm20: 1 }),
3256 Addi(I {
3257 rd: 1,
3258 rs1: 1,
3259 imm12: 904
3260 })
3261 ])
3262 );
3263 }
3264
3265 #[test]
3266 fn memcpy_works() {
3267 let mut memory_labels = HashMap::new();
3268
3269 memory_labels.insert("to_copy".to_owned(), 5000);
3270
3271 let instruction =
3272 Decoder::decode_text_section("la x1, to_copy", &HashMap::new(), &memory_labels, 0);
3273
3274 assert_eq!(
3275 instruction,
3276 Ok(fuse![
3277 Auipc(U { rd: 1, imm20: 1 }),
3278 Addi(I {
3279 rd: 1,
3280 rs1: 1,
3281 imm12: 904
3282 })
3283 ])
3284 );
3285 }
3286}