memcpy/
main.rs

1use eeric_core::prelude::*;
2use eeric_core::vtype;
3
4use format as F;
5use Instruction as I;
6
7// Example:
8// loop:
9//    vsetvli t0, a2, e8, m8, ta, ma   # Vectors of 8b
10//    vle8.v v0, (a1)               # Load bytes
11//      add a1, a1, t0              # Bump pointer
12//      sub a2, a2, t0              # Decrement count
13//    vse8.v v0, (a3)               # Store bytes
14//      add a3, a3, t0              # Bump pointer
15//      bnez a2, loop               # Any more?
16//      ret
17
18fn main() {
19    // Important note: eeric as low-level back-end abstraction layer does not support pseudo-instructions
20    // Burden of decoding pseudo-instructions is on the front-end layer
21    // E.G: ret == I::Jalr (F::I { rd: ZERO, rs1: RA, imm: 0 }),
22
23    use alias::*;
24
25    let mut core = RvCoreBuilder::default()
26        .instructions(vec![
27            I::Vsetvli(F::Vsetvli {
28                rd: T0,
29                rs1: A2,
30                vtypei: vtype!(e8, m8, ta, ma),
31            }),
32            I::Vlv {
33                eew: BaseSew::E8,
34                data: F::Vl {
35                    vd: 0,
36                    rs1: A1,
37                    vm: false,
38                },
39            },
40            I::Add(F::R {
41                rd: A1,
42                rs1: A1,
43                rs2: T0,
44            }),
45            I::Sub(F::R {
46                rd: A2,
47                rs1: A2,
48                rs2: T0,
49            }),
50            I::Vsv {
51                eew: BaseSew::E8,
52                data: F::Vs {
53                    vs3: 0,
54                    rs1: A3,
55                    vm: false,
56                },
57            },
58            I::Add(F::R {
59                rd: A3,
60                rs1: A3,
61                rs2: T0,
62            }),
63            I::Bne(F::S {
64                rs1: A2,
65                rs2: ZERO,
66                imm12: -24,
67            }),
68            I::Jalr(F::I {
69                rd: ZERO,
70                rs1: RA,
71                imm12: 0,
72            }),
73        ])
74        .build();
75
76    for machine_state in core.run() {
77        println!("{:?}", machine_state);
78    }
79}
memcpy/main.rs

memcpy/
main.rs
