1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "UART register block, DW_apb_uart"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Uart {
9 ptr: *mut u8,
10}
11unsafe impl Send for Uart {}
12unsafe impl Sync for Uart {}
13impl Uart {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "Divisor latch low. when LCR\\[7\\]
23bit = 1"]
24 #[inline(always)]
25 pub const fn dll(self) -> crate::common::Reg<regs::Dll, crate::common::RW> {
26 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
27 }
28 #[doc = "Receiver buffer register. when LCR\\[7\\]
29bit = 0"]
30 #[inline(always)]
31 pub const fn rbr(self) -> crate::common::Reg<regs::Rbr, crate::common::R> {
32 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
33 }
34 #[doc = "Transmitter holding register. when LCR\\[7\\]
35bit = 0"]
36 #[inline(always)]
37 pub const fn thr(self) -> crate::common::Reg<regs::Thr, crate::common::W> {
38 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
39 }
40 #[doc = "Divisor latch high. when LCR\\[7\\]
41bit = 1"]
42 #[inline(always)]
43 pub const fn dlh(self) -> crate::common::Reg<regs::Dlh, crate::common::RW> {
44 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
45 }
46 #[doc = "Interrupt enable register. when LCR\\[7\\]
47bit = 0"]
48 #[inline(always)]
49 pub const fn ier(self) -> crate::common::Reg<regs::Ier, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
51 }
52 #[doc = "FIFO control register."]
53 #[inline(always)]
54 pub const fn fcr(self) -> crate::common::Reg<regs::Fcr, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
56 }
57 #[doc = "Interrupt identification register."]
58 #[inline(always)]
59 pub const fn iir(self) -> crate::common::Reg<regs::Iir, crate::common::R> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
61 }
62 #[doc = "Line control register."]
63 #[inline(always)]
64 pub const fn lcr(self) -> crate::common::Reg<regs::Lcr, crate::common::RW> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
66 }
67 #[doc = "Modem control register."]
68 #[inline(always)]
69 pub const fn mcr(self) -> crate::common::Reg<regs::Mcr, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
71 }
72 #[doc = "Line status register."]
73 #[inline(always)]
74 pub const fn lsr(self) -> crate::common::Reg<regs::Lsr, crate::common::RW> {
75 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
76 }
77 #[doc = "Modem status register."]
78 #[inline(always)]
79 pub const fn msr(self) -> crate::common::Reg<regs::Msr, crate::common::RW> {
80 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
81 }
82 #[doc = "Scratch register."]
83 #[inline(always)]
84 pub const fn scr(self) -> crate::common::Reg<regs::Scr, crate::common::RW> {
85 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
86 }
87 #[doc = "Low power divisor latch low."]
88 #[inline(always)]
89 pub const fn lpdll(self) -> crate::common::Reg<regs::Dll, crate::common::RW> {
90 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
91 }
92 #[doc = "Low power divisor latch high."]
93 #[inline(always)]
94 pub const fn lpdlh(self) -> crate::common::Reg<regs::Dlh, crate::common::RW> {
95 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
96 }
97 #[doc = "Shadow receiver buffer register."]
98 #[inline(always)]
99 pub const fn srbr(self, n: usize) -> crate::common::Reg<regs::Rbr, crate::common::R> {
100 assert!(n < 16usize);
101 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize + n * 4usize) as _) }
102 }
103 #[doc = "Shadow transmitter holding register."]
104 #[inline(always)]
105 pub const fn sthr(self, n: usize) -> crate::common::Reg<regs::Thr, crate::common::W> {
106 assert!(n < 16usize);
107 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize + n * 4usize) as _) }
108 }
109 #[doc = "FIFO access register."]
110 #[inline(always)]
111 pub const fn far(self) -> crate::common::Reg<regs::Far, crate::common::RW> {
112 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) }
113 }
114 #[doc = "Transmit FIFO read."]
115 #[inline(always)]
116 pub const fn tfr(self) -> crate::common::Reg<regs::Tfr, crate::common::RW> {
117 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) }
118 }
119 #[doc = "Receive FIFO write."]
120 #[inline(always)]
121 pub const fn rfw(self) -> crate::common::Reg<regs::Rfw, crate::common::RW> {
122 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) }
123 }
124 #[doc = "UART status register."]
125 #[inline(always)]
126 pub const fn usr(self) -> crate::common::Reg<regs::Usr, crate::common::RW> {
127 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) }
128 }
129 #[doc = "Transmit FIFO level."]
130 #[inline(always)]
131 pub const fn tfl(self) -> crate::common::Reg<u32, crate::common::RW> {
132 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
133 }
134 #[doc = "Receive FIFO level."]
135 #[inline(always)]
136 pub const fn rfl(self) -> crate::common::Reg<u32, crate::common::RW> {
137 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) }
138 }
139 #[doc = "Software reset register."]
140 #[inline(always)]
141 pub const fn srr(self) -> crate::common::Reg<regs::Srr, crate::common::RW> {
142 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
143 }
144 #[doc = "Shadow request to send."]
145 #[inline(always)]
146 pub const fn srts(self) -> crate::common::Reg<regs::Srts, crate::common::RW> {
147 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) }
148 }
149 #[doc = "Shadow break control register."]
150 #[inline(always)]
151 pub const fn sbcr(self) -> crate::common::Reg<regs::Sbcr, crate::common::RW> {
152 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) }
153 }
154 #[doc = "Shadow DMA mode."]
155 #[inline(always)]
156 pub const fn sdmam(self) -> crate::common::Reg<regs::Sdmam, crate::common::RW> {
157 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) }
158 }
159 #[doc = "Shadow FIFO enable."]
160 #[inline(always)]
161 pub const fn sfe(self) -> crate::common::Reg<regs::Sfe, crate::common::RW> {
162 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) }
163 }
164 #[doc = "Shadow RCVR trigger."]
165 #[inline(always)]
166 pub const fn srt(self) -> crate::common::Reg<regs::Srt, crate::common::RW> {
167 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) }
168 }
169 #[doc = "Shadow TX empty trigger."]
170 #[inline(always)]
171 pub const fn stet(self) -> crate::common::Reg<regs::Stet, crate::common::RW> {
172 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) }
173 }
174 #[doc = "Halt TX."]
175 #[inline(always)]
176 pub const fn htx(self) -> crate::common::Reg<regs::Htx, crate::common::RW> {
177 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) }
178 }
179 #[doc = "DMA software acknowledge."]
180 #[inline(always)]
181 pub const fn dmasa(self) -> crate::common::Reg<regs::Dmasa, crate::common::RW> {
182 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf0usize) as _) }
183 }
184 #[doc = "Component parameter register."]
185 #[inline(always)]
186 pub const fn cpr(self) -> crate::common::Reg<regs::Cpr, crate::common::R> {
187 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf4usize) as _) }
188 }
189 #[doc = "UART component version."]
190 #[inline(always)]
191 pub const fn ucv(self) -> crate::common::Reg<regs::Ucv, crate::common::RW> {
192 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf8usize) as _) }
193 }
194 #[doc = "Component type register."]
195 #[inline(always)]
196 pub const fn ctr(self) -> crate::common::Reg<regs::Ctr, crate::common::RW> {
197 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xfcusize) as _) }
198 }
199}
200pub mod common {
201 use core::marker::PhantomData;
202 #[derive(Copy, Clone, PartialEq, Eq)]
203 pub struct RW;
204 #[derive(Copy, Clone, PartialEq, Eq)]
205 pub struct R;
206 #[derive(Copy, Clone, PartialEq, Eq)]
207 pub struct W;
208 mod sealed {
209 use super::*;
210 pub trait Access {}
211 impl Access for R {}
212 impl Access for W {}
213 impl Access for RW {}
214 }
215 pub trait Access: sealed::Access + Copy {}
216 impl Access for R {}
217 impl Access for W {}
218 impl Access for RW {}
219 pub trait Read: Access {}
220 impl Read for RW {}
221 impl Read for R {}
222 pub trait Write: Access {}
223 impl Write for RW {}
224 impl Write for W {}
225 #[derive(Copy, Clone, PartialEq, Eq)]
226 pub struct Reg<T: Copy, A: Access> {
227 ptr: *mut u8,
228 phantom: PhantomData<*mut (T, A)>,
229 }
230 unsafe impl<T: Copy, A: Access> Send for Reg<T, A> {}
231 unsafe impl<T: Copy, A: Access> Sync for Reg<T, A> {}
232 impl<T: Copy, A: Access> Reg<T, A> {
233 #[allow(clippy::missing_safety_doc)]
234 #[inline(always)]
235 pub const unsafe fn from_ptr(ptr: *mut T) -> Self {
236 Self {
237 ptr: ptr as _,
238 phantom: PhantomData,
239 }
240 }
241 #[inline(always)]
242 pub const fn as_ptr(&self) -> *mut T {
243 self.ptr as _
244 }
245 }
246 impl<T: Copy, A: Read> Reg<T, A> {
247 #[inline(always)]
248 pub fn read(&self) -> T {
249 unsafe { (self.ptr as *mut T).read_volatile() }
250 }
251 }
252 impl<T: Copy, A: Write> Reg<T, A> {
253 #[inline(always)]
254 pub fn write_value(&self, val: T) {
255 unsafe { (self.ptr as *mut T).write_volatile(val) }
256 }
257 }
258 impl<T: Default + Copy, A: Write> Reg<T, A> {
259 #[inline(always)]
260 pub fn write<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
261 let mut val = Default::default();
262 let res = f(&mut val);
263 self.write_value(val);
264 res
265 }
266 }
267 impl<T: Copy, A: Read + Write> Reg<T, A> {
268 #[inline(always)]
269 pub fn modify<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
270 let mut val = self.read();
271 let res = f(&mut val);
272 self.write_value(val);
273 res
274 }
275 }
276}
277pub mod regs {
278 #[doc = "Component parameter register"]
279 #[repr(transparent)]
280 #[derive(Copy, Clone, Eq, PartialEq)]
281 pub struct Cpr(pub u32);
282 impl Cpr {
283 #[doc = "APB data width"]
284 #[inline(always)]
285 pub const fn apb_data_width(&self) -> u8 {
286 let val = (self.0 >> 0usize) & 0x03;
287 val as u8
288 }
289 #[doc = "APB data width"]
290 #[inline(always)]
291 pub fn set_apb_data_width(&mut self, val: u8) {
292 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
293 }
294 #[doc = "Auto flow control enable mode"]
295 #[inline(always)]
296 pub const fn afce_mode(&self) -> bool {
297 let val = (self.0 >> 4usize) & 0x01;
298 val != 0
299 }
300 #[doc = "Auto flow control enable mode"]
301 #[inline(always)]
302 pub fn set_afce_mode(&mut self, val: bool) {
303 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
304 }
305 #[doc = "THRE mode"]
306 #[inline(always)]
307 pub const fn thre_mode(&self) -> bool {
308 let val = (self.0 >> 5usize) & 0x01;
309 val != 0
310 }
311 #[doc = "THRE mode"]
312 #[inline(always)]
313 pub fn set_thre_mode(&mut self, val: bool) {
314 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
315 }
316 #[doc = "SIR mode"]
317 #[inline(always)]
318 pub const fn sir_mode(&self) -> bool {
319 let val = (self.0 >> 6usize) & 0x01;
320 val != 0
321 }
322 #[doc = "SIR mode"]
323 #[inline(always)]
324 pub fn set_sir_mode(&mut self, val: bool) {
325 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
326 }
327 #[doc = "SIR low power mode"]
328 #[inline(always)]
329 pub const fn sir_lp_mode(&self) -> bool {
330 let val = (self.0 >> 7usize) & 0x01;
331 val != 0
332 }
333 #[doc = "SIR low power mode"]
334 #[inline(always)]
335 pub fn set_sir_lp_mode(&mut self, val: bool) {
336 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
337 }
338 #[doc = "Additional features"]
339 #[inline(always)]
340 pub const fn additional_feat(&self) -> bool {
341 let val = (self.0 >> 8usize) & 0x01;
342 val != 0
343 }
344 #[doc = "Additional features"]
345 #[inline(always)]
346 pub fn set_additional_feat(&mut self, val: bool) {
347 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
348 }
349 #[doc = "FIFO access"]
350 #[inline(always)]
351 pub const fn fifo_access(&self) -> bool {
352 let val = (self.0 >> 9usize) & 0x01;
353 val != 0
354 }
355 #[doc = "FIFO access"]
356 #[inline(always)]
357 pub fn set_fifo_access(&mut self, val: bool) {
358 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
359 }
360 #[doc = "FIFO status"]
361 #[inline(always)]
362 pub const fn fifo_stat(&self) -> bool {
363 let val = (self.0 >> 10usize) & 0x01;
364 val != 0
365 }
366 #[doc = "FIFO status"]
367 #[inline(always)]
368 pub fn set_fifo_stat(&mut self, val: bool) {
369 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
370 }
371 #[doc = "Shadow"]
372 #[inline(always)]
373 pub const fn shadow(&self) -> bool {
374 let val = (self.0 >> 11usize) & 0x01;
375 val != 0
376 }
377 #[doc = "Shadow"]
378 #[inline(always)]
379 pub fn set_shadow(&mut self, val: bool) {
380 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
381 }
382 #[doc = "UART additional encoded parameters"]
383 #[inline(always)]
384 pub const fn uart_add_encoded_params(&self) -> bool {
385 let val = (self.0 >> 12usize) & 0x01;
386 val != 0
387 }
388 #[doc = "UART additional encoded parameters"]
389 #[inline(always)]
390 pub fn set_uart_add_encoded_params(&mut self, val: bool) {
391 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
392 }
393 #[doc = "DMA extra"]
394 #[inline(always)]
395 pub const fn dma_extra(&self) -> bool {
396 let val = (self.0 >> 13usize) & 0x01;
397 val != 0
398 }
399 #[doc = "DMA extra"]
400 #[inline(always)]
401 pub fn set_dma_extra(&mut self, val: bool) {
402 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
403 }
404 #[doc = "FIFO mode"]
405 #[inline(always)]
406 pub const fn fifo_mode(&self) -> u8 {
407 let val = (self.0 >> 16usize) & 0xff;
408 val as u8
409 }
410 #[doc = "FIFO mode"]
411 #[inline(always)]
412 pub fn set_fifo_mode(&mut self, val: u8) {
413 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
414 }
415 }
416 impl Default for Cpr {
417 #[inline(always)]
418 fn default() -> Cpr {
419 Cpr(0)
420 }
421 }
422 #[doc = "Component type register"]
423 #[repr(transparent)]
424 #[derive(Copy, Clone, Eq, PartialEq)]
425 pub struct Ctr(pub u32);
426 impl Ctr {
427 #[doc = "Peripherals identification code"]
428 #[inline(always)]
429 pub const fn pid(&self) -> u32 {
430 let val = (self.0 >> 0usize) & 0xffff_ffff;
431 val as u32
432 }
433 #[doc = "Peripherals identification code"]
434 #[inline(always)]
435 pub fn set_pid(&mut self, val: u32) {
436 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
437 }
438 }
439 impl Default for Ctr {
440 #[inline(always)]
441 fn default() -> Ctr {
442 Ctr(0)
443 }
444 }
445 #[doc = "Divisor latch high"]
446 #[repr(transparent)]
447 #[derive(Copy, Clone, Eq, PartialEq)]
448 pub struct Dlh(pub u32);
449 impl Dlh {
450 #[doc = "Data"]
451 #[inline(always)]
452 pub const fn dlh(&self) -> u8 {
453 let val = (self.0 >> 0usize) & 0xff;
454 val as u8
455 }
456 #[doc = "Data"]
457 #[inline(always)]
458 pub fn set_dlh(&mut self, val: u8) {
459 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
460 }
461 }
462 impl Default for Dlh {
463 #[inline(always)]
464 fn default() -> Dlh {
465 Dlh(0)
466 }
467 }
468 #[doc = "Divisor latch low"]
469 #[repr(transparent)]
470 #[derive(Copy, Clone, Eq, PartialEq)]
471 pub struct Dll(pub u32);
472 impl Dll {
473 #[doc = "Data"]
474 #[inline(always)]
475 pub const fn dll(&self) -> u8 {
476 let val = (self.0 >> 0usize) & 0xff;
477 val as u8
478 }
479 #[doc = "Data"]
480 #[inline(always)]
481 pub fn set_dll(&mut self, val: u8) {
482 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
483 }
484 }
485 impl Default for Dll {
486 #[inline(always)]
487 fn default() -> Dll {
488 Dll(0)
489 }
490 }
491 #[doc = "DMA software acknowledge"]
492 #[repr(transparent)]
493 #[derive(Copy, Clone, Eq, PartialEq)]
494 pub struct Dmasa(pub u32);
495 impl Dmasa {
496 #[doc = "DMA software acknowledge"]
497 #[inline(always)]
498 pub const fn dmasa(&self) -> bool {
499 let val = (self.0 >> 0usize) & 0x01;
500 val != 0
501 }
502 #[doc = "DMA software acknowledge"]
503 #[inline(always)]
504 pub fn set_dmasa(&mut self, val: bool) {
505 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
506 }
507 }
508 impl Default for Dmasa {
509 #[inline(always)]
510 fn default() -> Dmasa {
511 Dmasa(0)
512 }
513 }
514 #[doc = "FIFO access register"]
515 #[repr(transparent)]
516 #[derive(Copy, Clone, Eq, PartialEq)]
517 pub struct Far(pub u32);
518 impl Far {
519 #[doc = "FIFO access register"]
520 #[inline(always)]
521 pub const fn far(&self) -> bool {
522 let val = (self.0 >> 0usize) & 0x01;
523 val != 0
524 }
525 #[doc = "FIFO access register"]
526 #[inline(always)]
527 pub fn set_far(&mut self, val: bool) {
528 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
529 }
530 }
531 impl Default for Far {
532 #[inline(always)]
533 fn default() -> Far {
534 Far(0)
535 }
536 }
537 #[doc = "FIFO control register"]
538 #[repr(transparent)]
539 #[derive(Copy, Clone, Eq, PartialEq)]
540 pub struct Fcr(pub u32);
541 impl Fcr {
542 #[doc = "FIFO enable"]
543 #[inline(always)]
544 pub const fn fifoe(&self) -> bool {
545 let val = (self.0 >> 0usize) & 0x01;
546 val != 0
547 }
548 #[doc = "FIFO enable"]
549 #[inline(always)]
550 pub fn set_fifoe(&mut self, val: bool) {
551 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
552 }
553 #[doc = "RCVR FIFO reset"]
554 #[inline(always)]
555 pub const fn rfifor(&self) -> bool {
556 let val = (self.0 >> 1usize) & 0x01;
557 val != 0
558 }
559 #[doc = "RCVR FIFO reset"]
560 #[inline(always)]
561 pub fn set_rfifor(&mut self, val: bool) {
562 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
563 }
564 #[doc = "XMIT FIFO reset"]
565 #[inline(always)]
566 pub const fn xfifor(&self) -> bool {
567 let val = (self.0 >> 2usize) & 0x01;
568 val != 0
569 }
570 #[doc = "XMIT FIFO reset"]
571 #[inline(always)]
572 pub fn set_xfifor(&mut self, val: bool) {
573 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
574 }
575 #[doc = "DMA mode"]
576 #[inline(always)]
577 pub const fn dmam(&self) -> bool {
578 let val = (self.0 >> 3usize) & 0x01;
579 val != 0
580 }
581 #[doc = "DMA mode"]
582 #[inline(always)]
583 pub fn set_dmam(&mut self, val: bool) {
584 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
585 }
586 #[doc = "TX Empty Trigger"]
587 #[inline(always)]
588 pub const fn tet(&self) -> u8 {
589 let val = (self.0 >> 4usize) & 0x03;
590 val as u8
591 }
592 #[doc = "TX Empty Trigger"]
593 #[inline(always)]
594 pub fn set_tet(&mut self, val: u8) {
595 self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
596 }
597 #[doc = "RCVR Trigger"]
598 #[inline(always)]
599 pub const fn rt(&self) -> u8 {
600 let val = (self.0 >> 6usize) & 0x03;
601 val as u8
602 }
603 #[doc = "RCVR Trigger"]
604 #[inline(always)]
605 pub fn set_rt(&mut self, val: u8) {
606 self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
607 }
608 }
609 impl Default for Fcr {
610 #[inline(always)]
611 fn default() -> Fcr {
612 Fcr(0)
613 }
614 }
615 #[doc = "Halt TX"]
616 #[repr(transparent)]
617 #[derive(Copy, Clone, Eq, PartialEq)]
618 pub struct Htx(pub u32);
619 impl Htx {
620 #[doc = "Halt TX"]
621 #[inline(always)]
622 pub const fn htx(&self) -> bool {
623 let val = (self.0 >> 0usize) & 0x01;
624 val != 0
625 }
626 #[doc = "Halt TX"]
627 #[inline(always)]
628 pub fn set_htx(&mut self, val: bool) {
629 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
630 }
631 }
632 impl Default for Htx {
633 #[inline(always)]
634 fn default() -> Htx {
635 Htx(0)
636 }
637 }
638 #[doc = "Interrupt enable register"]
639 #[repr(transparent)]
640 #[derive(Copy, Clone, Eq, PartialEq)]
641 pub struct Ier(pub u32);
642 impl Ier {
643 #[doc = "Enable received data available interrupt"]
644 #[inline(always)]
645 pub const fn erbfi(&self) -> bool {
646 let val = (self.0 >> 0usize) & 0x01;
647 val != 0
648 }
649 #[doc = "Enable received data available interrupt"]
650 #[inline(always)]
651 pub fn set_erbfi(&mut self, val: bool) {
652 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
653 }
654 #[doc = "Enable transmitter holding register empty interrupt"]
655 #[inline(always)]
656 pub const fn etbei(&self) -> bool {
657 let val = (self.0 >> 1usize) & 0x01;
658 val != 0
659 }
660 #[doc = "Enable transmitter holding register empty interrupt"]
661 #[inline(always)]
662 pub fn set_etbei(&mut self, val: bool) {
663 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
664 }
665 #[doc = "Enable receiver line status interrupt"]
666 #[inline(always)]
667 pub const fn elsi(&self) -> bool {
668 let val = (self.0 >> 2usize) & 0x01;
669 val != 0
670 }
671 #[doc = "Enable receiver line status interrupt"]
672 #[inline(always)]
673 pub fn set_elsi(&mut self, val: bool) {
674 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
675 }
676 #[doc = "Enable modem status interrupt"]
677 #[inline(always)]
678 pub const fn edssi(&self) -> bool {
679 let val = (self.0 >> 3usize) & 0x01;
680 val != 0
681 }
682 #[doc = "Enable modem status interrupt"]
683 #[inline(always)]
684 pub fn set_edssi(&mut self, val: bool) {
685 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
686 }
687 #[doc = "Programmable THRE Interrupt Mode Enable"]
688 #[inline(always)]
689 pub const fn ptime(&self) -> bool {
690 let val = (self.0 >> 7usize) & 0x01;
691 val != 0
692 }
693 #[doc = "Programmable THRE Interrupt Mode Enable"]
694 #[inline(always)]
695 pub fn set_ptime(&mut self, val: bool) {
696 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
697 }
698 }
699 impl Default for Ier {
700 #[inline(always)]
701 fn default() -> Ier {
702 Ier(0)
703 }
704 }
705 #[doc = "Interrupt Identity register"]
706 #[repr(transparent)]
707 #[derive(Copy, Clone, Eq, PartialEq)]
708 pub struct Iir(pub u32);
709 impl Iir {
710 #[doc = "Interrupt ID"]
711 #[inline(always)]
712 pub const fn iid(&self) -> u8 {
713 let val = (self.0 >> 0usize) & 0x0f;
714 val as u8
715 }
716 #[doc = "Interrupt ID"]
717 #[inline(always)]
718 pub fn set_iid(&mut self, val: u8) {
719 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
720 }
721 #[doc = "FIFOs Enabled"]
722 #[inline(always)]
723 pub const fn fifose(&self) -> u8 {
724 let val = (self.0 >> 6usize) & 0x03;
725 val as u8
726 }
727 #[doc = "FIFOs Enabled"]
728 #[inline(always)]
729 pub fn set_fifose(&mut self, val: u8) {
730 self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
731 }
732 }
733 impl Default for Iir {
734 #[inline(always)]
735 fn default() -> Iir {
736 Iir(0)
737 }
738 }
739 #[doc = "Line control register"]
740 #[repr(transparent)]
741 #[derive(Copy, Clone, Eq, PartialEq)]
742 pub struct Lcr(pub u32);
743 impl Lcr {
744 #[doc = "Data length select, aka. CLS, DLS"]
745 #[inline(always)]
746 pub const fn wls(&self) -> super::vals::DataBits {
747 let val = (self.0 >> 0usize) & 0x03;
748 super::vals::DataBits::from_bits(val as u8)
749 }
750 #[doc = "Data length select, aka. CLS, DLS"]
751 #[inline(always)]
752 pub fn set_wls(&mut self, val: super::vals::DataBits) {
753 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
754 }
755 #[doc = "Number of stop bits"]
756 #[inline(always)]
757 pub const fn stop(&self) -> super::vals::StopBits {
758 let val = (self.0 >> 2usize) & 0x01;
759 super::vals::StopBits::from_bits(val as u8)
760 }
761 #[doc = "Number of stop bits"]
762 #[inline(always)]
763 pub fn set_stop(&mut self, val: super::vals::StopBits) {
764 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize);
765 }
766 #[doc = "Parity enable"]
767 #[inline(always)]
768 pub const fn pen(&self) -> bool {
769 let val = (self.0 >> 3usize) & 0x01;
770 val != 0
771 }
772 #[doc = "Parity enable"]
773 #[inline(always)]
774 pub fn set_pen(&mut self, val: bool) {
775 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
776 }
777 #[doc = "Even parity select"]
778 #[inline(always)]
779 pub const fn eps(&self) -> super::vals::ParitySelect {
780 let val = (self.0 >> 4usize) & 0x01;
781 super::vals::ParitySelect::from_bits(val as u8)
782 }
783 #[doc = "Even parity select"]
784 #[inline(always)]
785 pub fn set_eps(&mut self, val: super::vals::ParitySelect) {
786 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
787 }
788 #[doc = "Stick parity (reserved in 16550, read as 0)"]
789 #[inline(always)]
790 pub const fn sp(&self) -> bool {
791 let val = (self.0 >> 5usize) & 0x01;
792 val != 0
793 }
794 #[doc = "Stick parity (reserved in 16550, read as 0)"]
795 #[inline(always)]
796 pub fn set_sp(&mut self, val: bool) {
797 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
798 }
799 #[doc = "Break control"]
800 #[inline(always)]
801 pub const fn bc(&self) -> bool {
802 let val = (self.0 >> 6usize) & 0x01;
803 val != 0
804 }
805 #[doc = "Break control"]
806 #[inline(always)]
807 pub fn set_bc(&mut self, val: bool) {
808 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
809 }
810 #[doc = "Divisor latch access bit"]
811 #[inline(always)]
812 pub const fn dlab(&self) -> bool {
813 let val = (self.0 >> 7usize) & 0x01;
814 val != 0
815 }
816 #[doc = "Divisor latch access bit"]
817 #[inline(always)]
818 pub fn set_dlab(&mut self, val: bool) {
819 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
820 }
821 }
822 impl Default for Lcr {
823 #[inline(always)]
824 fn default() -> Lcr {
825 Lcr(0)
826 }
827 }
828 #[doc = "Line status register"]
829 #[repr(transparent)]
830 #[derive(Copy, Clone, Eq, PartialEq)]
831 pub struct Lsr(pub u32);
832 impl Lsr {
833 #[doc = "Data ready"]
834 #[inline(always)]
835 pub const fn dr(&self) -> bool {
836 let val = (self.0 >> 0usize) & 0x01;
837 val != 0
838 }
839 #[doc = "Data ready"]
840 #[inline(always)]
841 pub fn set_dr(&mut self, val: bool) {
842 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
843 }
844 #[doc = "Overrun error"]
845 #[inline(always)]
846 pub const fn oe(&self) -> bool {
847 let val = (self.0 >> 1usize) & 0x01;
848 val != 0
849 }
850 #[doc = "Overrun error"]
851 #[inline(always)]
852 pub fn set_oe(&mut self, val: bool) {
853 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
854 }
855 #[doc = "Parity error"]
856 #[inline(always)]
857 pub const fn pe(&self) -> bool {
858 let val = (self.0 >> 2usize) & 0x01;
859 val != 0
860 }
861 #[doc = "Parity error"]
862 #[inline(always)]
863 pub fn set_pe(&mut self, val: bool) {
864 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
865 }
866 #[doc = "Framing error"]
867 #[inline(always)]
868 pub const fn fe(&self) -> bool {
869 let val = (self.0 >> 3usize) & 0x01;
870 val != 0
871 }
872 #[doc = "Framing error"]
873 #[inline(always)]
874 pub fn set_fe(&mut self, val: bool) {
875 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
876 }
877 #[doc = "Break interrupt"]
878 #[inline(always)]
879 pub const fn bi(&self) -> bool {
880 let val = (self.0 >> 4usize) & 0x01;
881 val != 0
882 }
883 #[doc = "Break interrupt"]
884 #[inline(always)]
885 pub fn set_bi(&mut self, val: bool) {
886 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
887 }
888 #[doc = "Transmitter holding register empty"]
889 #[inline(always)]
890 pub const fn thre(&self) -> bool {
891 let val = (self.0 >> 5usize) & 0x01;
892 val != 0
893 }
894 #[doc = "Transmitter holding register empty"]
895 #[inline(always)]
896 pub fn set_thre(&mut self, val: bool) {
897 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
898 }
899 #[doc = "Transmitter empty"]
900 #[inline(always)]
901 pub const fn temt(&self) -> bool {
902 let val = (self.0 >> 6usize) & 0x01;
903 val != 0
904 }
905 #[doc = "Transmitter empty"]
906 #[inline(always)]
907 pub fn set_temt(&mut self, val: bool) {
908 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
909 }
910 #[doc = "Receiver FIFO error"]
911 #[inline(always)]
912 pub const fn rfe(&self) -> bool {
913 let val = (self.0 >> 7usize) & 0x01;
914 val != 0
915 }
916 #[doc = "Receiver FIFO error"]
917 #[inline(always)]
918 pub fn set_rfe(&mut self, val: bool) {
919 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
920 }
921 }
922 impl Default for Lsr {
923 #[inline(always)]
924 fn default() -> Lsr {
925 Lsr(0)
926 }
927 }
928 #[doc = "Modem control register"]
929 #[repr(transparent)]
930 #[derive(Copy, Clone, Eq, PartialEq)]
931 pub struct Mcr(pub u32);
932 impl Mcr {
933 #[doc = "Data terminal ready"]
934 #[inline(always)]
935 pub const fn dtr(&self) -> bool {
936 let val = (self.0 >> 0usize) & 0x01;
937 val != 0
938 }
939 #[doc = "Data terminal ready"]
940 #[inline(always)]
941 pub fn set_dtr(&mut self, val: bool) {
942 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
943 }
944 #[doc = "Request to send"]
945 #[inline(always)]
946 pub const fn rts(&self) -> bool {
947 let val = (self.0 >> 1usize) & 0x01;
948 val != 0
949 }
950 #[doc = "Request to send"]
951 #[inline(always)]
952 pub fn set_rts(&mut self, val: bool) {
953 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
954 }
955 #[doc = "Output 1"]
956 #[inline(always)]
957 pub const fn out1(&self) -> bool {
958 let val = (self.0 >> 2usize) & 0x01;
959 val != 0
960 }
961 #[doc = "Output 1"]
962 #[inline(always)]
963 pub fn set_out1(&mut self, val: bool) {
964 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
965 }
966 #[doc = "Output 2"]
967 #[inline(always)]
968 pub const fn out2(&self) -> bool {
969 let val = (self.0 >> 3usize) & 0x01;
970 val != 0
971 }
972 #[doc = "Output 2"]
973 #[inline(always)]
974 pub fn set_out2(&mut self, val: bool) {
975 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
976 }
977 #[doc = "Loopback mode, aka. LOOP"]
978 #[inline(always)]
979 pub const fn lb(&self) -> bool {
980 let val = (self.0 >> 4usize) & 0x01;
981 val != 0
982 }
983 #[doc = "Loopback mode, aka. LOOP"]
984 #[inline(always)]
985 pub fn set_lb(&mut self, val: bool) {
986 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
987 }
988 #[doc = "Auto flow control enable"]
989 #[inline(always)]
990 pub const fn afce(&self) -> bool {
991 let val = (self.0 >> 5usize) & 0x01;
992 val != 0
993 }
994 #[doc = "Auto flow control enable"]
995 #[inline(always)]
996 pub fn set_afce(&mut self, val: bool) {
997 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
998 }
999 #[doc = "SIR mode enable"]
1000 #[inline(always)]
1001 pub const fn sire(&self) -> bool {
1002 let val = (self.0 >> 6usize) & 0x01;
1003 val != 0
1004 }
1005 #[doc = "SIR mode enable"]
1006 #[inline(always)]
1007 pub fn set_sire(&mut self, val: bool) {
1008 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1009 }
1010 }
1011 impl Default for Mcr {
1012 #[inline(always)]
1013 fn default() -> Mcr {
1014 Mcr(0)
1015 }
1016 }
1017 #[doc = "Modem status register"]
1018 #[repr(transparent)]
1019 #[derive(Copy, Clone, Eq, PartialEq)]
1020 pub struct Msr(pub u32);
1021 impl Msr {
1022 #[doc = "Delta clear to send"]
1023 #[inline(always)]
1024 pub const fn dcts(&self) -> bool {
1025 let val = (self.0 >> 0usize) & 0x01;
1026 val != 0
1027 }
1028 #[doc = "Delta clear to send"]
1029 #[inline(always)]
1030 pub fn set_dcts(&mut self, val: bool) {
1031 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1032 }
1033 #[doc = "Delta data set ready"]
1034 #[inline(always)]
1035 pub const fn ddsr(&self) -> bool {
1036 let val = (self.0 >> 1usize) & 0x01;
1037 val != 0
1038 }
1039 #[doc = "Delta data set ready"]
1040 #[inline(always)]
1041 pub fn set_ddsr(&mut self, val: bool) {
1042 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1043 }
1044 #[doc = "Trailing edge ring indicator"]
1045 #[inline(always)]
1046 pub const fn teri(&self) -> bool {
1047 let val = (self.0 >> 2usize) & 0x01;
1048 val != 0
1049 }
1050 #[doc = "Trailing edge ring indicator"]
1051 #[inline(always)]
1052 pub fn set_teri(&mut self, val: bool) {
1053 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1054 }
1055 #[doc = "Delta data carrier detect"]
1056 #[inline(always)]
1057 pub const fn ddcd(&self) -> bool {
1058 let val = (self.0 >> 3usize) & 0x01;
1059 val != 0
1060 }
1061 #[doc = "Delta data carrier detect"]
1062 #[inline(always)]
1063 pub fn set_ddcd(&mut self, val: bool) {
1064 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1065 }
1066 #[doc = "Clear to send"]
1067 #[inline(always)]
1068 pub const fn cts(&self) -> bool {
1069 let val = (self.0 >> 4usize) & 0x01;
1070 val != 0
1071 }
1072 #[doc = "Clear to send"]
1073 #[inline(always)]
1074 pub fn set_cts(&mut self, val: bool) {
1075 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1076 }
1077 #[doc = "Data set ready"]
1078 #[inline(always)]
1079 pub const fn dsr(&self) -> bool {
1080 let val = (self.0 >> 5usize) & 0x01;
1081 val != 0
1082 }
1083 #[doc = "Data set ready"]
1084 #[inline(always)]
1085 pub fn set_dsr(&mut self, val: bool) {
1086 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1087 }
1088 #[doc = "Ring indicator"]
1089 #[inline(always)]
1090 pub const fn ri(&self) -> bool {
1091 let val = (self.0 >> 6usize) & 0x01;
1092 val != 0
1093 }
1094 #[doc = "Ring indicator"]
1095 #[inline(always)]
1096 pub fn set_ri(&mut self, val: bool) {
1097 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1098 }
1099 #[doc = "Data carrier detect"]
1100 #[inline(always)]
1101 pub const fn dcd(&self) -> bool {
1102 let val = (self.0 >> 7usize) & 0x01;
1103 val != 0
1104 }
1105 #[doc = "Data carrier detect"]
1106 #[inline(always)]
1107 pub fn set_dcd(&mut self, val: bool) {
1108 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1109 }
1110 }
1111 impl Default for Msr {
1112 #[inline(always)]
1113 fn default() -> Msr {
1114 Msr(0)
1115 }
1116 }
1117 #[doc = "Receiver buffer register"]
1118 #[repr(transparent)]
1119 #[derive(Copy, Clone, Eq, PartialEq)]
1120 pub struct Rbr(pub u32);
1121 impl Rbr {
1122 #[doc = "Data"]
1123 #[inline(always)]
1124 pub const fn rbr(&self) -> u8 {
1125 let val = (self.0 >> 0usize) & 0xff;
1126 val as u8
1127 }
1128 #[doc = "Data"]
1129 #[inline(always)]
1130 pub fn set_rbr(&mut self, val: u8) {
1131 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1132 }
1133 }
1134 impl Default for Rbr {
1135 #[inline(always)]
1136 fn default() -> Rbr {
1137 Rbr(0)
1138 }
1139 }
1140 #[doc = "Receive FIFO write"]
1141 #[repr(transparent)]
1142 #[derive(Copy, Clone, Eq, PartialEq)]
1143 pub struct Rfw(pub u32);
1144 impl Rfw {
1145 #[doc = "Receive FIFO Write Data"]
1146 #[inline(always)]
1147 pub const fn rfwd(&self) -> u8 {
1148 let val = (self.0 >> 0usize) & 0xff;
1149 val as u8
1150 }
1151 #[doc = "Receive FIFO Write Data"]
1152 #[inline(always)]
1153 pub fn set_rfwd(&mut self, val: u8) {
1154 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1155 }
1156 #[doc = "Receive FIFO Parity Error"]
1157 #[inline(always)]
1158 pub const fn rfpe(&self) -> bool {
1159 let val = (self.0 >> 8usize) & 0x01;
1160 val != 0
1161 }
1162 #[doc = "Receive FIFO Parity Error"]
1163 #[inline(always)]
1164 pub fn set_rfpe(&mut self, val: bool) {
1165 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1166 }
1167 #[doc = "Receive FIFO Frame Error"]
1168 #[inline(always)]
1169 pub const fn rffe(&self) -> bool {
1170 let val = (self.0 >> 9usize) & 0x01;
1171 val != 0
1172 }
1173 #[doc = "Receive FIFO Frame Error"]
1174 #[inline(always)]
1175 pub fn set_rffe(&mut self, val: bool) {
1176 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1177 }
1178 }
1179 impl Default for Rfw {
1180 #[inline(always)]
1181 fn default() -> Rfw {
1182 Rfw(0)
1183 }
1184 }
1185 #[doc = "Shadow break control register"]
1186 #[repr(transparent)]
1187 #[derive(Copy, Clone, Eq, PartialEq)]
1188 pub struct Sbcr(pub u32);
1189 impl Sbcr {
1190 #[doc = "Shadow break control register"]
1191 #[inline(always)]
1192 pub const fn sbcr(&self) -> bool {
1193 let val = (self.0 >> 0usize) & 0x01;
1194 val != 0
1195 }
1196 #[doc = "Shadow break control register"]
1197 #[inline(always)]
1198 pub fn set_sbcr(&mut self, val: bool) {
1199 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1200 }
1201 }
1202 impl Default for Sbcr {
1203 #[inline(always)]
1204 fn default() -> Sbcr {
1205 Sbcr(0)
1206 }
1207 }
1208 #[doc = "Scratch register"]
1209 #[repr(transparent)]
1210 #[derive(Copy, Clone, Eq, PartialEq)]
1211 pub struct Scr(pub u32);
1212 impl Scr {
1213 #[doc = "Data"]
1214 #[inline(always)]
1215 pub const fn scr(&self) -> u8 {
1216 let val = (self.0 >> 0usize) & 0xff;
1217 val as u8
1218 }
1219 #[doc = "Data"]
1220 #[inline(always)]
1221 pub fn set_scr(&mut self, val: u8) {
1222 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1223 }
1224 }
1225 impl Default for Scr {
1226 #[inline(always)]
1227 fn default() -> Scr {
1228 Scr(0)
1229 }
1230 }
1231 #[doc = "Shadow DMA mode"]
1232 #[repr(transparent)]
1233 #[derive(Copy, Clone, Eq, PartialEq)]
1234 pub struct Sdmam(pub u32);
1235 impl Sdmam {
1236 #[doc = "Shadow DMA mode"]
1237 #[inline(always)]
1238 pub const fn sdmam(&self) -> bool {
1239 let val = (self.0 >> 0usize) & 0x01;
1240 val != 0
1241 }
1242 #[doc = "Shadow DMA mode"]
1243 #[inline(always)]
1244 pub fn set_sdmam(&mut self, val: bool) {
1245 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1246 }
1247 }
1248 impl Default for Sdmam {
1249 #[inline(always)]
1250 fn default() -> Sdmam {
1251 Sdmam(0)
1252 }
1253 }
1254 #[doc = "Shadow FIFO enable"]
1255 #[repr(transparent)]
1256 #[derive(Copy, Clone, Eq, PartialEq)]
1257 pub struct Sfe(pub u32);
1258 impl Sfe {
1259 #[doc = "Shadow FIFO enable"]
1260 #[inline(always)]
1261 pub const fn sfe(&self) -> bool {
1262 let val = (self.0 >> 0usize) & 0x01;
1263 val != 0
1264 }
1265 #[doc = "Shadow FIFO enable"]
1266 #[inline(always)]
1267 pub fn set_sfe(&mut self, val: bool) {
1268 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1269 }
1270 }
1271 impl Default for Sfe {
1272 #[inline(always)]
1273 fn default() -> Sfe {
1274 Sfe(0)
1275 }
1276 }
1277 #[doc = "Shadow receiver buffer register"]
1278 #[repr(transparent)]
1279 #[derive(Copy, Clone, Eq, PartialEq)]
1280 pub struct Srbr(pub u32);
1281 impl Srbr {
1282 #[doc = "Data"]
1283 #[inline(always)]
1284 pub const fn srbr(&self) -> u8 {
1285 let val = (self.0 >> 0usize) & 0xff;
1286 val as u8
1287 }
1288 #[doc = "Data"]
1289 #[inline(always)]
1290 pub fn set_srbr(&mut self, val: u8) {
1291 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1292 }
1293 }
1294 impl Default for Srbr {
1295 #[inline(always)]
1296 fn default() -> Srbr {
1297 Srbr(0)
1298 }
1299 }
1300 #[doc = "Software reset register"]
1301 #[repr(transparent)]
1302 #[derive(Copy, Clone, Eq, PartialEq)]
1303 pub struct Srr(pub u32);
1304 impl Srr {
1305 #[doc = "UART reset"]
1306 #[inline(always)]
1307 pub const fn ur(&self) -> bool {
1308 let val = (self.0 >> 0usize) & 0x01;
1309 val != 0
1310 }
1311 #[doc = "UART reset"]
1312 #[inline(always)]
1313 pub fn set_ur(&mut self, val: bool) {
1314 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1315 }
1316 #[doc = "RCVR FIFO reset"]
1317 #[inline(always)]
1318 pub const fn rfr(&self) -> bool {
1319 let val = (self.0 >> 1usize) & 0x01;
1320 val != 0
1321 }
1322 #[doc = "RCVR FIFO reset"]
1323 #[inline(always)]
1324 pub fn set_rfr(&mut self, val: bool) {
1325 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1326 }
1327 #[doc = "XMIT FIFO reset"]
1328 #[inline(always)]
1329 pub const fn xfr(&self) -> bool {
1330 let val = (self.0 >> 2usize) & 0x01;
1331 val != 0
1332 }
1333 #[doc = "XMIT FIFO reset"]
1334 #[inline(always)]
1335 pub fn set_xfr(&mut self, val: bool) {
1336 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1337 }
1338 }
1339 impl Default for Srr {
1340 #[inline(always)]
1341 fn default() -> Srr {
1342 Srr(0)
1343 }
1344 }
1345 #[doc = "Shadow RCVR trigger"]
1346 #[repr(transparent)]
1347 #[derive(Copy, Clone, Eq, PartialEq)]
1348 pub struct Srt(pub u32);
1349 impl Srt {
1350 #[doc = "Shadow RCVR trigger"]
1351 #[inline(always)]
1352 pub const fn srt(&self) -> u8 {
1353 let val = (self.0 >> 0usize) & 0x03;
1354 val as u8
1355 }
1356 #[doc = "Shadow RCVR trigger"]
1357 #[inline(always)]
1358 pub fn set_srt(&mut self, val: u8) {
1359 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
1360 }
1361 }
1362 impl Default for Srt {
1363 #[inline(always)]
1364 fn default() -> Srt {
1365 Srt(0)
1366 }
1367 }
1368 #[doc = "Shadow request to send"]
1369 #[repr(transparent)]
1370 #[derive(Copy, Clone, Eq, PartialEq)]
1371 pub struct Srts(pub u32);
1372 impl Srts {
1373 #[doc = "Shadow request to send"]
1374 #[inline(always)]
1375 pub const fn srts(&self) -> bool {
1376 let val = (self.0 >> 0usize) & 0x01;
1377 val != 0
1378 }
1379 #[doc = "Shadow request to send"]
1380 #[inline(always)]
1381 pub fn set_srts(&mut self, val: bool) {
1382 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1383 }
1384 }
1385 impl Default for Srts {
1386 #[inline(always)]
1387 fn default() -> Srts {
1388 Srts(0)
1389 }
1390 }
1391 #[doc = "Shadow TX empty trigger"]
1392 #[repr(transparent)]
1393 #[derive(Copy, Clone, Eq, PartialEq)]
1394 pub struct Stet(pub u32);
1395 impl Stet {
1396 #[doc = "Shadow TX empty trigger"]
1397 #[inline(always)]
1398 pub const fn stet(&self) -> u8 {
1399 let val = (self.0 >> 0usize) & 0x03;
1400 val as u8
1401 }
1402 #[doc = "Shadow TX empty trigger"]
1403 #[inline(always)]
1404 pub fn set_stet(&mut self, val: u8) {
1405 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
1406 }
1407 }
1408 impl Default for Stet {
1409 #[inline(always)]
1410 fn default() -> Stet {
1411 Stet(0)
1412 }
1413 }
1414 #[doc = "Shadow transmitter holding register"]
1415 #[repr(transparent)]
1416 #[derive(Copy, Clone, Eq, PartialEq)]
1417 pub struct Sthr(pub u32);
1418 impl Sthr {
1419 #[doc = "Data"]
1420 #[inline(always)]
1421 pub const fn sthr(&self) -> u8 {
1422 let val = (self.0 >> 0usize) & 0xff;
1423 val as u8
1424 }
1425 #[doc = "Data"]
1426 #[inline(always)]
1427 pub fn set_sthr(&mut self, val: u8) {
1428 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1429 }
1430 }
1431 impl Default for Sthr {
1432 #[inline(always)]
1433 fn default() -> Sthr {
1434 Sthr(0)
1435 }
1436 }
1437 #[doc = "Transmit FIFO read"]
1438 #[repr(transparent)]
1439 #[derive(Copy, Clone, Eq, PartialEq)]
1440 pub struct Tfr(pub u32);
1441 impl Tfr {
1442 #[doc = "Data"]
1443 #[inline(always)]
1444 pub const fn tfr(&self) -> u8 {
1445 let val = (self.0 >> 0usize) & 0xff;
1446 val as u8
1447 }
1448 #[doc = "Data"]
1449 #[inline(always)]
1450 pub fn set_tfr(&mut self, val: u8) {
1451 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1452 }
1453 }
1454 impl Default for Tfr {
1455 #[inline(always)]
1456 fn default() -> Tfr {
1457 Tfr(0)
1458 }
1459 }
1460 #[doc = "Transmitter holding register"]
1461 #[repr(transparent)]
1462 #[derive(Copy, Clone, Eq, PartialEq)]
1463 pub struct Thr(pub u32);
1464 impl Thr {
1465 #[doc = "Data"]
1466 #[inline(always)]
1467 pub const fn thr(&self) -> u8 {
1468 let val = (self.0 >> 0usize) & 0xff;
1469 val as u8
1470 }
1471 #[doc = "Data"]
1472 #[inline(always)]
1473 pub fn set_thr(&mut self, val: u8) {
1474 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1475 }
1476 }
1477 impl Default for Thr {
1478 #[inline(always)]
1479 fn default() -> Thr {
1480 Thr(0)
1481 }
1482 }
1483 #[doc = "UART component version"]
1484 #[repr(transparent)]
1485 #[derive(Copy, Clone, Eq, PartialEq)]
1486 pub struct Ucv(pub u32);
1487 impl Ucv {
1488 #[doc = "UART component version"]
1489 #[inline(always)]
1490 pub const fn ucv(&self) -> u32 {
1491 let val = (self.0 >> 0usize) & 0xffff_ffff;
1492 val as u32
1493 }
1494 #[doc = "UART component version"]
1495 #[inline(always)]
1496 pub fn set_ucv(&mut self, val: u32) {
1497 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1498 }
1499 }
1500 impl Default for Ucv {
1501 #[inline(always)]
1502 fn default() -> Ucv {
1503 Ucv(0)
1504 }
1505 }
1506 #[doc = "UART status register"]
1507 #[repr(transparent)]
1508 #[derive(Copy, Clone, Eq, PartialEq)]
1509 pub struct Usr(pub u32);
1510 impl Usr {
1511 #[doc = "Busy"]
1512 #[inline(always)]
1513 pub const fn busy(&self) -> bool {
1514 let val = (self.0 >> 0usize) & 0x01;
1515 val != 0
1516 }
1517 #[doc = "Busy"]
1518 #[inline(always)]
1519 pub fn set_busy(&mut self, val: bool) {
1520 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1521 }
1522 #[doc = "Transmit FIFO Not Full"]
1523 #[inline(always)]
1524 pub const fn tfnf(&self) -> bool {
1525 let val = (self.0 >> 1usize) & 0x01;
1526 val != 0
1527 }
1528 #[doc = "Transmit FIFO Not Full"]
1529 #[inline(always)]
1530 pub fn set_tfnf(&mut self, val: bool) {
1531 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1532 }
1533 #[doc = "Transmit FIFO Empty"]
1534 #[inline(always)]
1535 pub const fn tfe(&self) -> bool {
1536 let val = (self.0 >> 2usize) & 0x01;
1537 val != 0
1538 }
1539 #[doc = "Transmit FIFO Empty"]
1540 #[inline(always)]
1541 pub fn set_tfe(&mut self, val: bool) {
1542 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1543 }
1544 #[doc = "Receive FIFO Not Empty"]
1545 #[inline(always)]
1546 pub const fn rfne(&self) -> bool {
1547 let val = (self.0 >> 3usize) & 0x01;
1548 val != 0
1549 }
1550 #[doc = "Receive FIFO Not Empty"]
1551 #[inline(always)]
1552 pub fn set_rfne(&mut self, val: bool) {
1553 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1554 }
1555 #[doc = "Receive FIFO Full"]
1556 #[inline(always)]
1557 pub const fn rff(&self) -> bool {
1558 let val = (self.0 >> 4usize) & 0x01;
1559 val != 0
1560 }
1561 #[doc = "Receive FIFO Full"]
1562 #[inline(always)]
1563 pub fn set_rff(&mut self, val: bool) {
1564 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1565 }
1566 }
1567 impl Default for Usr {
1568 #[inline(always)]
1569 fn default() -> Usr {
1570 Usr(0)
1571 }
1572 }
1573}
1574pub mod vals {
1575 #[repr(u8)]
1576 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1577 pub enum DataBits {
1578 #[doc = "5 bits"]
1579 BIT5 = 0x0,
1580 #[doc = "6 bits"]
1581 BIT6 = 0x01,
1582 #[doc = "7 bits"]
1583 BIT7 = 0x02,
1584 #[doc = "8 bits"]
1585 BIT8 = 0x03,
1586 }
1587 impl DataBits {
1588 #[inline(always)]
1589 pub const fn from_bits(val: u8) -> DataBits {
1590 unsafe { core::mem::transmute(val & 0x03) }
1591 }
1592 #[inline(always)]
1593 pub const fn to_bits(self) -> u8 {
1594 unsafe { core::mem::transmute(self) }
1595 }
1596 }
1597 impl From<u8> for DataBits {
1598 #[inline(always)]
1599 fn from(val: u8) -> DataBits {
1600 DataBits::from_bits(val)
1601 }
1602 }
1603 impl From<DataBits> for u8 {
1604 #[inline(always)]
1605 fn from(val: DataBits) -> u8 {
1606 DataBits::to_bits(val)
1607 }
1608 }
1609 #[repr(u8)]
1610 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1611 pub enum ParitySelect {
1612 #[doc = "Odd parity (one)"]
1613 ODD = 0x0,
1614 #[doc = "Even parity (zero)"]
1615 EVEN = 0x01,
1616 }
1617 impl ParitySelect {
1618 #[inline(always)]
1619 pub const fn from_bits(val: u8) -> ParitySelect {
1620 unsafe { core::mem::transmute(val & 0x01) }
1621 }
1622 #[inline(always)]
1623 pub const fn to_bits(self) -> u8 {
1624 unsafe { core::mem::transmute(self) }
1625 }
1626 }
1627 impl From<u8> for ParitySelect {
1628 #[inline(always)]
1629 fn from(val: u8) -> ParitySelect {
1630 ParitySelect::from_bits(val)
1631 }
1632 }
1633 impl From<ParitySelect> for u8 {
1634 #[inline(always)]
1635 fn from(val: ParitySelect) -> u8 {
1636 ParitySelect::to_bits(val)
1637 }
1638 }
1639 #[repr(u8)]
1640 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1641 pub enum StopBits {
1642 #[doc = "1 stop bit"]
1643 STOP1 = 0x0,
1644 #[doc = "2 stop bits (1.5 when 5 bits)"]
1645 STOP2 = 0x01,
1646 }
1647 impl StopBits {
1648 #[inline(always)]
1649 pub const fn from_bits(val: u8) -> StopBits {
1650 unsafe { core::mem::transmute(val & 0x01) }
1651 }
1652 #[inline(always)]
1653 pub const fn to_bits(self) -> u8 {
1654 unsafe { core::mem::transmute(self) }
1655 }
1656 }
1657 impl From<u8> for StopBits {
1658 #[inline(always)]
1659 fn from(val: u8) -> StopBits {
1660 StopBits::from_bits(val)
1661 }
1662 }
1663 impl From<StopBits> for u8 {
1664 #[inline(always)]
1665 fn from(val: StopBits) -> u8 {
1666 StopBits::to_bits(val)
1667 }
1668 }
1669}