Crate dsp56300_core

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DSP56300 ISA definitions: architectural constants, register indices, status register bits, instruction decoder, encoder, and parallel ALU types.

Modules§

Accumulator: Accumulator selector (bit d in many encodings).
CondCode: Condition code (4-bit CCCC field).
Instruction: Decoded DSP56300 instruction.
MemSpace
MulShiftOp: Operation type for MulShift (S,#n,D) instructions.
ParallelAlu: Decoded parallel ALU operation (bits 7:0 of a parallel instruction).
ParallelMoveType: Parallel move type (bits 23:20 of a parallel instruction).

CC_NAMES: Condition code names (indexed by 4-bit CCCC field).
PC_MASK
PERIPH_BASE
PERIPH_SIZE
REGISTERS_LMOVE: Long-move register names for L: parallel moves.
REGISTERS_TCC: TCC register pairs: [src, dst] indexed by (opcode>>3) & 0xF.
REGISTER_NAMES: Register names (indexed by register number, matching reg::* constants).
REG_MASKS: Architectural register masks applied when writing registers.

decode_parallel_alu: Decode the parallel ALU byte (bits 7:0) into a structured ParallelAlu.
ggg_reg: GGG register mapping for CMPU: 3-bit field, values 1-3 reserved. Value 0 selects the opposite accumulator from d.
mask_pc: Mask a value to the 24-bit program address space.
mask_reg: Mask a value to the architectural width of register r.
qq_reg: QQ register mapping for standard multiply instructions (mpyi/maci/etc).
qq_reg_mulshift: QQ register mapping for MulShift instructions (mpy/mpyr/mac/macr S,#n,D). Different from the standard qq mapping used by mpyi/maci/etc.
qqq_reg: QQQ register mapping (Table 12-13, S2 column): 3-bit field, values 0-1 reserved. Differs from sss: 2=A0, 3=B0 (vs A1, B1 for sss).
qqqq_regs: QQQQ register pair mapping for DMAC/MpySU/MacSU instructions. 4-bit field per Table 12-16 “Data ALU Multiply Operands Encoding 4”. All 16 values (0x0-0xF) are valid.
sss_reg: SSS register mapping (Table 12-13, S1 column): 3-bit field, values 0-1 reserved.