Struct drv2605::Control3Reg

pub struct Control3Reg(pub u8);

Methods

impl Control3Reg

pub fn ng_thresh(&self) -> u8

This bit is the noise-gate threshold for PWM and analog inputs. 0: Disabled 1: 2% 2: 4% (Default) 3: 8%

pub fn set_ng_thresh(&mut self, value: u8)

This bit is the noise-gate threshold for PWM and analog inputs. 0: Disabled 1: 2% 2: 4% (Default) 3: 8%

pub fn erm_open_loop(&self) -> bool

This bit selects mode of operation while in ERM mode. Closed-loop operation is usually desired for because of automatic overdrive and braking properties. However, many existing waveform libraries were designed for open-loop operation, so open-loop operation may be required for compatibility. 0: Closed Loop 1: Open Loop

pub fn set_erm_open_loop(&mut self, value: bool)

This bit selects mode of operation while in ERM mode. Closed-loop operation is usually desired for because of automatic overdrive and braking properties. However, many existing waveform libraries were designed for open-loop operation, so open-loop operation may be required for compatibility. 0: Closed Loop 1: Open Loop

pub fn supply_comp_dis(&self) -> bool

This bit disables supply compensation. The DRV2605 device generally provides constant drive output over variation in the power supply input (V DD ). In some systems, supply compensation may have already been implemented upstream, so disabling the DRV2605 supply compensation can be useful. 0: Supply compensation enabled 1: Supply compensation disabled

pub fn set_supply_comp_dis(&mut self, value: bool)

This bit disables supply compensation. The DRV2605 device generally provides constant drive output over variation in the power supply input (V DD ). In some systems, supply compensation may have already been implemented upstream, so disabling the DRV2605 supply compensation can be useful. 0: Supply compensation enabled 1: Supply compensation disabled

pub fn data_format_rtp(&self) -> bool

This bit selects the input data interpretation for RTP (Real-Time Playback) mode. 0: Signed 1: Unsigned

pub fn set_data_format_rtp(&mut self, value: bool)

This bit selects the input data interpretation for RTP (Real-Time Playback) mode. 0: Signed 1: Unsigned

pub fn lra_drive_mode(&self) -> bool

This bit selects the drive mode for the LRA algorithm. This bit determines how often the drive amplitude is updated. Updating once per cycle provides a symmetrical output signal, while updating twice per cycle provides more precise control. 0: Once per cycle 1: Twice per cycle

pub fn set_lra_drive_mode(&mut self, value: bool)

This bit selects the drive mode for the LRA algorithm. This bit determines how often the drive amplitude is updated. Updating once per cycle provides a symmetrical output signal, while updating twice per cycle provides more precise control. 0: Once per cycle 1: Twice per cycle

pub fn n_pwm_analog(&self) -> bool

This bit selects the input mode for the IN/TRIG pin when MODE[2:0] = 3. In PWM input mode, the duty cycle of the input signal determines the amplitude of the waveform. In analog input mode, the amplitude of the input determines the amplitude of the waveform. 0: PWM Input 1: Analog Input

pub fn set_n_pwm_analog(&mut self, value: bool)

This bit selects the input mode for the IN/TRIG pin when MODE[2:0] = 3. In PWM input mode, the duty cycle of the input signal determines the amplitude of the waveform. In analog input mode, the amplitude of the input determines the amplitude of the waveform. 0: PWM Input 1: Analog Input

pub fn lra_open_loop(&self) -> bool

This bit selects an open-loop drive option for LRA Mode. When asserted, the playback engine drives the LRA at the selected frequency independently of the resonance frequency. In PWM input mode, the playback engine recovers the LRA commutation frequency from the PWM input, dividing the frequency by

128. Therefore the PWM input frequency must be equal to 128 times the resonant frequency of the LRA. 0: Auto-resonance mode 1: LRA open-loop mode

pub fn set_lra_open_loop(&mut self, value: bool)

This bit selects an open-loop drive option for LRA Mode. When asserted, the playback engine drives the LRA at the selected frequency independently of the resonance frequency. In PWM input mode, the playback engine recovers the LRA commutation frequency from the PWM input, dividing the frequency by

128. Therefore the PWM input frequency must be equal to 128 times the resonant frequency of the LRA. 0: Auto-resonance mode 1: LRA open-loop mode

Trait Implementations

impl<T> BitRange<T> for Control3Reg where     u8: BitRange<T>,

fn bit_range(&self, msb: usize, lsb: usize) -> T

Get a range of bits.

fn set_bit_range(&mut self, msb: usize, lsb: usize, value: T)

Set a range of bits.

impl Debug for Control3Reg

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.