Struct drone_sx1276::sess::Sess

pub struct Sess<C: Conn, M: Mode> {
    pub device: Device<C, M>,
    pub spi: C::Spi,
    pub buffer: Vec<u8>,
}

Semtech SX1276/77/78/79 communication session.

Fields

device: Device<C, M>

A Semtech SX1276/77/78/79 device,

spi: C::Spi

A SPI connection interface.

buffer: Vec<u8>

A byte buffer for I/O operations.

Methods

impl<C: Conn, M: Mode> Sess<C, M>

pub fn recv<R1>(self) -> impl Future<Item = (Self, R1), Error = SendError<C>> where
    R1: RSpiReg<M>, 

Reads a register.

pub fn recv2<R1, R2>(
    self
) -> impl Future<Item = (Self, R1, R2), Error = SendError<C>> where
    R1: RSpiReg<M, Next = R2>,
    R2: RSpiReg<M>, 

Reads 2 registers in burst mode.

pub fn recv3<R1, R2, R3>(
    self
) -> impl Future<Item = (Self, R1, R2, R3), Error = SendError<C>> where
    R1: RSpiReg<M, Next = R2>,
    R2: RSpiReg<M, Next = R3>,
    R3: RSpiReg<M>, 

Reads 3 registers in burst mode.

pub fn recv4<R1, R2, R3, R4>(
    self
) -> impl Future<Item = (Self, R1, R2, R3, R4), Error = SendError<C>> where
    R1: RSpiReg<M, Next = R2>,
    R2: RSpiReg<M, Next = R3>,
    R3: RSpiReg<M, Next = R4>,
    R4: RSpiReg<M>, 

Reads 4 registers in burst mode.

pub fn recv5<R1, R2, R3, R4, R5>(
    self
) -> impl Future<Item = (Self, R1, R2, R3, R4, R5), Error = SendError<C>> where
    R1: RSpiReg<M, Next = R2>,
    R2: RSpiReg<M, Next = R3>,
    R3: RSpiReg<M, Next = R4>,
    R4: RSpiReg<M, Next = R5>,
    R5: RSpiReg<M>, 

Reads 5 registers in burst mode.

pub fn recv6<R1, R2, R3, R4, R5, R6>(
    self
) -> impl Future<Item = (Self, R1, R2, R3, R4, R5, R6), Error = SendError<C>> where
    R1: RSpiReg<M, Next = R2>,
    R2: RSpiReg<M, Next = R3>,
    R3: RSpiReg<M, Next = R4>,
    R4: RSpiReg<M, Next = R5>,
    R5: RSpiReg<M, Next = R6>,
    R6: RSpiReg<M>, 

Reads 6 registers in burst mode.

pub fn recv7<R1, R2, R3, R4, R5, R6, R7>(
    self
) -> impl Future<Item = (Self, R1, R2, R3, R4, R5, R6, R7), Error = SendError<C>> where
    R1: RSpiReg<M, Next = R2>,
    R2: RSpiReg<M, Next = R3>,
    R3: RSpiReg<M, Next = R4>,
    R4: RSpiReg<M, Next = R5>,
    R5: RSpiReg<M, Next = R6>,
    R6: RSpiReg<M, Next = R7>,
    R7: RSpiReg<M>, 

Reads 7 registers in burst mode.

pub fn recv8<R1, R2, R3, R4, R5, R6, R7, R8>(
    self
) -> impl Future<Item = (Self, R1, R2, R3, R4, R5, R6, R7, R8), Error = SendError<C>> where
    R1: RSpiReg<M, Next = R2>,
    R2: RSpiReg<M, Next = R3>,
    R3: RSpiReg<M, Next = R4>,
    R4: RSpiReg<M, Next = R5>,
    R5: RSpiReg<M, Next = R6>,
    R6: RSpiReg<M, Next = R7>,
    R7: RSpiReg<M, Next = R8>,
    R8: RSpiReg<M>, 

Reads 8 registers in burst mode.

impl<C: Conn, M: Mode> Sess<C, M>

pub fn new(device: Device<C, M>, spi: C::Spi, buffer: Vec<u8>) -> Self

Creates a new Sess.

See Sess for the arguments description.

pub fn destroy(self) -> (Device<C, M>, C::Spi, Vec<u8>)

Destructures the Sess.

pub unsafe fn send_raw(
    self,
    address: u8,
    data: &[u8]
) -> impl Future<Item = Self, Error = SendError<C>>

Writes data bytes at the address.

pub unsafe fn recv_raw(
    self,
    address: u8,
    count: usize
) -> impl Future<Item = Self, Error = SendError<C>>

Reads count bytes from the address.

pub fn send_data(
    self,
    data: &[u8]
) -> impl Future<Item = Self, Error = SendError<C>>

Writes bytes to the FIFO.

pub fn recv_data(
    self,
    count: usize
) -> impl Future<Item = Self, Error = SendError<C>>

Reads bytes from the FIFO.

impl<C: Conn> Sess<C, FskOok>

pub unsafe fn into_lora(self) -> Sess<C, Lora>

Converts into LoRa mode.

impl<C: Conn> Sess<C, Lora>

pub unsafe fn into_fsk_ook(self) -> Sess<C, FskOok>

Converts into FSK/OOK mode.

impl<C: Conn> Sess<C, Undefined>

pub unsafe fn into_lora(self) -> Sess<C, Lora>

Converts into LoRa mode.

pub unsafe fn into_fsk_ook(self) -> Sess<C, FskOok>

Converts into FSK/OOK mode.

Trait Implementations

impl<F1, C, M> SessSend1<F1, C, M> for Sess<C, M> where
    C: Conn,
    M: Mode, 

fn send<R1>(
    self,
    f1: F1
) -> Box<Future<Item = Self, Error = SendError<C>> + Send> where
    R1: WSpiReg<M>,
    F1: FnOnce(&mut R1) -> &mut R1, 

Writes a register.

impl<F1, C> SessSend1OpMode<F1, C, Lora> for Sess<C, FskOok> where
    C: Conn, 

type Output = Sess<C, Lora>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send_op_mode(
    self,
    f1: F1
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode, 

Writes to the op mode register.

impl<F1, C> SessSend1OpMode<F1, C, FskOok> for Sess<C, Lora> where
    C: Conn, 

type Output = Sess<C, FskOok>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send_op_mode(
    self,
    f1: F1
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode, 

Writes to the op mode register.

impl<F1, F2, C, M> SessSend2<F1, F2, C, M> for Sess<C, M> where
    C: Conn,
    M: Mode, 

fn send2<R1, R2>(
    self,
    f1: F1,
    f2: F2
) -> Box<Future<Item = Self, Error = SendError<C>> + Send> where
    R1: WSpiReg<M, Next = R2>,
    R2: WSpiReg<M>,
    F1: FnOnce(&mut R1) -> &mut R1,
    F2: FnOnce(&mut R2) -> &mut R2, 

Writes 2 registers in burst mode.

impl<F1, F2, C> SessSend2OpMode<F1, F2, C, Lora> for Sess<C, FskOok> where
    C: Conn, 

type Output = Sess<C, Lora>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send2_op_mode<R2>(
    self,
    f1: F1,
    f2: F2
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<Lora>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2, 

Writes to the op mode and another register in burst mode.

impl<F1, F2, C> SessSend2OpMode<F1, F2, C, FskOok> for Sess<C, Lora> where
    C: Conn, 

type Output = Sess<C, FskOok>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send2_op_mode<R2>(
    self,
    f1: F1,
    f2: F2
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<FskOok>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2, 

Writes to the op mode and another register in burst mode.

impl<F1, F2, F3, C, M> SessSend3<F1, F2, F3, C, M> for Sess<C, M> where
    C: Conn,
    M: Mode, 

fn send3<R1, R2, R3>(
    self,
    f1: F1,
    f2: F2,
    f3: F3
) -> Box<Future<Item = Self, Error = SendError<C>> + Send> where
    R1: WSpiReg<M, Next = R2>,
    R2: WSpiReg<M, Next = R3>,
    R3: WSpiReg<M>,
    F1: FnOnce(&mut R1) -> &mut R1,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3, 

Writes 3 registers in burst mode.

impl<F1, F2, F3, C> SessSend3OpMode<F1, F2, F3, C, Lora> for Sess<C, FskOok> where
    C: Conn, 

type Output = Sess<C, Lora>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send3_op_mode<R2, R3>(
    self,
    f1: F1,
    f2: F2,
    f3: F3
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<Lora, Next = R3>,
    R3: WSpiReg<Lora>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3, 

Writes to the op mode and 2 other registers in burst mode.

impl<F1, F2, F3, C> SessSend3OpMode<F1, F2, F3, C, FskOok> for Sess<C, Lora> where
    C: Conn, 

type Output = Sess<C, FskOok>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send3_op_mode<R2, R3>(
    self,
    f1: F1,
    f2: F2,
    f3: F3
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<FskOok, Next = R3>,
    R3: WSpiReg<FskOok>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3, 

Writes to the op mode and 2 other registers in burst mode.

impl<F1, F2, F3, F4, C, M> SessSend4<F1, F2, F3, F4, C, M> for Sess<C, M> where
    C: Conn,
    M: Mode, 

fn send4<R1, R2, R3, R4>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4
) -> Box<Future<Item = Self, Error = SendError<C>> + Send> where
    R1: WSpiReg<M, Next = R2>,
    R2: WSpiReg<M, Next = R3>,
    R3: WSpiReg<M, Next = R4>,
    R4: WSpiReg<M>,
    F1: FnOnce(&mut R1) -> &mut R1,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4, 

Writes 4 registers in burst mode.

impl<F1, F2, F3, F4, C> SessSend4OpMode<F1, F2, F3, F4, C, Lora> for Sess<C, FskOok> where
    C: Conn, 

type Output = Sess<C, Lora>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send4_op_mode<R2, R3, R4>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<Lora, Next = R3>,
    R3: WSpiReg<Lora, Next = R4>,
    R4: WSpiReg<Lora>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4, 

Writes to the op mode and 3 other registers in burst mode.

impl<F1, F2, F3, F4, C> SessSend4OpMode<F1, F2, F3, F4, C, FskOok> for Sess<C, Lora> where
    C: Conn, 

type Output = Sess<C, FskOok>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send4_op_mode<R2, R3, R4>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<FskOok, Next = R3>,
    R3: WSpiReg<FskOok, Next = R4>,
    R4: WSpiReg<FskOok>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4, 

Writes to the op mode and 3 other registers in burst mode.

impl<F1, F2, F3, F4, F5, C, M> SessSend5<F1, F2, F3, F4, F5, C, M> for Sess<C, M> where
    C: Conn,
    M: Mode, 

fn send5<R1, R2, R3, R4, R5>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5
) -> Box<Future<Item = Self, Error = SendError<C>> + Send> where
    R1: WSpiReg<M, Next = R2>,
    R2: WSpiReg<M, Next = R3>,
    R3: WSpiReg<M, Next = R4>,
    R4: WSpiReg<M, Next = R5>,
    R5: WSpiReg<M>,
    F1: FnOnce(&mut R1) -> &mut R1,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5, 

Writes 5 registers in burst mode.

impl<F1, F2, F3, F4, F5, C> SessSend5OpMode<F1, F2, F3, F4, F5, C, Lora> for Sess<C, FskOok> where
    C: Conn, 

type Output = Sess<C, Lora>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send5_op_mode<R2, R3, R4, R5>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<Lora, Next = R3>,
    R3: WSpiReg<Lora, Next = R4>,
    R4: WSpiReg<Lora, Next = R5>,
    R5: WSpiReg<Lora>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5, 

Writes to the op mode and 4 other registers in burst mode.

impl<F1, F2, F3, F4, F5, C> SessSend5OpMode<F1, F2, F3, F4, F5, C, FskOok> for Sess<C, Lora> where
    C: Conn, 

type Output = Sess<C, FskOok>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send5_op_mode<R2, R3, R4, R5>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<FskOok, Next = R3>,
    R3: WSpiReg<FskOok, Next = R4>,
    R4: WSpiReg<FskOok, Next = R5>,
    R5: WSpiReg<FskOok>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5, 

Writes to the op mode and 4 other registers in burst mode.

impl<F1, F2, F3, F4, F5, F6, C, M> SessSend6<F1, F2, F3, F4, F5, F6, C, M> for Sess<C, M> where
    C: Conn,
    M: Mode, 

fn send6<R1, R2, R3, R4, R5, R6>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5,
    f6: F6
) -> Box<Future<Item = Self, Error = SendError<C>> + Send> where
    R1: WSpiReg<M, Next = R2>,
    R2: WSpiReg<M, Next = R3>,
    R3: WSpiReg<M, Next = R4>,
    R4: WSpiReg<M, Next = R5>,
    R5: WSpiReg<M, Next = R6>,
    R6: WSpiReg<M>,
    F1: FnOnce(&mut R1) -> &mut R1,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5,
    F6: FnOnce(&mut R6) -> &mut R6, 

Writes 6 registers in burst mode.

impl<F1, F2, F3, F4, F5, F6, C> SessSend6OpMode<F1, F2, F3, F4, F5, F6, C, Lora> for Sess<C, FskOok> where
    C: Conn, 

type Output = Sess<C, Lora>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send6_op_mode<R2, R3, R4, R5, R6>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5,
    f6: F6
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<Lora, Next = R3>,
    R3: WSpiReg<Lora, Next = R4>,
    R4: WSpiReg<Lora, Next = R5>,
    R5: WSpiReg<Lora, Next = R6>,
    R6: WSpiReg<Lora>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5,
    F6: FnOnce(&mut R6) -> &mut R6, 

Writes to the op mode and 5 other registers in burst mode.

impl<F1, F2, F3, F4, F5, F6, C> SessSend6OpMode<F1, F2, F3, F4, F5, F6, C, FskOok> for Sess<C, Lora> where
    C: Conn, 

type Output = Sess<C, FskOok>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send6_op_mode<R2, R3, R4, R5, R6>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5,
    f6: F6
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<FskOok, Next = R3>,
    R3: WSpiReg<FskOok, Next = R4>,
    R4: WSpiReg<FskOok, Next = R5>,
    R5: WSpiReg<FskOok, Next = R6>,
    R6: WSpiReg<FskOok>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5,
    F6: FnOnce(&mut R6) -> &mut R6, 

Writes to the op mode and 5 other registers in burst mode.

impl<F1, F2, F3, F4, F5, F6, F7, C, M> SessSend7<F1, F2, F3, F4, F5, F6, F7, C, M> for Sess<C, M> where
    C: Conn,
    M: Mode, 

fn send7<R1, R2, R3, R4, R5, R6, R7>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5,
    f6: F6,
    f7: F7
) -> Box<Future<Item = Self, Error = SendError<C>> + Send> where
    R1: WSpiReg<M, Next = R2>,
    R2: WSpiReg<M, Next = R3>,
    R3: WSpiReg<M, Next = R4>,
    R4: WSpiReg<M, Next = R5>,
    R5: WSpiReg<M, Next = R6>,
    R6: WSpiReg<M, Next = R7>,
    R7: WSpiReg<M>,
    F1: FnOnce(&mut R1) -> &mut R1,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5,
    F6: FnOnce(&mut R6) -> &mut R6,
    F7: FnOnce(&mut R7) -> &mut R7, 

Writes 7 registers in burst mode.

impl<F1, F2, F3, F4, F5, F6, F7, C> SessSend7OpMode<F1, F2, F3, F4, F5, F6, F7, C, Lora> for Sess<C, FskOok> where
    C: Conn, 

type Output = Sess<C, Lora>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send7_op_mode<R2, R3, R4, R5, R6, R7>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5,
    f6: F6,
    f7: F7
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<Lora, Next = R3>,
    R3: WSpiReg<Lora, Next = R4>,
    R4: WSpiReg<Lora, Next = R5>,
    R5: WSpiReg<Lora, Next = R6>,
    R6: WSpiReg<Lora, Next = R7>,
    R7: WSpiReg<Lora>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5,
    F6: FnOnce(&mut R6) -> &mut R6,
    F7: FnOnce(&mut R7) -> &mut R7, 

Writes to the op mode and 6 other registers in burst mode.

impl<F1, F2, F3, F4, F5, F6, F7, C> SessSend7OpMode<F1, F2, F3, F4, F5, F6, F7, C, FskOok> for Sess<C, Lora> where
    C: Conn, 

type Output = Sess<C, FskOok>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send7_op_mode<R2, R3, R4, R5, R6, R7>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5,
    f6: F6,
    f7: F7
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<FskOok, Next = R3>,
    R3: WSpiReg<FskOok, Next = R4>,
    R4: WSpiReg<FskOok, Next = R5>,
    R5: WSpiReg<FskOok, Next = R6>,
    R6: WSpiReg<FskOok, Next = R7>,
    R7: WSpiReg<FskOok>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5,
    F6: FnOnce(&mut R6) -> &mut R6,
    F7: FnOnce(&mut R7) -> &mut R7, 

Writes to the op mode and 6 other registers in burst mode.

impl<F1, F2, F3, F4, F5, F6, F7, F8, C, M> SessSend8<F1, F2, F3, F4, F5, F6, F7, F8, C, M> for Sess<C, M> where
    C: Conn,
    M: Mode, 

fn send8<R1, R2, R3, R4, R5, R6, R7, R8>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5,
    f6: F6,
    f7: F7,
    f8: F8
) -> Box<Future<Item = Self, Error = SendError<C>> + Send> where
    R1: WSpiReg<M, Next = R2>,
    R2: WSpiReg<M, Next = R3>,
    R3: WSpiReg<M, Next = R4>,
    R4: WSpiReg<M, Next = R5>,
    R5: WSpiReg<M, Next = R6>,
    R6: WSpiReg<M, Next = R7>,
    R7: WSpiReg<M, Next = R8>,
    R8: WSpiReg<M>,
    F1: FnOnce(&mut R1) -> &mut R1,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5,
    F6: FnOnce(&mut R6) -> &mut R6,
    F7: FnOnce(&mut R7) -> &mut R7,
    F8: FnOnce(&mut R8) -> &mut R8, 

Writes 8 registers in burst mode.

impl<F1, F2, F3, F4, F5, F6, F7, F8, C> SessSend8OpMode<F1, F2, F3, F4, F5, F6, F7, F8, C, Lora> for Sess<C, FskOok> where
    C: Conn, 

type Output = Sess<C, Lora>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send8_op_mode<R2, R3, R4, R5, R6, R7, R8>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5,
    f6: F6,
    f7: F7,
    f8: F8
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<Lora, Next = R3>,
    R3: WSpiReg<Lora, Next = R4>,
    R4: WSpiReg<Lora, Next = R5>,
    R5: WSpiReg<Lora, Next = R6>,
    R6: WSpiReg<Lora, Next = R7>,
    R7: WSpiReg<Lora, Next = R8>,
    R8: WSpiReg<Lora>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5,
    F6: FnOnce(&mut R6) -> &mut R6,
    F7: FnOnce(&mut R7) -> &mut R7,
    F8: FnOnce(&mut R8) -> &mut R8, 

Writes to the op mode and 7 other registers in burst mode.

impl<F1, F2, F3, F4, F5, F6, F7, F8, C> SessSend8OpMode<F1, F2, F3, F4, F5, F6, F7, F8, C, FskOok> for Sess<C, Lora> where
    C: Conn, 

type Output = Sess<C, FskOok>

Resulting session type.

type OpMode = OpMode

Concrete OpMode register.

fn send8_op_mode<R2, R3, R4, R5, R6, R7, R8>(
    self,
    f1: F1,
    f2: F2,
    f3: F3,
    f4: F4,
    f5: F5,
    f6: F6,
    f7: F7,
    f8: F8
) -> Box<Future<Item = Self::Output, Error = SendError<C>> + Send> where
    R2: WSpiReg<FskOok, Next = R3>,
    R3: WSpiReg<FskOok, Next = R4>,
    R4: WSpiReg<FskOok, Next = R5>,
    R5: WSpiReg<FskOok, Next = R6>,
    R6: WSpiReg<FskOok, Next = R7>,
    R7: WSpiReg<FskOok, Next = R8>,
    R8: WSpiReg<FskOok>,
    F1: FnOnce(&mut Self::OpMode) -> &mut Self::OpMode,
    F2: FnOnce(&mut R2) -> &mut R2,
    F3: FnOnce(&mut R3) -> &mut R3,
    F4: FnOnce(&mut R4) -> &mut R4,
    F5: FnOnce(&mut R5) -> &mut R5,
    F6: FnOnce(&mut R6) -> &mut R6,
    F7: FnOnce(&mut R7) -> &mut R7,
    F8: FnOnce(&mut R8) -> &mut R8, 

Writes to the op mode and 7 other registers in burst mode.