pub fn pixel_clock_khz(mode: &VideoMode) -> u32Expand description
Returns the pixel clock in kHz for a VideoMode.
When mode.pixel_clock_khz is Some (set from a Detailed Timing Descriptor), returns
that exact value directly. When it is None (modes decoded from standard timings,
established timings, or SVD entries that lack a DTD), falls back to a CVT Reduced
Blanking estimate:
- Horizontal blanking: 160 pixels (CVT-RB fixed blank, VESA CVT 1.2 §2.2).
- Vertical blanking: 8 lines (minimum RB frame-height adjustment).
pixel_clock_khz ≈ (width + 160) × (height + 8) × refresh_rate / 1000Returns 0 when neither mode.pixel_clock_khz nor mode.refresh_rate is set.
§Accuracy of the fallback estimate
CVT-RB is the dominant timing standard for modern display modes. For typical consumer resolutions the estimate is within ~2% of the actual clock. HDMI Forum-specified CTA modes (e.g. 4K@60, VIC 97) use larger blanking than CVT-RB predicts and may be under-estimated by ~10–15%, which can produce false accepts in bandwidth ceiling checks. Interlaced modes diverge further.
The fallback is only used when no exact clock is available. Prefer populating
pixel_clock_khz from the EDID Detailed Timing Descriptor wherever possible.