Expand description
A RISC-V disassembler.
Supports RV32, RV64 and RV128 with the I, M, A, F, D, Q and C extensions,
Zicsr, Zifencei, and the bit-manipulation extensions Zba, Zbb, Zbc and
Zbs. The text follows GNU objdump’s for a raw binary
(objdump -D -b binary), so branch targets are written as 0x1008.
use disc_v::{disassemble, Isa};
let code = [0x13, 0x05, 0x10, 0x00, 0x82, 0x80]; // li a0,1; ret
for ins in disassemble(Isa::Rv64, 0x1000, &code) {
println!("{:x}: {ins}", ins.pc());
}Structs§
- Disassembler
- An iterator over the instructions in a byte slice. Create one with
disassemble. - Instruction
- A decoded instruction.
- Operands
- The operands of an instruction, formatted as objdump does:
a0,8(sp).
Enums§
- Isa
- The base integer ISA, which determines the register width and which encodings are valid.
Functions§
- decode
- Decodes the instruction
inst, located at addresspc. - decode_
bytes - Decodes the instruction at the start of
bytes, located at addresspc. - disassemble
- Disassembles
bytes, the first of which is at addresspc. - inst_
length - Returns the length in bytes of the instruction whose first 16-bit parcel
is
parcel, orNonefor the reserved lengths of 10 bytes or more.