Crate disc_v 

A RISC-V disassembler.

Supports RV32, RV64 and RV128 (and RV32E and RV64E, as the E extension) with these extensions:

• M, A, F, D, Q and C
• Zicsr and Zifencei
• Zba, Zbb, Zbc and Zbs
• Zicond
• Zawrs
• Zicbom, Zicboz and Zicbop; Zihintntl and Zihintpause
• Zimop and Zcmop, with the Zicfiss and Zicfilp instructions
• Zcb
• Zfh and Zfhmin
• Zfinx, Zdinx, Zhinx and Zhinxmin, which conflict with F and so are only decoded by a Decoder that enables them
• Zfa
• V (vectors)
• Zvbb and Zvbc; Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed and Zvksh
• H (hypervisor), Svinval, Smrnmi and Ssctr
• Zalasr, Zacas and Zabha
• Zfbfmin, Zvfbfmin and Zvfbfwma (BFloat16)
• Zbkb, Zbkc and Zbkx; Zknd, Zkne, Zknh, Zksed and Zksh (scalar cryptography)
• Zca, Zcf and Zcd (the parts of C); Zcmp and Zcmt, which conflict with Zcd and so are only decoded by a Decoder that enables them
• Zilsd; Zclsd, which conflicts with Zcf and so is only decoded by a Decoder that enables it
• T-Head and CORE-V vendor extensions, which are only decoded by a Decoder that enables them

The vector and vendor extensions need the vector, vendor-thead and vendor-corev Cargo features, which are on by default; without them, their instructions are shown as .insn and the binary is smaller.

The text follows GNU objdump’s for a raw binary (objdump -D -b binary), so branch targets are written as 0x1008.

decode, decode_bytes and disassemble decode every supported extension that does not conflict with another. A Decoder decodes for a particular target instead, such as Decoder::RVA23U64 or one from an ISA string with Decoder::from_march.

use disc_v::{disassemble, Isa};

let code = [0x13, 0x05, 0x10, 0x00, 0x82, 0x80]; // li a0,1; ret
for ins in disassemble(Isa::Rv64, 0x1000, &code) {
    println!("{:x}: {ins}", ins.pc());
}

Structs

Conflict

Two extensions that give different meanings to the same encodings, and so cannot be decoded together.

Decoder

Decodes instructions for a base ISA with a chosen set of extensions.

Disassembler

An iterator over the instructions in a byte slice. Create one with disassemble or Decoder::disassemble.

Extensions

A set of Extensions.

Instruction

A decoded instruction.

Operands

The operands of an instruction, formatted as objdump does: a0,8(sp).

Enums

Extension

A RISC-V extension that defines instructions disc-v can decode.

Isa

The base integer ISA, which determines the register width and which encodings are valid.

MarchError

An error parsing an ISA string with Decoder::from_march.

Functions

decode

Decodes the instruction inst, located at address pc.

decode_bytes

Decodes the instruction at the start of bytes, located at address pc.

disassemble

Disassembles bytes, the first of which is at address pc.

inst_length

Returns the length in bytes of the instruction whose first 16-bit parcel is parcel, or None for the reserved lengths of 10 bytes or more.