disasm_riscv/
consts.rs

1/// Custom instruction flags
2pub mod insn {
3    pub const INSN_AQ: u32 = 1 << 16;
4    pub const INSN_RL: u32 = 1 << 17;
5}
6
7/// Custom register classes
8pub mod reg_class {
9    use crate::RegClass;
10
11    pub const CSR: RegClass = RegClass::arch(0);
12}
13
14/// Custom operands
15pub mod operand {
16    disasm_core::macros::impl_arch_operands! {
17        pub enum RiscvOperand {
18            Fence = 0,
19            RM = 1,
20        }
21    }
22
23    // rm values for fops
24    pub const RM_RNE: u8 = 0;
25    pub const RM_RTZ: u8 = 1;
26    pub const RM_RDN: u8 = 2;
27    pub const RM_RUP: u8 = 3;
28    pub const RM_RMM: u8 = 4;
29    pub const RM_DYN: u8 = 7;
30}