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#![no_std]
use core::{
ptr::NonNull,
sync::atomic::{AtomicBool, Ordering},
};
use cortex_m::{interrupt, itm, peripheral::ITM, register};
#[cfg(armv6m)]
compile_error!("`defmt-itm` cannot be used on Cortex-M0(+) chips, because it requires an ITM peripheral");
static ENABLED: AtomicBool = AtomicBool::new(false);
pub fn enable(itm: ITM) {
unsafe { itm.ter[0].write(1) }
drop(itm);
ENABLED.store(true, Ordering::Relaxed);
}
#[defmt::global_logger]
struct Logger;
impl defmt::Write for Logger {
fn write(&mut self, bytes: &[u8]) {
unsafe { itm::write_all(&mut (*ITM::ptr()).stim[0], bytes) }
}
}
static TAKEN: AtomicBool = AtomicBool::new(false);
static INTERRUPTS_ACTIVE: AtomicBool = AtomicBool::new(false);
unsafe impl defmt::Logger for Logger {
fn acquire() -> Option<NonNull<dyn defmt::Write>> {
if !ENABLED.load(Ordering::Relaxed) {
return None;
}
let primask = register::primask::read();
interrupt::disable();
if !TAKEN.load(Ordering::Relaxed) {
TAKEN.store(true, Ordering::Relaxed);
INTERRUPTS_ACTIVE.store(primask.is_active(), Ordering::Relaxed);
Some(NonNull::from(&Logger as &dyn defmt::Write))
} else {
if primask.is_active() {
unsafe { interrupt::enable() }
}
None
}
}
unsafe fn release(_: NonNull<dyn defmt::Write>) {
TAKEN.store(false, Ordering::Relaxed);
if INTERRUPTS_ACTIVE.load(Ordering::Relaxed) {
interrupt::enable()
}
}
}