dbs_arch/x86_64/cpuid/
cpu_leaf.rs

1// Copyright 2021 Alibaba Cloud. All Rights Reserved.
2// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3// SPDX-License-Identifier: Apache-2.0
4
5#![allow(missing_docs)]
6
7//! CPUID leaf registers constant values.
8
9#![allow(unused)]
10pub mod leaf_0x0 {
11    pub const LEAF_NUM: u32 = 0x0;
12}
13
14pub mod leaf_0x1 {
15    pub const LEAF_NUM: u32 = 0x1;
16
17    pub mod eax {
18        use crate::cpuid::bit_helper::BitRange;
19
20        pub const EXTENDED_FAMILY_ID_BITRANGE: BitRange = bit_range!(27, 20);
21        pub const EXTENDED_PROCESSOR_MODEL_BITRANGE: BitRange = bit_range!(19, 16);
22        pub const PROCESSOR_TYPE_BITRANGE: BitRange = bit_range!(13, 12);
23        pub const PROCESSOR_FAMILY_BITRANGE: BitRange = bit_range!(11, 8);
24        pub const PROCESSOR_MODEL_BITRANGE: BitRange = bit_range!(7, 4);
25        pub const STEPPING_BITRANGE: BitRange = bit_range!(3, 0);
26    }
27
28    pub mod ebx {
29        use crate::cpuid::bit_helper::BitRange;
30
31        // The bit-range containing the (fixed) default APIC ID.
32        pub const APICID_BITRANGE: BitRange = bit_range!(31, 24);
33        // The bit-range containing the logical processor count.
34        pub const CPU_COUNT_BITRANGE: BitRange = bit_range!(23, 16);
35        // The bit-range containing the number of bytes flushed when executing CLFLUSH.
36        pub const CLFLUSH_SIZE_BITRANGE: BitRange = bit_range!(15, 8);
37    }
38
39    pub mod ecx {
40        // DTES64 = 64-bit debug store
41        pub const DTES64_BITINDEX: u32 = 2;
42        // MONITOR = Monitor/MWAIT
43        pub const MONITOR_BITINDEX: u32 = 3;
44        // CPL Qualified Debug Store
45        pub const DS_CPL_SHIFT: u32 = 4;
46        // 5 = VMX (Virtual Machine Extensions)
47        // 6 = SMX (Safer Mode Extensions)
48        // 7 = EIST (Enhanced Intel SpeedStep® technology)
49        // TM2 = Thermal Monitor 2
50        pub const TM2_BITINDEX: u32 = 8;
51        // CNXT_ID = L1 Context ID (L1 data cache can be set to adaptive/shared mode)
52        pub const CNXT_ID_BITINDEX: u32 = 10;
53        // SDBG (cpu supports IA32_DEBUG_INTERFACE MSR for silicon debug)
54        pub const SDBG_BITINDEX: u32 = 11;
55        pub const FMA_BITINDEX: u32 = 12;
56        // XTPR_UPDATE = xTPR Update Control
57        pub const XTPR_UPDATE_BITINDEX: u32 = 14;
58        // PDCM = Perfmon and Debug Capability
59        pub const PDCM_BITINDEX: u32 = 15;
60        // 18 = DCA Direct Cache Access (prefetch data from a memory mapped device)
61        pub const MOVBE_BITINDEX: u32 = 22;
62        pub const TSC_DEADLINE_TIMER_BITINDEX: u32 = 24;
63        pub const OSXSAVE_BITINDEX: u32 = 27;
64        // Cpu is running on a hypervisor.
65        pub const HYPERVISOR_BITINDEX: u32 = 31;
66    }
67
68    pub mod edx {
69        pub const PSN_BITINDEX: u32 = 18; // Processor Serial Number
70        pub const DS_BITINDEX: u32 = 21; // Debug Store.
71        pub const ACPI_BITINDEX: u32 = 22; // Thermal Monitor and Software Controlled Clock Facilities.
72        pub const SS_BITINDEX: u32 = 27; // Self Snoop
73        pub const HTT_BITINDEX: u32 = 28; // Max APIC IDs reserved field is valid
74        pub const TM_BITINDEX: u32 = 29; // Thermal Monitor.
75        pub const PBE_BITINDEX: u32 = 31; // Pending Break Enable.
76    }
77}
78
79pub mod leaf_cache_parameters {
80    pub mod eax {
81        use crate::cpuid::bit_helper::BitRange;
82
83        pub const CACHE_LEVEL_BITRANGE: BitRange = bit_range!(7, 5);
84        pub const MAX_CPUS_PER_CORE_BITRANGE: BitRange = bit_range!(25, 14);
85    }
86}
87
88// Deterministic Cache Parameters Leaf
89pub mod leaf_0x4 {
90    pub const LEAF_NUM: u32 = 0x4;
91
92    pub mod eax {
93        use crate::cpuid::bit_helper::BitRange;
94
95        // inherit eax from leaf_cache_parameters
96        pub use crate::cpuid::cpu_leaf::leaf_cache_parameters::eax::*;
97
98        pub const MAX_CORES_PER_PACKAGE_BITRANGE: BitRange = bit_range!(31, 26);
99    }
100}
101
102// Thermal and Power Management Leaf
103#[allow(dead_code)]
104pub mod leaf_0x6 {
105    pub const LEAF_NUM: u32 = 0x6;
106
107    pub mod eax {
108        pub const TURBO_BOOST_BITINDEX: u32 = 1;
109    }
110
111    pub mod ecx {
112        // "Energy Performance Bias" bit.
113        pub const EPB_BITINDEX: u32 = 3;
114    }
115}
116
117// Structured Extended Feature Flags Enumeration Leaf
118pub mod leaf_0x7 {
119    pub const LEAF_NUM: u32 = 0x7;
120
121    pub mod index0 {
122        pub mod ebx {
123            // 1 = TSC_ADJUST
124            pub const SGX_BITINDEX: u32 = 2;
125            pub const BMI1_BITINDEX: u32 = 3;
126            pub const HLE_BITINDEX: u32 = 4;
127            pub const AVX2_BITINDEX: u32 = 5;
128            // FPU Data Pointer updated only on x87 exceptions if 1.
129            pub const FPDP_BITINDEX: u32 = 6;
130            // 7 = SMEP (Supervisor-Mode Execution Prevention if 1)
131            pub const BMI2_BITINDEX: u32 = 8;
132            // 9 = Enhanced REP MOVSB/STOSB if 1
133            // 10 = INVPCID
134            pub const INVPCID_BITINDEX: u32 = 10;
135            pub const RTM_BITINDEX: u32 = 11;
136            // Intel® Resource Director Technology (Intel® RDT) Monitoring
137            pub const RDT_M_BITINDEX: u32 = 12;
138            // 13 = Deprecates FPU CS and FPU DS values if 1
139            // Memory Protection Extensions
140            pub const MPX_BITINDEX: u32 = 14;
141            // RDT = Intel® Resource Director Technology
142            pub const RDT_A_BITINDEX: u32 = 15;
143            // AVX-512 Foundation instructions
144            pub const AVX512F_BITINDEX: u32 = 16;
145            // AVX-512 Doubleword and Quadword Instructions
146            pub const AVX512DQ_BITINDEX: u32 = 17;
147            pub const RDSEED_BITINDEX: u32 = 18;
148            pub const ADX_BITINDEX: u32 = 19;
149            // 20 = SMAP (Supervisor-Mode Access Prevention)
150            // AVX512IFMA = AVX-512 Integer Fused Multiply-Add Instructions
151            pub const AVX512IFMA_BITINDEX: u32 = 21;
152            // 21 = PCOMMIT intruction
153            // 22 reserved
154            // CLFLUSHOPT (flushing multiple cache lines in parallel within a single logical processor)
155            pub const CLFLUSHOPT_BITINDEX: u32 = 23;
156            // CLWB = Cache Line Write Back
157            pub const CLWB_BITINDEX: u32 = 24;
158            // PT = Intel Processor Trace
159            pub const PT_BITINDEX: u32 = 25;
160            // AVX512PF = AVX512 Prefetch Instructions
161            pub const AVX512PF_BITINDEX: u32 = 26;
162            // AVX512ER = AVX-512 Exponential and Reciprocal Instructions
163            pub const AVX512ER_BITINDEX: u32 = 27;
164            // AVX512CD = AVX-512 Conflict Detection Instructions
165            pub const AVX512CD_BITINDEX: u32 = 28;
166            // Intel Secure Hash Algorithm Extensions
167            pub const SHA_BITINDEX: u32 = 29;
168            // AVX-512 Byte and Word Instructions
169            pub const AVX512BW_BITINDEX: u32 = 30;
170            // AVX-512 Vector Length Extensions
171            pub const AVX512VL_BITINDEX: u32 = 31;
172        }
173
174        pub mod ecx {
175            // 0 = PREFETCHWT1 (move data closer to the processor in anticipation of future use)
176            // AVX512_VBMI = AVX-512 Vector Byte Manipulation Instructions
177            pub const AVX512_VBMI_BITINDEX: u32 = 1;
178            // 2 = UMIP (User Mode Instruction Prevention)
179            // PKU = Protection Keys for user-mode pages
180            pub const PKU_BITINDEX: u32 = 3;
181            // OSPKE = If 1, OS has set CR4.PKE to enable protection keys
182            pub const OSPKE_BITINDEX: u32 = 4;
183            // 5 = WAITPKG
184            // 7-6 reserved
185            // 8 = GFNI
186            // 13-09 reserved
187            // AVX512_VPOPCNTDQ = Vector population count instruction (Intel® Xeon Phi™ only.)
188            pub const AVX512_VPOPCNTDQ_BITINDEX: u32 = 14;
189            // 21 - 17 = The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
190            // Read Processor ID
191            pub const RDPID_BITINDEX: u32 = 22;
192            // 23 - 29 reserved
193            // SGX_LC = SGX Launch Configuration
194            pub const SGX_LC_BITINDEX: u32 = 30;
195            // 31 reserved
196        }
197
198        pub mod edx {
199            // AVX-512 4-register Neural Network Instructions
200            pub const AVX512_4VNNIW_BITINDEX: u32 = 2;
201            // AVX-512 4-register Multiply Accumulation Single precision
202            pub const AVX512_4FMAPS_BITINDEX: u32 = 3;
203            pub const ARCH_CAPABILITIES_BITINDEX: u32 = 29;
204        }
205    }
206}
207
208// Architecture Performance Monitor Features
209pub mod leaf_0xa {
210    pub const LEAF_NUM: u32 = 0xa;
211
212    pub mod eax {
213        use crate::cpuid::bit_helper::BitRange;
214        pub const PMC_VERSION_ID: BitRange = bit_range!(7, 0);
215        pub const BIT_LEN_PMEVENT: BitRange = bit_range!(31, 24);
216    }
217
218    pub mod ebx {
219        pub const CORE_CYCLES_BITINDEX: u32 = 0;
220        pub const INST_RETIRED_BITINDEX: u32 = 1;
221        pub const REF_CYCLES_BITINDEX: u32 = 2;
222        pub const LLC_REF_BITINDEX: u32 = 3;
223        pub const LLC_MISSES_BITINDEX: u32 = 4;
224        pub const BR_INST_RETIRED_BITINDEX: u32 = 5;
225        pub const BR_MIS_RETIRED_BITINDEX: u32 = 6;
226    }
227}
228
229// Extended Topology Leaf
230pub mod leaf_0xb {
231    pub const LEAF_NUM: u32 = 0xb;
232
233    pub const LEVEL_TYPE_THREAD: u32 = 1;
234    pub const LEVEL_TYPE_CORE: u32 = 2;
235
236    pub mod eax {
237        use crate::cpuid::bit_helper::BitRange;
238
239        // The bit-range containing the number of bits to shift right the APIC ID in order to get
240        // the next level APIC ID
241        pub const APICID_BITRANGE: BitRange = bit_range!(4, 0);
242    }
243
244    pub mod ebx {
245        use crate::cpuid::bit_helper::BitRange;
246
247        // The bit-range containing the number of factory-configured logical processors
248        // at the current cache level
249        pub const NUM_LOGICAL_PROCESSORS_BITRANGE: BitRange = bit_range!(15, 0);
250    }
251
252    pub mod ecx {
253        use crate::cpuid::bit_helper::BitRange;
254
255        pub const LEVEL_TYPE_BITRANGE: BitRange = bit_range!(15, 8);
256        pub const LEVEL_NUMBER_BITRANGE: BitRange = bit_range!(7, 0);
257    }
258}
259
260// Processor Extended State Enumeration Sub-leaves
261pub mod leaf_0xd {
262    pub const LEAF_NUM: u32 = 0xd;
263
264    pub mod index0 {
265        pub mod eax {
266            use crate::cpuid::bit_helper::BitRange;
267
268            pub const MPX_STATE_BITRANGE: BitRange = bit_range!(4, 3);
269            pub const AVX512_STATE_BITRANGE: BitRange = bit_range!(7, 5);
270        }
271    }
272
273    pub mod index1 {
274        pub mod eax {
275            pub const XSAVEC_SHIFT: u32 = 1;
276            pub const XGETBV_SHIFT: u32 = 2;
277            pub const XSAVES_SHIFT: u32 = 3;
278        }
279    }
280}
281
282// V2 Extended Topology Enumeration Leaf
283pub mod leaf_0x1f {
284    pub const LEAF_NUM: u32 = 0x1f;
285
286    pub const LEVEL_TYPE_THREAD: u32 = 1;
287    pub const LEVEL_TYPE_CORE: u32 = 2;
288    pub const LEVEL_TYPE_DIE: u32 = 5;
289
290    pub mod eax {
291        use crate::cpuid::bit_helper::BitRange;
292
293        // The bit-range containing the number of bits to shift right the APIC ID in order to get
294        // the next level APIC ID
295        pub const APICID_BITRANGE: BitRange = bit_range!(4, 0);
296    }
297
298    pub mod ebx {
299        use crate::cpuid::bit_helper::BitRange;
300
301        // The bit-range containing the number of factory-configured logical processors
302        // at the current cache level
303        pub const NUM_LOGICAL_PROCESSORS_BITRANGE: BitRange = bit_range!(15, 0);
304    }
305
306    pub mod ecx {
307        use crate::cpuid::bit_helper::BitRange;
308
309        pub const LEVEL_TYPE_BITRANGE: BitRange = bit_range!(15, 8);
310        pub const LEVEL_NUMBER_BITRANGE: BitRange = bit_range!(7, 0);
311    }
312}
313
314pub mod leaf_0x80000000 {
315    pub const LEAF_NUM: u32 = 0x8000_0000;
316
317    pub mod eax {
318        use crate::cpuid::bit_helper::BitRange;
319
320        pub const LARGEST_EXTENDED_FN_BITRANGE: BitRange = bit_range!(31, 0);
321    }
322}
323
324pub mod leaf_0x80000001 {
325    pub const LEAF_NUM: u32 = 0x8000_0001;
326
327    pub mod ecx {
328        pub const TOPOEXT_INDEX: u32 = 22;
329        pub const PREFETCH_BITINDEX: u32 = 8; // 3DNow! PREFETCH/PREFETCHW instructions
330        pub const LZCNT_BITINDEX: u32 = 5; // advanced bit manipulation
331    }
332
333    pub mod edx {
334        pub const PDPE1GB_BITINDEX: u32 = 26; // 1-GByte pages are available if 1.
335    }
336}
337
338pub mod leaf_0x80000008 {
339    pub const LEAF_NUM: u32 = 0x8000_0008;
340
341    pub mod ecx {
342        use crate::cpuid::bit_helper::BitRange;
343
344        // The number of bits in the initial ApicId value that indicate thread ID within a package
345        // Possible values:
346        // 0-3 -> Reserved
347        // 4 -> 1 Die, up to 16 threads
348        // 5 -> 2 Die, up to 32 threads
349        // 6 -> 3,4 Die, up to 64 threads
350        pub const THREAD_ID_SIZE_BITRANGE: BitRange = bit_range!(15, 12);
351        // The number of threads in the package - 1
352        pub const NUM_THREADS_BITRANGE: BitRange = bit_range!(7, 0);
353    }
354}
355
356// Extended Cache Topology Leaf
357pub mod leaf_0x8000001d {
358    pub const LEAF_NUM: u32 = 0x8000_001d;
359
360    // inherit eax from leaf_cache_parameters
361    pub use crate::cpuid::cpu_leaf::leaf_cache_parameters::eax;
362}
363
364// Extended APIC ID Leaf
365pub mod leaf_0x8000001e {
366    pub const LEAF_NUM: u32 = 0x8000_001e;
367
368    pub mod eax {
369        use crate::cpuid::bit_helper::BitRange;
370
371        pub const EXTENDED_APIC_ID_BITRANGE: BitRange = bit_range!(31, 0);
372    }
373
374    pub mod ebx {
375        use crate::cpuid::bit_helper::BitRange;
376
377        // The number of threads per core - 1
378        pub const THREADS_PER_CORE_BITRANGE: BitRange = bit_range!(15, 8);
379        pub const CORE_ID_BITRANGE: BitRange = bit_range!(7, 0);
380    }
381
382    pub mod ecx {
383        use crate::cpuid::bit_helper::BitRange;
384
385        // The number of nodes per processor. Possible values:
386        // 0 -> 1 node per processor
387        // 1 -> 2 nodes per processor
388        // 2 -> Reserved
389        // 3 -> 4 nodes per processor
390        pub const NODES_PER_PROCESSOR_BITRANGE: BitRange = bit_range!(10, 8);
391        pub const NODE_ID_BITRANGE: BitRange = bit_range!(7, 0);
392    }
393}
dbs_arch/x86_64/cpuid/cpu_leaf.rs

dbs_arch/x86_64/cpuid/
cpu_leaf.rs
