da1470x_pac/
memctrl.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:52 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"MEMCTRL registers"]
28unsafe impl ::core::marker::Send for super::Memctrl {}
29unsafe impl ::core::marker::Sync for super::Memctrl {}
30impl super::Memctrl {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "BSR Reset Register"]
38    #[inline(always)]
39    pub const fn busy_reset_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::BusyResetReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::BusyResetReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(120usize),
45            )
46        }
47    }
48
49    #[doc = "BSR2 Reset Register"]
50    #[inline(always)]
51    pub const fn busy_reset_reg2(
52        &self,
53    ) -> &'static crate::common::Reg<self::BusyResetReg2_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::BusyResetReg2_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(124usize),
57            )
58        }
59    }
60
61    #[doc = "BSR Set Register"]
62    #[inline(always)]
63    pub const fn busy_set_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::BusySetReg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::BusySetReg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(112usize),
69            )
70        }
71    }
72
73    #[doc = "BSR2 Set Register"]
74    #[inline(always)]
75    pub const fn busy_set_reg2(
76        &self,
77    ) -> &'static crate::common::Reg<self::BusySetReg2_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::BusySetReg2_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(116usize),
81            )
82        }
83    }
84
85    #[doc = "BSR Status Register"]
86    #[inline(always)]
87    pub const fn busy_stat_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::BusyStatReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::BusyStatReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(128usize),
93            )
94        }
95    }
96
97    #[doc = "BSR2 Status Register"]
98    #[inline(always)]
99    pub const fn busy_stat_reg2(
100        &self,
101    ) -> &'static crate::common::Reg<self::BusyStatReg2_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::BusyStatReg2_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(132usize),
105            )
106        }
107    }
108
109    #[doc = "Memory Arbiter Status Register"]
110    #[inline(always)]
111    pub const fn cmac_status_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::CmacStatusReg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::CmacStatusReg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(48usize),
117            )
118        }
119    }
120
121    #[doc = "CMAC code Base Address Register"]
122    #[inline(always)]
123    pub const fn cmi_code_base_reg(
124        &self,
125    ) -> &'static crate::common::Reg<self::CmiCodeBaseReg_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::CmiCodeBaseReg_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(32usize),
129            )
130        }
131    }
132
133    #[doc = "CMAC data Base Address Register"]
134    #[inline(always)]
135    pub const fn cmi_data_base_reg(
136        &self,
137    ) -> &'static crate::common::Reg<self::CmiDataBaseReg_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::CmiDataBaseReg_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(36usize),
141            )
142        }
143    }
144
145    #[doc = "CMAC end Address Register"]
146    #[inline(always)]
147    pub const fn cmi_end_reg(
148        &self,
149    ) -> &'static crate::common::Reg<self::CmiEndReg_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::CmiEndReg_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(44usize),
153            )
154        }
155    }
156
157    #[doc = "CMAC shared data Base Address Register"]
158    #[inline(always)]
159    pub const fn cmi_shared_base_reg(
160        &self,
161    ) -> &'static crate::common::Reg<self::CmiSharedBaseReg_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::CmiSharedBaseReg_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(40usize),
165            )
166        }
167    }
168
169    #[doc = "Priority Control Register for arbiter 1, 2, 3 and 4"]
170    #[inline(always)]
171    pub const fn mem_prio_arb1_4_reg(
172        &self,
173    ) -> &'static crate::common::Reg<self::MemPrioArb14Reg_SPEC, crate::common::RW> {
174        unsafe {
175            crate::common::Reg::<self::MemPrioArb14Reg_SPEC, crate::common::RW>::from_ptr(
176                self._svd2pac_as_ptr().add(4usize),
177            )
178        }
179    }
180
181    #[doc = "Priority Control Register for arbiter 5, 6, 7 and 8"]
182    #[inline(always)]
183    pub const fn mem_prio_arb5_8_reg(
184        &self,
185    ) -> &'static crate::common::Reg<self::MemPrioArb58Reg_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::MemPrioArb58Reg_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(8usize),
189            )
190        }
191    }
192
193    #[doc = "Maximum Stall cycles Control Register"]
194    #[inline(always)]
195    pub const fn mem_stall_reg(
196        &self,
197    ) -> &'static crate::common::Reg<self::MemStallReg_SPEC, crate::common::RW> {
198        unsafe {
199            crate::common::Reg::<self::MemStallReg_SPEC, crate::common::RW>::from_ptr(
200                self._svd2pac_as_ptr().add(16usize),
201            )
202        }
203    }
204
205    #[doc = "RAM cells Status Register"]
206    #[inline(always)]
207    pub const fn mem_status2_reg(
208        &self,
209    ) -> &'static crate::common::Reg<self::MemStatus2Reg_SPEC, crate::common::RW> {
210        unsafe {
211            crate::common::Reg::<self::MemStatus2Reg_SPEC, crate::common::RW>::from_ptr(
212                self._svd2pac_as_ptr().add(24usize),
213            )
214        }
215    }
216
217    #[doc = "Memory Arbiter Status Register"]
218    #[inline(always)]
219    pub const fn mem_status_reg(
220        &self,
221    ) -> &'static crate::common::Reg<self::MemStatusReg_SPEC, crate::common::RW> {
222        unsafe {
223            crate::common::Reg::<self::MemStatusReg_SPEC, crate::common::RW>::from_ptr(
224                self._svd2pac_as_ptr().add(20usize),
225            )
226        }
227    }
228}
229#[doc(hidden)]
230#[derive(Copy, Clone, Eq, PartialEq)]
231pub struct BusyResetReg_SPEC;
232impl crate::sealed::RegSpec for BusyResetReg_SPEC {
233    type DataType = u32;
234}
235
236#[doc = "BSR Reset Register"]
237pub type BusyResetReg = crate::RegValueT<BusyResetReg_SPEC>;
238
239impl BusyResetReg {
240    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
241    #[inline(always)]
242    pub fn busy_sdadc(
243        self,
244    ) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
245    {
246        crate::common::RegisterField::<30,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
247    }
248
249    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
250    #[inline(always)]
251    pub fn busy_gpadc(
252        self,
253    ) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
254    {
255        crate::common::RegisterField::<28,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
256    }
257
258    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
259    #[inline(always)]
260    pub fn busy_src2(
261        self,
262    ) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
263    {
264        crate::common::RegisterField::<26,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
265    }
266
267    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
268    #[inline(always)]
269    pub fn busy_src(
270        self,
271    ) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
272    {
273        crate::common::RegisterField::<24,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
274    }
275
276    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
277    #[inline(always)]
278    pub fn busy_pdm(
279        self,
280    ) -> crate::common::RegisterField<22, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
281    {
282        crate::common::RegisterField::<22,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
283    }
284
285    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
286    #[inline(always)]
287    pub fn busy_pcm(
288        self,
289    ) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
290    {
291        crate::common::RegisterField::<20,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
292    }
293
294    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
295    #[inline(always)]
296    pub fn busy_i3c(
297        self,
298    ) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
299    {
300        crate::common::RegisterField::<18,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
301    }
302
303    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
304    #[inline(always)]
305    pub fn busy_i2c3(
306        self,
307    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
308    {
309        crate::common::RegisterField::<16,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
310    }
311
312    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
313    #[inline(always)]
314    pub fn busy_i2c2(
315        self,
316    ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
317    {
318        crate::common::RegisterField::<14,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
319    }
320
321    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
322    #[inline(always)]
323    pub fn busy_i2c(
324        self,
325    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
326    {
327        crate::common::RegisterField::<12,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
328    }
329
330    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
331    #[inline(always)]
332    pub fn busy_spi3(
333        self,
334    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
335    {
336        crate::common::RegisterField::<10,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
337    }
338
339    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
340    #[inline(always)]
341    pub fn busy_spi2(
342        self,
343    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
344    {
345        crate::common::RegisterField::<8,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
346    }
347
348    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
349    #[inline(always)]
350    pub fn busy_spi(
351        self,
352    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
353    {
354        crate::common::RegisterField::<6,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
355    }
356
357    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
358    #[inline(always)]
359    pub fn busy_uart3(
360        self,
361    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
362    {
363        crate::common::RegisterField::<4,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
364    }
365
366    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
367    #[inline(always)]
368    pub fn busy_uart2(
369        self,
370    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
371    {
372        crate::common::RegisterField::<2,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
373    }
374
375    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
376    #[inline(always)]
377    pub fn busy_uart(
378        self,
379    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
380    {
381        crate::common::RegisterField::<0,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
382    }
383}
384impl ::core::default::Default for BusyResetReg {
385    #[inline(always)]
386    fn default() -> BusyResetReg {
387        <crate::RegValueT<BusyResetReg_SPEC> as RegisterValue<_>>::new(0)
388    }
389}
390
391#[doc(hidden)]
392#[derive(Copy, Clone, Eq, PartialEq)]
393pub struct BusyResetReg2_SPEC;
394impl crate::sealed::RegSpec for BusyResetReg2_SPEC {
395    type DataType = u32;
396}
397
398#[doc = "BSR2 Reset Register"]
399pub type BusyResetReg2 = crate::RegValueT<BusyResetReg2_SPEC>;
400
401impl BusyResetReg2 {
402    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
403    #[inline(always)]
404    pub fn busy_timer6(
405        self,
406    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, BusyResetReg2_SPEC, crate::common::RW>
407    {
408        crate::common::RegisterField::<10,0x3,1,0,u8,u8,BusyResetReg2_SPEC,crate::common::RW>::from_register(self,0)
409    }
410
411    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
412    #[inline(always)]
413    pub fn busy_timer5(
414        self,
415    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, BusyResetReg2_SPEC, crate::common::RW>
416    {
417        crate::common::RegisterField::<8,0x3,1,0,u8,u8,BusyResetReg2_SPEC,crate::common::RW>::from_register(self,0)
418    }
419
420    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
421    #[inline(always)]
422    pub fn busy_timer4(
423        self,
424    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, BusyResetReg2_SPEC, crate::common::RW>
425    {
426        crate::common::RegisterField::<6,0x3,1,0,u8,u8,BusyResetReg2_SPEC,crate::common::RW>::from_register(self,0)
427    }
428
429    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
430    #[inline(always)]
431    pub fn busy_timer3(
432        self,
433    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, BusyResetReg2_SPEC, crate::common::RW>
434    {
435        crate::common::RegisterField::<4,0x3,1,0,u8,u8,BusyResetReg2_SPEC,crate::common::RW>::from_register(self,0)
436    }
437
438    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
439    #[inline(always)]
440    pub fn busy_timer2(
441        self,
442    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, BusyResetReg2_SPEC, crate::common::RW>
443    {
444        crate::common::RegisterField::<2,0x3,1,0,u8,u8,BusyResetReg2_SPEC,crate::common::RW>::from_register(self,0)
445    }
446
447    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
448    #[inline(always)]
449    pub fn busy_timer(
450        self,
451    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BusyResetReg2_SPEC, crate::common::RW>
452    {
453        crate::common::RegisterField::<0,0x3,1,0,u8,u8,BusyResetReg2_SPEC,crate::common::RW>::from_register(self,0)
454    }
455}
456impl ::core::default::Default for BusyResetReg2 {
457    #[inline(always)]
458    fn default() -> BusyResetReg2 {
459        <crate::RegValueT<BusyResetReg2_SPEC> as RegisterValue<_>>::new(0)
460    }
461}
462
463#[doc(hidden)]
464#[derive(Copy, Clone, Eq, PartialEq)]
465pub struct BusySetReg_SPEC;
466impl crate::sealed::RegSpec for BusySetReg_SPEC {
467    type DataType = u32;
468}
469
470#[doc = "BSR Set Register"]
471pub type BusySetReg = crate::RegValueT<BusySetReg_SPEC>;
472
473impl BusySetReg {
474    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
475    #[inline(always)]
476    pub fn busy_sdadc(
477        self,
478    ) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
479    {
480        crate::common::RegisterField::<30,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
481    }
482
483    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
484    #[inline(always)]
485    pub fn busy_gpadc(
486        self,
487    ) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
488    {
489        crate::common::RegisterField::<28,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
490    }
491
492    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
493    #[inline(always)]
494    pub fn busy_src2(
495        self,
496    ) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
497    {
498        crate::common::RegisterField::<26,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
499    }
500
501    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
502    #[inline(always)]
503    pub fn busy_src(
504        self,
505    ) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
506    {
507        crate::common::RegisterField::<24,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
508    }
509
510    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
511    #[inline(always)]
512    pub fn busy_pdm(
513        self,
514    ) -> crate::common::RegisterField<22, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
515    {
516        crate::common::RegisterField::<22,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
517    }
518
519    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
520    #[inline(always)]
521    pub fn busy_pcm(
522        self,
523    ) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
524    {
525        crate::common::RegisterField::<20,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
526    }
527
528    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
529    #[inline(always)]
530    pub fn busy_i3c(
531        self,
532    ) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
533    {
534        crate::common::RegisterField::<18,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
535    }
536
537    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
538    #[inline(always)]
539    pub fn busy_i2c3(
540        self,
541    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
542    {
543        crate::common::RegisterField::<16,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
544    }
545
546    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
547    #[inline(always)]
548    pub fn busy_i2c2(
549        self,
550    ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
551    {
552        crate::common::RegisterField::<14,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
553    }
554
555    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
556    #[inline(always)]
557    pub fn busy_i2c(
558        self,
559    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
560    {
561        crate::common::RegisterField::<12,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
562    }
563
564    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
565    #[inline(always)]
566    pub fn busy_spi3(
567        self,
568    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W>
569    {
570        crate::common::RegisterField::<10,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
571    }
572
573    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
574    #[inline(always)]
575    pub fn busy_spi2(
576        self,
577    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W> {
578        crate::common::RegisterField::<8,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
579    }
580
581    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
582    #[inline(always)]
583    pub fn busy_spi(
584        self,
585    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W> {
586        crate::common::RegisterField::<6,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
587    }
588
589    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
590    #[inline(always)]
591    pub fn busy_uart3(
592        self,
593    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W> {
594        crate::common::RegisterField::<4,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
595    }
596
597    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
598    #[inline(always)]
599    pub fn busy_uart2(
600        self,
601    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W> {
602        crate::common::RegisterField::<2,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
603    }
604
605    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
606    #[inline(always)]
607    pub fn busy_uart(
608        self,
609    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::W> {
610        crate::common::RegisterField::<0,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::W>::from_register(self,0)
611    }
612}
613impl ::core::default::Default for BusySetReg {
614    #[inline(always)]
615    fn default() -> BusySetReg {
616        <crate::RegValueT<BusySetReg_SPEC> as RegisterValue<_>>::new(0)
617    }
618}
619
620#[doc(hidden)]
621#[derive(Copy, Clone, Eq, PartialEq)]
622pub struct BusySetReg2_SPEC;
623impl crate::sealed::RegSpec for BusySetReg2_SPEC {
624    type DataType = u32;
625}
626
627#[doc = "BSR2 Set Register"]
628pub type BusySetReg2 = crate::RegValueT<BusySetReg2_SPEC>;
629
630impl BusySetReg2 {
631    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
632    #[inline(always)]
633    pub fn busy_timer6(
634        self,
635    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, BusySetReg2_SPEC, crate::common::W>
636    {
637        crate::common::RegisterField::<10,0x3,1,0,u8,u8,BusySetReg2_SPEC,crate::common::W>::from_register(self,0)
638    }
639
640    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
641    #[inline(always)]
642    pub fn busy_timer5(
643        self,
644    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, BusySetReg2_SPEC, crate::common::W>
645    {
646        crate::common::RegisterField::<8,0x3,1,0,u8,u8,BusySetReg2_SPEC,crate::common::W>::from_register(self,0)
647    }
648
649    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
650    #[inline(always)]
651    pub fn busy_timer4(
652        self,
653    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, BusySetReg2_SPEC, crate::common::W>
654    {
655        crate::common::RegisterField::<6,0x3,1,0,u8,u8,BusySetReg2_SPEC,crate::common::W>::from_register(self,0)
656    }
657
658    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
659    #[inline(always)]
660    pub fn busy_timer3(
661        self,
662    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, BusySetReg2_SPEC, crate::common::W>
663    {
664        crate::common::RegisterField::<4,0x3,1,0,u8,u8,BusySetReg2_SPEC,crate::common::W>::from_register(self,0)
665    }
666
667    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
668    #[inline(always)]
669    pub fn busy_timer2(
670        self,
671    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, BusySetReg2_SPEC, crate::common::W>
672    {
673        crate::common::RegisterField::<2,0x3,1,0,u8,u8,BusySetReg2_SPEC,crate::common::W>::from_register(self,0)
674    }
675
676    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
677    #[inline(always)]
678    pub fn busy_timer(
679        self,
680    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BusySetReg2_SPEC, crate::common::W>
681    {
682        crate::common::RegisterField::<0,0x3,1,0,u8,u8,BusySetReg2_SPEC,crate::common::W>::from_register(self,0)
683    }
684}
685impl ::core::default::Default for BusySetReg2 {
686    #[inline(always)]
687    fn default() -> BusySetReg2 {
688        <crate::RegValueT<BusySetReg2_SPEC> as RegisterValue<_>>::new(0)
689    }
690}
691
692#[doc(hidden)]
693#[derive(Copy, Clone, Eq, PartialEq)]
694pub struct BusyStatReg_SPEC;
695impl crate::sealed::RegSpec for BusyStatReg_SPEC {
696    type DataType = u32;
697}
698
699#[doc = "BSR Status Register"]
700pub type BusyStatReg = crate::RegValueT<BusyStatReg_SPEC>;
701
702impl BusyStatReg {
703    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
704    #[inline(always)]
705    pub fn busy_sdadc(
706        self,
707    ) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
708    {
709        crate::common::RegisterField::<30,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
710    }
711
712    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
713    #[inline(always)]
714    pub fn busy_gpadc(
715        self,
716    ) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
717    {
718        crate::common::RegisterField::<28,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
719    }
720
721    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
722    #[inline(always)]
723    pub fn busy_src2(
724        self,
725    ) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
726    {
727        crate::common::RegisterField::<26,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
728    }
729
730    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
731    #[inline(always)]
732    pub fn busy_src(
733        self,
734    ) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
735    {
736        crate::common::RegisterField::<24,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
737    }
738
739    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
740    #[inline(always)]
741    pub fn busy_pdm(
742        self,
743    ) -> crate::common::RegisterField<22, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
744    {
745        crate::common::RegisterField::<22,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
746    }
747
748    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
749    #[inline(always)]
750    pub fn busy_pcm(
751        self,
752    ) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
753    {
754        crate::common::RegisterField::<20,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
755    }
756
757    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
758    #[inline(always)]
759    pub fn busy_i3c(
760        self,
761    ) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
762    {
763        crate::common::RegisterField::<18,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
764    }
765
766    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
767    #[inline(always)]
768    pub fn busy_i2c3(
769        self,
770    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
771    {
772        crate::common::RegisterField::<16,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
773    }
774
775    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
776    #[inline(always)]
777    pub fn busy_i2c2(
778        self,
779    ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
780    {
781        crate::common::RegisterField::<14,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
782    }
783
784    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
785    #[inline(always)]
786    pub fn busy_i2c(
787        self,
788    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
789    {
790        crate::common::RegisterField::<12,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
791    }
792
793    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
794    #[inline(always)]
795    pub fn busy_spi3(
796        self,
797    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
798    {
799        crate::common::RegisterField::<10,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
800    }
801
802    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
803    #[inline(always)]
804    pub fn busy_spi2(
805        self,
806    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
807    {
808        crate::common::RegisterField::<8,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
809    }
810
811    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
812    #[inline(always)]
813    pub fn busy_spi(
814        self,
815    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
816    {
817        crate::common::RegisterField::<6,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
818    }
819
820    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
821    #[inline(always)]
822    pub fn busy_uart3(
823        self,
824    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
825    {
826        crate::common::RegisterField::<4,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
827    }
828
829    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
830    #[inline(always)]
831    pub fn busy_uart2(
832        self,
833    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
834    {
835        crate::common::RegisterField::<2,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
836    }
837
838    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
839    #[inline(always)]
840    pub fn busy_uart(
841        self,
842    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
843    {
844        crate::common::RegisterField::<0,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
845    }
846}
847impl ::core::default::Default for BusyStatReg {
848    #[inline(always)]
849    fn default() -> BusyStatReg {
850        <crate::RegValueT<BusyStatReg_SPEC> as RegisterValue<_>>::new(0)
851    }
852}
853
854#[doc(hidden)]
855#[derive(Copy, Clone, Eq, PartialEq)]
856pub struct BusyStatReg2_SPEC;
857impl crate::sealed::RegSpec for BusyStatReg2_SPEC {
858    type DataType = u32;
859}
860
861#[doc = "BSR2 Status Register"]
862pub type BusyStatReg2 = crate::RegValueT<BusyStatReg2_SPEC>;
863
864impl BusyStatReg2 {
865    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
866    #[inline(always)]
867    pub fn busy_timer6(
868        self,
869    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, BusyStatReg2_SPEC, crate::common::R>
870    {
871        crate::common::RegisterField::<10,0x3,1,0,u8,u8,BusyStatReg2_SPEC,crate::common::R>::from_register(self,0)
872    }
873
874    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
875    #[inline(always)]
876    pub fn busy_timer5(
877        self,
878    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, BusyStatReg2_SPEC, crate::common::R>
879    {
880        crate::common::RegisterField::<8,0x3,1,0,u8,u8,BusyStatReg2_SPEC,crate::common::R>::from_register(self,0)
881    }
882
883    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
884    #[inline(always)]
885    pub fn busy_timer4(
886        self,
887    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, BusyStatReg2_SPEC, crate::common::R>
888    {
889        crate::common::RegisterField::<6,0x3,1,0,u8,u8,BusyStatReg2_SPEC,crate::common::R>::from_register(self,0)
890    }
891
892    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
893    #[inline(always)]
894    pub fn busy_timer3(
895        self,
896    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, BusyStatReg2_SPEC, crate::common::R>
897    {
898        crate::common::RegisterField::<4,0x3,1,0,u8,u8,BusyStatReg2_SPEC,crate::common::R>::from_register(self,0)
899    }
900
901    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
902    #[inline(always)]
903    pub fn busy_timer2(
904        self,
905    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, BusyStatReg2_SPEC, crate::common::R>
906    {
907        crate::common::RegisterField::<2,0x3,1,0,u8,u8,BusyStatReg2_SPEC,crate::common::R>::from_register(self,0)
908    }
909
910    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
911    #[inline(always)]
912    pub fn busy_timer(
913        self,
914    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BusyStatReg2_SPEC, crate::common::R>
915    {
916        crate::common::RegisterField::<0,0x3,1,0,u8,u8,BusyStatReg2_SPEC,crate::common::R>::from_register(self,0)
917    }
918}
919impl ::core::default::Default for BusyStatReg2 {
920    #[inline(always)]
921    fn default() -> BusyStatReg2 {
922        <crate::RegValueT<BusyStatReg2_SPEC> as RegisterValue<_>>::new(0)
923    }
924}
925
926#[doc(hidden)]
927#[derive(Copy, Clone, Eq, PartialEq)]
928pub struct CmacStatusReg_SPEC;
929impl crate::sealed::RegSpec for CmacStatusReg_SPEC {
930    type DataType = u32;
931}
932
933#[doc = "Memory Arbiter Status Register"]
934pub type CmacStatusReg = crate::RegValueT<CmacStatusReg_SPEC>;
935
936impl CmacStatusReg {
937    #[doc = "Writing a \'1\' clears CMI_NOT_READY bit."]
938    #[inline(always)]
939    pub fn cmi_clear_ready(
940        self,
941    ) -> crate::common::RegisterFieldBool<13, 1, 0, CmacStatusReg_SPEC, crate::common::W> {
942        crate::common::RegisterFieldBool::<13,1,0,CmacStatusReg_SPEC,crate::common::W>::from_register(self,0)
943    }
944
945    #[doc = "0: Normal operation\n1: CMI access performed which couldn\'t be handled right away (interface doesn\'t allow wait cycles)"]
946    #[inline(always)]
947    pub fn cmi_not_ready(
948        self,
949    ) -> crate::common::RegisterFieldBool<12, 1, 0, CmacStatusReg_SPEC, crate::common::R> {
950        crate::common::RegisterFieldBool::<12,1,0,CmacStatusReg_SPEC,crate::common::R>::from_register(self,0)
951    }
952
953    #[doc = "The maximum number of arbiter clock cycles that an CPUC AHB access has been buffered."]
954    #[inline(always)]
955    pub fn ahb_rfmon_wr_buff_cnt(
956        self,
957    ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, CmacStatusReg_SPEC, crate::common::R>
958    {
959        crate::common::RegisterField::<8,0xf,1,0,u8,u8,CmacStatusReg_SPEC,crate::common::R>::from_register(self,0)
960    }
961
962    #[doc = "The maximum number of arbiter clock cycles that an CPUS_AHB access has been buffered."]
963    #[inline(always)]
964    pub fn ahb_sys2cmac_wr_buff_cnt(
965        self,
966    ) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, CmacStatusReg_SPEC, crate::common::R>
967    {
968        crate::common::RegisterField::<4,0xf,1,0,u8,u8,CmacStatusReg_SPEC,crate::common::R>::from_register(self,0)
969    }
970
971    #[doc = "Writing a \'1\' clears AHB_CPUC_WR_BUFF_CNT."]
972    #[inline(always)]
973    pub fn ahb_rfmon_clr_wr_buff(
974        self,
975    ) -> crate::common::RegisterFieldBool<3, 1, 0, CmacStatusReg_SPEC, crate::common::W> {
976        crate::common::RegisterFieldBool::<3,1,0,CmacStatusReg_SPEC,crate::common::W>::from_register(self,0)
977    }
978
979    #[doc = "Writing a \'1\' clears AHB_CPUS_WR_BUFF_CNT."]
980    #[inline(always)]
981    pub fn ahb_sys2cmac_clr_wr_buff(
982        self,
983    ) -> crate::common::RegisterFieldBool<2, 1, 0, CmacStatusReg_SPEC, crate::common::W> {
984        crate::common::RegisterFieldBool::<2,1,0,CmacStatusReg_SPEC,crate::common::W>::from_register(self,0)
985    }
986
987    #[doc = "0: No CPUC AHB write access is buffered.\n1: Currently a single CPUC AHB write access is buffered in the arbiter."]
988    #[inline(always)]
989    pub fn ahb_rfmon_write_buff(
990        self,
991    ) -> crate::common::RegisterFieldBool<1, 1, 0, CmacStatusReg_SPEC, crate::common::R> {
992        crate::common::RegisterFieldBool::<1,1,0,CmacStatusReg_SPEC,crate::common::R>::from_register(self,0)
993    }
994
995    #[doc = "0: No CPUS AHB write access is buffered.\n1: Currently a single CPUS AHB write access is buffered in the arbiter."]
996    #[inline(always)]
997    pub fn ahb_sys2cmac_write_buff(
998        self,
999    ) -> crate::common::RegisterFieldBool<0, 1, 0, CmacStatusReg_SPEC, crate::common::R> {
1000        crate::common::RegisterFieldBool::<0,1,0,CmacStatusReg_SPEC,crate::common::R>::from_register(self,0)
1001    }
1002}
1003impl ::core::default::Default for CmacStatusReg {
1004    #[inline(always)]
1005    fn default() -> CmacStatusReg {
1006        <crate::RegValueT<CmacStatusReg_SPEC> as RegisterValue<_>>::new(0)
1007    }
1008}
1009
1010#[doc(hidden)]
1011#[derive(Copy, Clone, Eq, PartialEq)]
1012pub struct CmiCodeBaseReg_SPEC;
1013impl crate::sealed::RegSpec for CmiCodeBaseReg_SPEC {
1014    type DataType = u32;
1015}
1016
1017#[doc = "CMAC code Base Address Register"]
1018pub type CmiCodeBaseReg = crate::RegValueT<CmiCodeBaseReg_SPEC>;
1019
1020impl CmiCodeBaseReg {
1021    #[doc = "Base address for CMAC code with steps of 1 kB.\n0x001: 1 kB base address\n0x010: 16 kB base address\n0x100: 256 kB base address"]
1022    #[inline(always)]
1023    pub fn cmi_code_base_addr(
1024        self,
1025    ) -> crate::common::RegisterField<
1026        10,
1027        0x3ff,
1028        1,
1029        0,
1030        u16,
1031        u16,
1032        CmiCodeBaseReg_SPEC,
1033        crate::common::R,
1034    > {
1035        crate::common::RegisterField::<
1036            10,
1037            0x3ff,
1038            1,
1039            0,
1040            u16,
1041            u16,
1042            CmiCodeBaseReg_SPEC,
1043            crate::common::R,
1044        >::from_register(self, 0)
1045    }
1046}
1047impl ::core::default::Default for CmiCodeBaseReg {
1048    #[inline(always)]
1049    fn default() -> CmiCodeBaseReg {
1050        <crate::RegValueT<CmiCodeBaseReg_SPEC> as RegisterValue<_>>::new(0)
1051    }
1052}
1053
1054#[doc(hidden)]
1055#[derive(Copy, Clone, Eq, PartialEq)]
1056pub struct CmiDataBaseReg_SPEC;
1057impl crate::sealed::RegSpec for CmiDataBaseReg_SPEC {
1058    type DataType = u32;
1059}
1060
1061#[doc = "CMAC data Base Address Register"]
1062pub type CmiDataBaseReg = crate::RegValueT<CmiDataBaseReg_SPEC>;
1063
1064impl CmiDataBaseReg {
1065    #[doc = "Base address for CMAC data with steps of 4 bytes. Note that the CMAC address scheme is used.\n0x00001: 4 byte base address\n0x00010: 64 byte base address\n0x00100: 1 kB base address\n0x01000: 16 kB base address\n0x10000: 256 kB base address"]
1066    #[inline(always)]
1067    pub fn cmi_data_base_addr(
1068        self,
1069    ) -> crate::common::RegisterField<
1070        2,
1071        0x3ffff,
1072        1,
1073        0,
1074        u32,
1075        u32,
1076        CmiDataBaseReg_SPEC,
1077        crate::common::RW,
1078    > {
1079        crate::common::RegisterField::<
1080            2,
1081            0x3ffff,
1082            1,
1083            0,
1084            u32,
1085            u32,
1086            CmiDataBaseReg_SPEC,
1087            crate::common::RW,
1088        >::from_register(self, 0)
1089    }
1090}
1091impl ::core::default::Default for CmiDataBaseReg {
1092    #[inline(always)]
1093    fn default() -> CmiDataBaseReg {
1094        <crate::RegValueT<CmiDataBaseReg_SPEC> as RegisterValue<_>>::new(0)
1095    }
1096}
1097
1098#[doc(hidden)]
1099#[derive(Copy, Clone, Eq, PartialEq)]
1100pub struct CmiEndReg_SPEC;
1101impl crate::sealed::RegSpec for CmiEndReg_SPEC {
1102    type DataType = u32;
1103}
1104
1105#[doc = "CMAC end Address Register"]
1106pub type CmiEndReg = crate::RegValueT<CmiEndReg_SPEC>;
1107
1108impl CmiEndReg {
1109    #[doc = "End address for CMAC code and data accesses with steps of 1 kB. Note that the CMAC address scheme is used.\n0x000: accesses up to 1kB are allowed\n0x001: accesses up to 2kB are allowed\n0x01F: accesses up to 32kB are allowed\n0x1FF: accesses up to 512kB are allowed"]
1110    #[inline(always)]
1111    pub fn cmi_end_addr(
1112        self,
1113    ) -> crate::common::RegisterField<10, 0x3ff, 1, 0, u16, u16, CmiEndReg_SPEC, crate::common::RW>
1114    {
1115        crate::common::RegisterField::<10,0x3ff,1,0,u16,u16,CmiEndReg_SPEC,crate::common::RW>::from_register(self,0)
1116    }
1117}
1118impl ::core::default::Default for CmiEndReg {
1119    #[inline(always)]
1120    fn default() -> CmiEndReg {
1121        <crate::RegValueT<CmiEndReg_SPEC> as RegisterValue<_>>::new(1048575)
1122    }
1123}
1124
1125#[doc(hidden)]
1126#[derive(Copy, Clone, Eq, PartialEq)]
1127pub struct CmiSharedBaseReg_SPEC;
1128impl crate::sealed::RegSpec for CmiSharedBaseReg_SPEC {
1129    type DataType = u32;
1130}
1131
1132#[doc = "CMAC shared data Base Address Register"]
1133pub type CmiSharedBaseReg = crate::RegValueT<CmiSharedBaseReg_SPEC>;
1134
1135impl CmiSharedBaseReg {
1136    #[doc = "Base address for CMAC shared data with steps of 1 kB. Note that the CMAC address scheme is used and should only be used to point to RAM 9 or 10..\n0x001: 1 kB base address\n0x010: 16 kB base address\n0x100: 256 kB base address"]
1137    #[inline(always)]
1138    pub fn cmi_shared_base_addr(
1139        self,
1140    ) -> crate::common::RegisterField<
1141        10,
1142        0x3ff,
1143        1,
1144        0,
1145        u16,
1146        u16,
1147        CmiSharedBaseReg_SPEC,
1148        crate::common::RW,
1149    > {
1150        crate::common::RegisterField::<
1151            10,
1152            0x3ff,
1153            1,
1154            0,
1155            u16,
1156            u16,
1157            CmiSharedBaseReg_SPEC,
1158            crate::common::RW,
1159        >::from_register(self, 0)
1160    }
1161}
1162impl ::core::default::Default for CmiSharedBaseReg {
1163    #[inline(always)]
1164    fn default() -> CmiSharedBaseReg {
1165        <crate::RegValueT<CmiSharedBaseReg_SPEC> as RegisterValue<_>>::new(0)
1166    }
1167}
1168
1169#[doc(hidden)]
1170#[derive(Copy, Clone, Eq, PartialEq)]
1171pub struct MemPrioArb14Reg_SPEC;
1172impl crate::sealed::RegSpec for MemPrioArb14Reg_SPEC {
1173    type DataType = u32;
1174}
1175
1176#[doc = "Priority Control Register for arbiter 1, 2, 3 and 4"]
1177pub type MemPrioArb14Reg = crate::RegValueT<MemPrioArb14Reg_SPEC>;
1178
1179impl MemPrioArb14Reg {
1180    #[doc = "Priority for the DMA AHB interface of arbiter 4\n00: low priority (default)\n01: mid priority\n1x: high priority"]
1181    #[inline(always)]
1182    pub fn arb4_ahb_dma_prio(
1183        self,
1184    ) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1185    {
1186        crate::common::RegisterField::<28,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1187    }
1188
1189    #[doc = "Priority for the CPUS AHB interface of arbiter 4.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1190    #[inline(always)]
1191    pub fn arb4_ahb_cpus_prio(
1192        self,
1193    ) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1194    {
1195        crate::common::RegisterField::<26,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1196    }
1197
1198    #[doc = "Priority for the DMA AHB interface of arbiter 3\n00: low priority (default)\n01: mid priority\n1x: high priority"]
1199    #[inline(always)]
1200    pub fn arb3_ahb_dma_prio(
1201        self,
1202    ) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1203    {
1204        crate::common::RegisterField::<20,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1205    }
1206
1207    #[doc = "Priority for the CPUS AHB interface of arbiter 3.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1208    #[inline(always)]
1209    pub fn arb3_ahb_cpus_prio(
1210        self,
1211    ) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1212    {
1213        crate::common::RegisterField::<18,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1214    }
1215
1216    #[doc = "Priority for the CPUC AHB interface of arbiter 3.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1217    #[inline(always)]
1218    pub fn arb3_ahb_cpuc_prio(
1219        self,
1220    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1221    {
1222        crate::common::RegisterField::<16,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1223    }
1224
1225    #[doc = "Priority for the SNC interface of arbiter 2.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1226    #[inline(always)]
1227    pub fn arb2_snc_prio(
1228        self,
1229    ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1230    {
1231        crate::common::RegisterField::<14,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1232    }
1233
1234    #[doc = "Priority for the DMA AHB interface of arbiter 2.\n00: low priority (default)\n01: mid priority\n1x: high priority"]
1235    #[inline(always)]
1236    pub fn arb2_ahb_dma_prio(
1237        self,
1238    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1239    {
1240        crate::common::RegisterField::<12,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1241    }
1242
1243    #[doc = "Priority for the CPUS AHB interface of arbiter 2.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1244    #[inline(always)]
1245    pub fn arb2_ahb_cpus_prio(
1246        self,
1247    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1248    {
1249        crate::common::RegisterField::<10,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1250    }
1251
1252    #[doc = "Priority for the CPUC AHB interface of arbiter 2.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1253    #[inline(always)]
1254    pub fn arb2_ahb_cpuc_prio(
1255        self,
1256    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1257    {
1258        crate::common::RegisterField::<8,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1259    }
1260
1261    #[doc = "Priority for the SNC interface of arbiter 1.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1262    #[inline(always)]
1263    pub fn arb1_snc_prio(
1264        self,
1265    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1266    {
1267        crate::common::RegisterField::<6,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1268    }
1269
1270    #[doc = "Priority for the DMA AHB interface of arbiter 1.\n00: low priority (default)\n01: mid priority\n1x: high priority"]
1271    #[inline(always)]
1272    pub fn arb1_ahb_dma_prio(
1273        self,
1274    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1275    {
1276        crate::common::RegisterField::<4,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1277    }
1278
1279    #[doc = "Priority for the CPUS AHB interface of arbiter 1.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1280    #[inline(always)]
1281    pub fn arb1_ahb_cpus_prio(
1282        self,
1283    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1284    {
1285        crate::common::RegisterField::<2,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1286    }
1287
1288    #[doc = "Priority for the CPUC AHB interface of arbiter 1.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1289    #[inline(always)]
1290    pub fn arb1_ahb_cpuc_prio(
1291        self,
1292    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, MemPrioArb14Reg_SPEC, crate::common::RW>
1293    {
1294        crate::common::RegisterField::<0,0x3,1,0,u8,u8,MemPrioArb14Reg_SPEC,crate::common::RW>::from_register(self,0)
1295    }
1296}
1297impl ::core::default::Default for MemPrioArb14Reg {
1298    #[inline(always)]
1299    fn default() -> MemPrioArb14Reg {
1300        <crate::RegValueT<MemPrioArb14Reg_SPEC> as RegisterValue<_>>::new(0)
1301    }
1302}
1303
1304#[doc(hidden)]
1305#[derive(Copy, Clone, Eq, PartialEq)]
1306pub struct MemPrioArb58Reg_SPEC;
1307impl crate::sealed::RegSpec for MemPrioArb58Reg_SPEC {
1308    type DataType = u32;
1309}
1310
1311#[doc = "Priority Control Register for arbiter 5, 6, 7 and 8"]
1312pub type MemPrioArb58Reg = crate::RegValueT<MemPrioArb58Reg_SPEC>;
1313
1314impl MemPrioArb58Reg {
1315    #[doc = "Priority for the SNC interface of arbiter 8.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1316    #[inline(always)]
1317    pub fn arb8_snc_prio(
1318        self,
1319    ) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, MemPrioArb58Reg_SPEC, crate::common::RW>
1320    {
1321        crate::common::RegisterField::<30,0x3,1,0,u8,u8,MemPrioArb58Reg_SPEC,crate::common::RW>::from_register(self,0)
1322    }
1323
1324    #[doc = "Priority for the DMA AHB interface of arbiter 8.\n00: low priority (default)\n01: mid priority\n1x: high priority"]
1325    #[inline(always)]
1326    pub fn arb8_ahb_dma_prio(
1327        self,
1328    ) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, MemPrioArb58Reg_SPEC, crate::common::RW>
1329    {
1330        crate::common::RegisterField::<28,0x3,1,0,u8,u8,MemPrioArb58Reg_SPEC,crate::common::RW>::from_register(self,0)
1331    }
1332
1333    #[doc = "Priority for the CPUS AHB interface of arbiter 8.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1334    #[inline(always)]
1335    pub fn arb8_ahb_cpus_prio(
1336        self,
1337    ) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, MemPrioArb58Reg_SPEC, crate::common::RW>
1338    {
1339        crate::common::RegisterField::<26,0x3,1,0,u8,u8,MemPrioArb58Reg_SPEC,crate::common::RW>::from_register(self,0)
1340    }
1341
1342    #[doc = "Priority for the DMA AHB interface of arbiter 7.\n00: low priority (default)\n01: mid priority\n1x: high priority"]
1343    #[inline(always)]
1344    pub fn arb7_ahb_dma_prio(
1345        self,
1346    ) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, MemPrioArb58Reg_SPEC, crate::common::RW>
1347    {
1348        crate::common::RegisterField::<20,0x3,1,0,u8,u8,MemPrioArb58Reg_SPEC,crate::common::RW>::from_register(self,0)
1349    }
1350
1351    #[doc = "Priority for the CPUS AHB interface of arbiter 7.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1352    #[inline(always)]
1353    pub fn arb7_ahb_cpus_prio(
1354        self,
1355    ) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, MemPrioArb58Reg_SPEC, crate::common::RW>
1356    {
1357        crate::common::RegisterField::<18,0x3,1,0,u8,u8,MemPrioArb58Reg_SPEC,crate::common::RW>::from_register(self,0)
1358    }
1359
1360    #[doc = "Priority for the DMA AHB interface of arbiter 6.\n00: low priority (default)\n01: mid priority\n1x: high priority"]
1361    #[inline(always)]
1362    pub fn arb6_ahb_dma_prio(
1363        self,
1364    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, MemPrioArb58Reg_SPEC, crate::common::RW>
1365    {
1366        crate::common::RegisterField::<12,0x3,1,0,u8,u8,MemPrioArb58Reg_SPEC,crate::common::RW>::from_register(self,0)
1367    }
1368
1369    #[doc = "Priority for the CPUS AHB interface of arbiter 6.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1370    #[inline(always)]
1371    pub fn arb6_ahb_cpus_prio(
1372        self,
1373    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, MemPrioArb58Reg_SPEC, crate::common::RW>
1374    {
1375        crate::common::RegisterField::<10,0x3,1,0,u8,u8,MemPrioArb58Reg_SPEC,crate::common::RW>::from_register(self,0)
1376    }
1377
1378    #[doc = "Priority for the DMA AHB interface of arbiter 5.\n00: low priority (default)\n01: mid priority\n1x: high priority"]
1379    #[inline(always)]
1380    pub fn arb5_ahb_dma_prio(
1381        self,
1382    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, MemPrioArb58Reg_SPEC, crate::common::RW>
1383    {
1384        crate::common::RegisterField::<4,0x3,1,0,u8,u8,MemPrioArb58Reg_SPEC,crate::common::RW>::from_register(self,0)
1385    }
1386
1387    #[doc = "Priority for the CPUS AHB interface of arbiter 5.\n00: low priority (default)\n01: mid priority\n10: high priority\n11: top priority"]
1388    #[inline(always)]
1389    pub fn arb5_ahb_cpus_prio(
1390        self,
1391    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, MemPrioArb58Reg_SPEC, crate::common::RW>
1392    {
1393        crate::common::RegisterField::<2,0x3,1,0,u8,u8,MemPrioArb58Reg_SPEC,crate::common::RW>::from_register(self,0)
1394    }
1395}
1396impl ::core::default::Default for MemPrioArb58Reg {
1397    #[inline(always)]
1398    fn default() -> MemPrioArb58Reg {
1399        <crate::RegValueT<MemPrioArb58Reg_SPEC> as RegisterValue<_>>::new(0)
1400    }
1401}
1402
1403#[doc(hidden)]
1404#[derive(Copy, Clone, Eq, PartialEq)]
1405pub struct MemStallReg_SPEC;
1406impl crate::sealed::RegSpec for MemStallReg_SPEC {
1407    type DataType = u32;
1408}
1409
1410#[doc = "Maximum Stall cycles Control Register"]
1411pub type MemStallReg = crate::RegValueT<MemStallReg_SPEC>;
1412
1413impl MemStallReg {
1414    #[doc = "Maximum allowed number of stall cycles for the SNC interface. If exceeded, the interface will get high priority. Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles.\n0: don\'t use, not feasible and can block other interfaces\n1: max 1 stall cycle\n15: max 15 stall cycles"]
1415    #[inline(always)]
1416    pub fn snc_max_stall(
1417        self,
1418    ) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, MemStallReg_SPEC, crate::common::RW>
1419    {
1420        crate::common::RegisterField::<12,0xf,1,0,u8,u8,MemStallReg_SPEC,crate::common::RW>::from_register(self,0)
1421    }
1422
1423    #[doc = "Maximum allowed number of stall cycles for the DMA AHB interface. If exceeded, the interface will get high priority. Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles.\n0: don\'t use, not feasible and can block other interfaces\n1: max 1 stall cycle\n15: max 15 stall cycles"]
1424    #[inline(always)]
1425    pub fn ahb_dma_max_stall(
1426        self,
1427    ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, MemStallReg_SPEC, crate::common::RW>
1428    {
1429        crate::common::RegisterField::<8,0xf,1,0,u8,u8,MemStallReg_SPEC,crate::common::RW>::from_register(self,0)
1430    }
1431
1432    #[doc = "Maximum allowed number of stall cycles for the CPUS AHB interface. If exceeded, the interface will get high priority. Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles.\n0: don\'t use, not feasible and can block other interfaces\n1: max 1 stall cycle\n15: max 15 stall cycles"]
1433    #[inline(always)]
1434    pub fn ahb_cpus_max_stall(
1435        self,
1436    ) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, MemStallReg_SPEC, crate::common::RW>
1437    {
1438        crate::common::RegisterField::<4,0xf,1,0,u8,u8,MemStallReg_SPEC,crate::common::RW>::from_register(self,0)
1439    }
1440
1441    #[doc = "Maximum allowed number of stall cycles for the CPUC AHB interface. If exceeded, the interface will get high priority. Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles.\n0: don\'t use, not feasible and can block other interfaces\n1: max 1 stall cycle\n15: max 15 stall cycles"]
1442    #[inline(always)]
1443    pub fn ahb_cpuc_max_stall(
1444        self,
1445    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, MemStallReg_SPEC, crate::common::RW>
1446    {
1447        crate::common::RegisterField::<0,0xf,1,0,u8,u8,MemStallReg_SPEC,crate::common::RW>::from_register(self,0)
1448    }
1449}
1450impl ::core::default::Default for MemStallReg {
1451    #[inline(always)]
1452    fn default() -> MemStallReg {
1453        <crate::RegValueT<MemStallReg_SPEC> as RegisterValue<_>>::new(65535)
1454    }
1455}
1456
1457#[doc(hidden)]
1458#[derive(Copy, Clone, Eq, PartialEq)]
1459pub struct MemStatus2Reg_SPEC;
1460impl crate::sealed::RegSpec for MemStatus2Reg_SPEC {
1461    type DataType = u32;
1462}
1463
1464#[doc = "RAM cells Status Register"]
1465pub type MemStatus2Reg = crate::RegValueT<MemStatus2Reg_SPEC>;
1466
1467impl MemStatus2Reg {
1468    #[doc = "Reading a \'1\' indicates RAM13 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1469    #[inline(always)]
1470    pub fn ram13_off_but_access(
1471        self,
1472    ) -> crate::common::RegisterFieldBool<13, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1473        crate::common::RegisterFieldBool::<13,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1474    }
1475
1476    #[doc = "Reading a \'1\' indicates RAM12 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1477    #[inline(always)]
1478    pub fn ram12_off_but_access(
1479        self,
1480    ) -> crate::common::RegisterFieldBool<12, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1481        crate::common::RegisterFieldBool::<12,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1482    }
1483
1484    #[doc = "Reading a \'1\' indicates RAM11 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1485    #[inline(always)]
1486    pub fn ram11_off_but_access(
1487        self,
1488    ) -> crate::common::RegisterFieldBool<11, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1489        crate::common::RegisterFieldBool::<11,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1490    }
1491
1492    #[doc = "Reading a \'1\' indicates RAM10 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1493    #[inline(always)]
1494    pub fn ram10_off_but_access(
1495        self,
1496    ) -> crate::common::RegisterFieldBool<10, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1497        crate::common::RegisterFieldBool::<10,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1498    }
1499
1500    #[doc = "Reading a \'1\' indicates RAM9 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1501    #[inline(always)]
1502    pub fn ram9_off_but_access(
1503        self,
1504    ) -> crate::common::RegisterFieldBool<9, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1505        crate::common::RegisterFieldBool::<9,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1506    }
1507
1508    #[doc = "Reading a \'1\' indicates RAM8 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1509    #[inline(always)]
1510    pub fn ram8_off_but_access(
1511        self,
1512    ) -> crate::common::RegisterFieldBool<8, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1513        crate::common::RegisterFieldBool::<8,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1514    }
1515
1516    #[doc = "Reading a \'1\' indicates RAM7 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1517    #[inline(always)]
1518    pub fn ram7_off_but_access(
1519        self,
1520    ) -> crate::common::RegisterFieldBool<7, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1521        crate::common::RegisterFieldBool::<7,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1522    }
1523
1524    #[doc = "Reading a \'1\' indicates RAM6 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1525    #[inline(always)]
1526    pub fn ram6_off_but_access(
1527        self,
1528    ) -> crate::common::RegisterFieldBool<6, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1529        crate::common::RegisterFieldBool::<6,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1530    }
1531
1532    #[doc = "Reading a \'1\' indicates RAM5 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1533    #[inline(always)]
1534    pub fn ram5_off_but_access(
1535        self,
1536    ) -> crate::common::RegisterFieldBool<5, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1537        crate::common::RegisterFieldBool::<5,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1538    }
1539
1540    #[doc = "Reading a \'1\' indicates RAM4 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1541    #[inline(always)]
1542    pub fn ram4_off_but_access(
1543        self,
1544    ) -> crate::common::RegisterFieldBool<4, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1545        crate::common::RegisterFieldBool::<4,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1546    }
1547
1548    #[doc = "Reading a \'1\' indicates RAM3 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1549    #[inline(always)]
1550    pub fn ram3_off_but_access(
1551        self,
1552    ) -> crate::common::RegisterFieldBool<3, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1553        crate::common::RegisterFieldBool::<3,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1554    }
1555
1556    #[doc = "Reading a \'1\' indicates RAM2 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1557    #[inline(always)]
1558    pub fn ram2_off_but_access(
1559        self,
1560    ) -> crate::common::RegisterFieldBool<2, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1561        crate::common::RegisterFieldBool::<2,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1562    }
1563
1564    #[doc = "Reading a \'1\' indicates RAM1 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1565    #[inline(always)]
1566    pub fn ram1_off_but_access(
1567        self,
1568    ) -> crate::common::RegisterFieldBool<1, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1569        crate::common::RegisterFieldBool::<1,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1570    }
1571
1572    #[doc = "Reading a \'1\' indicates RAM0 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
1573    #[inline(always)]
1574    pub fn ram0_off_but_access(
1575        self,
1576    ) -> crate::common::RegisterFieldBool<0, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
1577        crate::common::RegisterFieldBool::<0,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
1578    }
1579}
1580impl ::core::default::Default for MemStatus2Reg {
1581    #[inline(always)]
1582    fn default() -> MemStatus2Reg {
1583        <crate::RegValueT<MemStatus2Reg_SPEC> as RegisterValue<_>>::new(0)
1584    }
1585}
1586
1587#[doc(hidden)]
1588#[derive(Copy, Clone, Eq, PartialEq)]
1589pub struct MemStatusReg_SPEC;
1590impl crate::sealed::RegSpec for MemStatusReg_SPEC {
1591    type DataType = u32;
1592}
1593
1594#[doc = "Memory Arbiter Status Register"]
1595pub type MemStatusReg = crate::RegValueT<MemStatusReg_SPEC>;
1596
1597impl MemStatusReg {
1598    #[doc = "The maximum number of arbiter clock cycles that an SNC AHB access has been buffered."]
1599    #[inline(always)]
1600    pub fn ahb_snc_wr_buff_cnt(
1601        self,
1602    ) -> crate::common::RegisterField<20, 0xf, 1, 0, u8, u8, MemStatusReg_SPEC, crate::common::R>
1603    {
1604        crate::common::RegisterField::<20,0xf,1,0,u8,u8,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1605    }
1606
1607    #[doc = "The maximum number of arbiter clock cycles that an DMA AHB access has been buffered."]
1608    #[inline(always)]
1609    pub fn ahb_dma_wr_buff_cnt(
1610        self,
1611    ) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, MemStatusReg_SPEC, crate::common::R>
1612    {
1613        crate::common::RegisterField::<16,0xf,1,0,u8,u8,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1614    }
1615
1616    #[doc = "The maximum number of arbiter clock cycles that an CPUC AHB access has been buffered."]
1617    #[inline(always)]
1618    pub fn ahb_cpuc_wr_buff_cnt(
1619        self,
1620    ) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, MemStatusReg_SPEC, crate::common::R>
1621    {
1622        crate::common::RegisterField::<12,0xf,1,0,u8,u8,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1623    }
1624
1625    #[doc = "The maximum number of arbiter clock cycles that an CPUS_AHB access has been buffered."]
1626    #[inline(always)]
1627    pub fn ahb_cpus_wr_buff_cnt(
1628        self,
1629    ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, MemStatusReg_SPEC, crate::common::R>
1630    {
1631        crate::common::RegisterField::<8,0xf,1,0,u8,u8,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1632    }
1633
1634    #[doc = "Writing a \'1\' clears AHB_SNC_WR_BUFF_CNT."]
1635    #[inline(always)]
1636    pub fn ahb_snc_clr_wr_buff(
1637        self,
1638    ) -> crate::common::RegisterFieldBool<7, 1, 0, MemStatusReg_SPEC, crate::common::W> {
1639        crate::common::RegisterFieldBool::<7,1,0,MemStatusReg_SPEC,crate::common::W>::from_register(self,0)
1640    }
1641
1642    #[doc = "Writing a \'1\' clears AHB_DMA_WR_BUFF_CNT."]
1643    #[inline(always)]
1644    pub fn ahb_dma_clr_wr_buff(
1645        self,
1646    ) -> crate::common::RegisterFieldBool<6, 1, 0, MemStatusReg_SPEC, crate::common::W> {
1647        crate::common::RegisterFieldBool::<6,1,0,MemStatusReg_SPEC,crate::common::W>::from_register(self,0)
1648    }
1649
1650    #[doc = "Writing a \'1\' clears AHB_CPUC_WR_BUFF_CNT."]
1651    #[inline(always)]
1652    pub fn ahb_cpuc_clr_wr_buff(
1653        self,
1654    ) -> crate::common::RegisterFieldBool<5, 1, 0, MemStatusReg_SPEC, crate::common::W> {
1655        crate::common::RegisterFieldBool::<5,1,0,MemStatusReg_SPEC,crate::common::W>::from_register(self,0)
1656    }
1657
1658    #[doc = "Writing a \'1\' clears AHB_CPUS_WR_BUFF_CNT."]
1659    #[inline(always)]
1660    pub fn ahb_cpus_clr_wr_buff(
1661        self,
1662    ) -> crate::common::RegisterFieldBool<4, 1, 0, MemStatusReg_SPEC, crate::common::W> {
1663        crate::common::RegisterFieldBool::<4,1,0,MemStatusReg_SPEC,crate::common::W>::from_register(self,0)
1664    }
1665
1666    #[doc = "0: No SNC AHB write access is buffered.\n1: Currently a single SNC AHB write access is buffered in the arbiter."]
1667    #[inline(always)]
1668    pub fn ahb_snc_write_buff(
1669        self,
1670    ) -> crate::common::RegisterFieldBool<3, 1, 0, MemStatusReg_SPEC, crate::common::R> {
1671        crate::common::RegisterFieldBool::<3,1,0,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1672    }
1673
1674    #[doc = "0: No DMA AHB write access is buffered.\n1: Currently a single DMA AHB write access is buffered in the arbiter."]
1675    #[inline(always)]
1676    pub fn ahb_dma_write_buff(
1677        self,
1678    ) -> crate::common::RegisterFieldBool<2, 1, 0, MemStatusReg_SPEC, crate::common::R> {
1679        crate::common::RegisterFieldBool::<2,1,0,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1680    }
1681
1682    #[doc = "0: No CPUC AHB write access is buffered.\n1: Currently a single CPUC AHB write access is buffered in the arbiter."]
1683    #[inline(always)]
1684    pub fn ahb_cpuc_write_buff(
1685        self,
1686    ) -> crate::common::RegisterFieldBool<1, 1, 0, MemStatusReg_SPEC, crate::common::R> {
1687        crate::common::RegisterFieldBool::<1,1,0,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1688    }
1689
1690    #[doc = "0: No CPUS AHB write access is buffered.\n1: Currently a single CPUS AHB write access is buffered in the arbiter."]
1691    #[inline(always)]
1692    pub fn ahb_cpus_write_buff(
1693        self,
1694    ) -> crate::common::RegisterFieldBool<0, 1, 0, MemStatusReg_SPEC, crate::common::R> {
1695        crate::common::RegisterFieldBool::<0,1,0,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1696    }
1697}
1698impl ::core::default::Default for MemStatusReg {
1699    #[inline(always)]
1700    fn default() -> MemStatusReg {
1701        <crate::RegValueT<MemStatusReg_SPEC> as RegisterValue<_>>::new(0)
1702    }
1703}
da1470x_pac/memctrl.rs

da1470x_pac/
memctrl.rs
