da14697_pac/
spi2.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:38 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"SPI2 registers"]
28unsafe impl ::core::marker::Send for super::Spi2 {}
29unsafe impl ::core::marker::Sync for super::Spi2 {}
30impl super::Spi2 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "SPI clear interrupt register"]
38    #[inline(always)]
39    pub const fn spi2_clear_int_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::Spi2ClearIntReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::Spi2ClearIntReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(8usize),
45            )
46        }
47    }
48
49    #[doc = "SPI control register 0"]
50    #[inline(always)]
51    pub const fn spi2_ctrl_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::Spi2CtrlReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::Spi2CtrlReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0usize),
57            )
58        }
59    }
60
61    #[doc = "SPI RX/TX register0"]
62    #[inline(always)]
63    pub const fn spi2_rx_tx_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::Spi2RxTxReg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::Spi2RxTxReg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(4usize),
69            )
70        }
71    }
72}
73#[doc(hidden)]
74#[derive(Copy, Clone, Eq, PartialEq)]
75pub struct Spi2ClearIntReg_SPEC;
76impl crate::sealed::RegSpec for Spi2ClearIntReg_SPEC {
77    type DataType = u32;
78}
79
80#[doc = "SPI clear interrupt register"]
81pub type Spi2ClearIntReg = crate::RegValueT<Spi2ClearIntReg_SPEC>;
82
83impl Spi2ClearIntReg {
84    #[doc = "Writing any value to this register will clear the SPI_CTRL_REG\\[SPI_INT_BIT\\]\nReading returns 0."]
85    #[inline(always)]
86    pub fn spi_clear_int(
87        self,
88    ) -> crate::common::RegisterField<
89        0,
90        0xffffffff,
91        1,
92        0,
93        u32,
94        u32,
95        Spi2ClearIntReg_SPEC,
96        crate::common::W,
97    > {
98        crate::common::RegisterField::<
99            0,
100            0xffffffff,
101            1,
102            0,
103            u32,
104            u32,
105            Spi2ClearIntReg_SPEC,
106            crate::common::W,
107        >::from_register(self, 0)
108    }
109}
110impl ::core::default::Default for Spi2ClearIntReg {
111    #[inline(always)]
112    fn default() -> Spi2ClearIntReg {
113        <crate::RegValueT<Spi2ClearIntReg_SPEC> as RegisterValue<_>>::new(0)
114    }
115}
116
117#[doc(hidden)]
118#[derive(Copy, Clone, Eq, PartialEq)]
119pub struct Spi2CtrlReg_SPEC;
120impl crate::sealed::RegSpec for Spi2CtrlReg_SPEC {
121    type DataType = u32;
122}
123
124#[doc = "SPI control register 0"]
125pub type Spi2CtrlReg = crate::RegValueT<Spi2CtrlReg_SPEC>;
126
127impl Spi2CtrlReg {
128    #[doc = "When 1, SPI Interrupt is generated when TX fifo is not full"]
129    #[inline(always)]
130    pub fn spi_tx_fifo_notfull_mask(
131        self,
132    ) -> crate::common::RegisterFieldBool<25, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
133        crate::common::RegisterFieldBool::<25,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
134    }
135
136    #[doc = "In case SPI_FIFO_MODE=3\n0 = DMA TX request is generated when transaction is finished\n1 = DMA TX request is generated when tx buffer is free"]
137    #[inline(always)]
138    pub fn spi_dma_txreq_mode(
139        self,
140    ) -> crate::common::RegisterFieldBool<24, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
141        crate::common::RegisterFieldBool::<24,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
142    }
143
144    #[doc = "0 = Trasmit fifo is not empty\n1 = Trasmit fifo is empty"]
145    #[inline(always)]
146    pub fn spi_tx_fifo_empty(
147        self,
148    ) -> crate::common::RegisterFieldBool<23, 1, 0, Spi2CtrlReg_SPEC, crate::common::R> {
149        crate::common::RegisterFieldBool::<23,1,0,Spi2CtrlReg_SPEC,crate::common::R>::from_register(self,0)
150    }
151
152    #[doc = "0 = Receive fifo is not full\n1 = Receive fifo is full"]
153    #[inline(always)]
154    pub fn spi_rx_fifo_full(
155        self,
156    ) -> crate::common::RegisterFieldBool<22, 1, 0, Spi2CtrlReg_SPEC, crate::common::R> {
157        crate::common::RegisterFieldBool::<22,1,0,Spi2CtrlReg_SPEC,crate::common::R>::from_register(self,0)
158    }
159
160    #[doc = "0 = Receive fifo is not empty\n1 = Receive fifo is empty"]
161    #[inline(always)]
162    pub fn spi_rx_fifo_empty(
163        self,
164    ) -> crate::common::RegisterFieldBool<21, 1, 0, Spi2CtrlReg_SPEC, crate::common::R> {
165        crate::common::RegisterFieldBool::<21,1,0,Spi2CtrlReg_SPEC,crate::common::R>::from_register(self,0)
166    }
167
168    #[doc = "Determines the value of the first bit in 9 bits SPI mode."]
169    #[inline(always)]
170    pub fn spi_9bit_val(
171        self,
172    ) -> crate::common::RegisterFieldBool<20, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
173        crate::common::RegisterFieldBool::<20,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
174    }
175
176    #[doc = "0 = The SPI is not busy with a transfer. This means that either no TX-data is available or that the transfers have been suspended due to a full RX-FIFO. The SPI_CTRL_REG\\[SPI_INT_BIT\\] can be used to distinguish between these situations.\n1 = The SPI is busy with a transfer."]
177    #[inline(always)]
178    pub fn spi_busy(
179        self,
180    ) -> crate::common::RegisterFieldBool<19, 1, 0, Spi2CtrlReg_SPEC, crate::common::R> {
181        crate::common::RegisterFieldBool::<19,1,0,Spi2CtrlReg_SPEC,crate::common::R>::from_register(self,0)
182    }
183
184    #[doc = "0 = The SPI has low priority, the DMA request signals are reset after the corresponding acknowledge.\n1 = The SPI has high priority, DMA request signals remain\nactive until the FIFOS are filled/emptied, so the DMA holds the AHB bus."]
185    #[inline(always)]
186    pub fn spi_priority(
187        self,
188    ) -> crate::common::RegisterFieldBool<18, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
189        crate::common::RegisterFieldBool::<18,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
190    }
191
192    #[doc = "0 = TX-FIFO and RX-FIFO used (Bidirectional mode).\n1 = RX-FIFO used (Read Only Mode) TX-FIFO single depth, no flow control\n2 = TX-FIFO used (Write Only Mode), RX-FIFO single depth, no flow control\n3 = No FIFOs used (backwards compatible mode)"]
193    #[inline(always)]
194    pub fn spi_fifo_mode(
195        self,
196    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, Spi2CtrlReg_SPEC, crate::common::RW>
197    {
198        crate::common::RegisterField::<16,0x3,1,0,u8,u8,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
199    }
200
201    #[doc = "0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don\'t care.\n1 = SPI_EN pin enabled in slave mode."]
202    #[inline(always)]
203    pub fn spi_en_ctrl(
204        self,
205    ) -> crate::common::RegisterFieldBool<15, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
206        crate::common::RegisterFieldBool::<15,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
207    }
208
209    #[doc = "0 = Disable SPI_INT_BIT to ICU\n1 = Enable SPI_INT_BIT to ICU."]
210    #[inline(always)]
211    pub fn spi_mint(
212        self,
213    ) -> crate::common::RegisterFieldBool<14, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
214        crate::common::RegisterFieldBool::<14,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
215    }
216
217    #[doc = "0 = RX Register or FIFO is empty.\n1 = SPI interrupt. Data has been transmitted and receivedMust be reset by SW by writing to SPI_CLEAR_INT_REG."]
218    #[inline(always)]
219    pub fn spi_int_bit(
220        self,
221    ) -> crate::common::RegisterFieldBool<13, 1, 0, Spi2CtrlReg_SPEC, crate::common::R> {
222        crate::common::RegisterFieldBool::<13,1,0,Spi2CtrlReg_SPEC,crate::common::R>::from_register(self,0)
223    }
224
225    #[doc = "Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles)"]
226    #[inline(always)]
227    pub fn spi_di(
228        self,
229    ) -> crate::common::RegisterFieldBool<12, 1, 0, Spi2CtrlReg_SPEC, crate::common::R> {
230        crate::common::RegisterFieldBool::<12,1,0,Spi2CtrlReg_SPEC,crate::common::R>::from_register(self,0)
231    }
232
233    #[doc = "0 = TX-FIFO is not full, data can be written.\n1 = TX-FIFO is full, data can not be written."]
234    #[inline(always)]
235    pub fn spi_txh(
236        self,
237    ) -> crate::common::RegisterFieldBool<11, 1, 0, Spi2CtrlReg_SPEC, crate::common::R> {
238        crate::common::RegisterFieldBool::<11,1,0,Spi2CtrlReg_SPEC,crate::common::R>::from_register(self,0)
239    }
240
241    #[doc = "0 = normal operation\n1 = Force SPIDO output level to value of SPI_DO."]
242    #[inline(always)]
243    pub fn spi_force_do(
244        self,
245    ) -> crate::common::RegisterFieldBool<10, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
246        crate::common::RegisterFieldBool::<10,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
247    }
248
249    #[doc = "00 = 8 bits mode\n01 = 16 bit mode\n10 = 32 bits mode\n11 = 9 bits mode. Only valid in master mode."]
250    #[inline(always)]
251    pub fn spi_word(
252        self,
253    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Spi2CtrlReg_SPEC, crate::common::RW>
254    {
255        crate::common::RegisterField::<8,0x3,1,0,u8,u8,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
256    }
257
258    #[doc = "0 = normal operation\n1 = Reset SPI. Same function as SPI_ON except that internal clock remain active."]
259    #[inline(always)]
260    pub fn spi_rst(
261        self,
262    ) -> crate::common::RegisterFieldBool<7, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
263        crate::common::RegisterFieldBool::<7,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
264    }
265
266    #[doc = "Master/slave mode\n0 = Master\n1 = Slave"]
267    #[inline(always)]
268    pub fn spi_smn(
269        self,
270    ) -> crate::common::RegisterFieldBool<6, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
271        crate::common::RegisterFieldBool::<6,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
272    }
273
274    #[doc = "Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1"]
275    #[inline(always)]
276    pub fn spi_do(
277        self,
278    ) -> crate::common::RegisterFieldBool<5, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
279        crate::common::RegisterFieldBool::<5,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
280    }
281
282    #[doc = "Select SPI_CLK clock output frequency in master mode:\n00 = SPI_CLK / 8\n01 = SPI_CLK / 4\n10 = SPI_CLK / 2\n11 = SPI_CLK / 14"]
283    #[inline(always)]
284    pub fn spi_clk(
285        self,
286    ) -> crate::common::RegisterField<3, 0x3, 1, 0, u8, u8, Spi2CtrlReg_SPEC, crate::common::RW>
287    {
288        crate::common::RegisterField::<3,0x3,1,0,u8,u8,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
289    }
290
291    #[doc = "Select SPI_CLK polarity.\n0 = SPI_CLK is initially low.\n1 = SPI_CLK is initially high."]
292    #[inline(always)]
293    pub fn spi_pol(
294        self,
295    ) -> crate::common::RegisterFieldBool<2, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
296        crate::common::RegisterFieldBool::<2,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
297    }
298
299    #[doc = "Select SPI_CLK phase. See functional timing diagrams in SPI chapter"]
300    #[inline(always)]
301    pub fn spi_pha(
302        self,
303    ) -> crate::common::RegisterFieldBool<1, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
304        crate::common::RegisterFieldBool::<1,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
305    }
306
307    #[doc = "0 = SPI Module switched off (power saving). Everything is reset except SPI_CTRL_REG. When this bit is cleared the SPI will remain active in master mode until the shift register and holding register are both empty.\n1 = SPI Module switched on. Should only be set after all control bits have their desired values. So two writes are needed!"]
308    #[inline(always)]
309    pub fn spi_on(
310        self,
311    ) -> crate::common::RegisterFieldBool<0, 1, 0, Spi2CtrlReg_SPEC, crate::common::RW> {
312        crate::common::RegisterFieldBool::<0,1,0,Spi2CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
313    }
314}
315impl ::core::default::Default for Spi2CtrlReg {
316    #[inline(always)]
317    fn default() -> Spi2CtrlReg {
318        <crate::RegValueT<Spi2CtrlReg_SPEC> as RegisterValue<_>>::new(10682368)
319    }
320}
321
322#[doc(hidden)]
323#[derive(Copy, Clone, Eq, PartialEq)]
324pub struct Spi2RxTxReg_SPEC;
325impl crate::sealed::RegSpec for Spi2RxTxReg_SPEC {
326    type DataType = u32;
327}
328
329#[doc = "SPI RX/TX register0"]
330pub type Spi2RxTxReg = crate::RegValueT<Spi2RxTxReg_SPEC>;
331
332impl Spi2RxTxReg {
333    #[doc = "Write: SPI_TX_REG output register 0 (TX-FIFO)\nRead: SPI_RX_REG input register 0 (RX-FIFO)\nIn 8 or 9 bits mode bits 31 to 8 are not used, they contain old data.\nIn 16 bits mode bits 31 to 16 are not used, they contain old data."]
334    #[inline(always)]
335    pub fn spi_data(
336        self,
337    ) -> crate::common::RegisterField<
338        0,
339        0xffffffff,
340        1,
341        0,
342        u32,
343        u32,
344        Spi2RxTxReg_SPEC,
345        crate::common::W,
346    > {
347        crate::common::RegisterField::<
348            0,
349            0xffffffff,
350            1,
351            0,
352            u32,
353            u32,
354            Spi2RxTxReg_SPEC,
355            crate::common::W,
356        >::from_register(self, 0)
357    }
358}
359impl ::core::default::Default for Spi2RxTxReg {
360    #[inline(always)]
361    fn default() -> Spi2RxTxReg {
362        <crate::RegValueT<Spi2RxTxReg_SPEC> as RegisterValue<_>>::new(0)
363    }
364}
da14697_pac/spi2.rs

da14697_pac/
spi2.rs
