da14697_pac/
otpc.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:38 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"OTPC registers"]
28unsafe impl ::core::marker::Send for super::Otpc {}
29unsafe impl ::core::marker::Sync for super::Otpc {}
30impl super::Otpc {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Mode register"]
38    #[inline(always)]
39    pub const fn otpc_mode_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::OtpcModeReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::OtpcModeReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(0usize),
45            )
46        }
47    }
48
49    #[doc = "The address of the word that will be programmed, when the PROG mode is used."]
50    #[inline(always)]
51    pub const fn otpc_paddr_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::OtpcPaddrReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::OtpcPaddrReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(8usize),
57            )
58        }
59    }
60
61    #[doc = "The 32-bit word that will be programmed, when the PROG mode is used."]
62    #[inline(always)]
63    pub const fn otpc_pword_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::OtpcPwordReg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::OtpcPwordReg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(12usize),
69            )
70        }
71    }
72
73    #[doc = "Status register"]
74    #[inline(always)]
75    pub const fn otpc_stat_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::OtpcStatReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::OtpcStatReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(4usize),
81            )
82        }
83    }
84
85    #[doc = "Various timing parameters of the OTP cell."]
86    #[inline(always)]
87    pub const fn otpc_tim1_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::OtpcTim1Reg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::OtpcTim1Reg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(16usize),
93            )
94        }
95    }
96
97    #[doc = "Various timing parameters of the OTP cell."]
98    #[inline(always)]
99    pub const fn otpc_tim2_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::OtpcTim2Reg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::OtpcTim2Reg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(20usize),
105            )
106        }
107    }
108}
109#[doc(hidden)]
110#[derive(Copy, Clone, Eq, PartialEq)]
111pub struct OtpcModeReg_SPEC;
112impl crate::sealed::RegSpec for OtpcModeReg_SPEC {
113    type DataType = u32;
114}
115
116#[doc = "Mode register"]
117pub type OtpcModeReg = crate::RegValueT<OtpcModeReg_SPEC>;
118
119impl OtpcModeReg {
120    #[doc = "Defines the part of the OTP cell that is programmed by the controller during the PROG mode, for each program request that is applied.\n0x0 : Both normal and redundancy arrays are programmed. This is the normal way of programming.\n0x1 : Only the normal array is programmed.\n0x2 : Only the redundancy array is programmed.\n0x3 : Reserved\nThe value of this configuration field can be modified only when the controller is in an inactive mode (PDOWN, DSTBY, STBY). The setting will take effect when will be enabled again the PROG mode."]
121    #[inline(always)]
122    pub fn otpc_mode_prg_sel(
123        self,
124    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, OtpcModeReg_SPEC, crate::common::RW>
125    {
126        crate::common::RegisterField::<6,0x3,1,0,u8,u8,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
127    }
128
129    #[doc = "Defines the temperature condition under which is performed a margin read. It affects only the initial margin read (RINI mode) and the programming verification margin read (PVFY).\n0 : Regular temperature condition (less than 85°C)\n1 : High temperature condition (85°C or more)\nThe value of this configuration field can be modified only when the controller is in an inactive mode (PDOWN, DSTBY, STBY). The selection will take effect at the next PVFY or RINI mode that will be enabled. The READ mode is not affected by the setting of this configuration bit."]
130    #[inline(always)]
131    pub fn otpc_mode_ht_marg_en(
132        self,
133    ) -> crate::common::RegisterFieldBool<5, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
134        crate::common::RegisterFieldBool::<5,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
135    }
136
137    #[doc = "Selects the memory area of the OTP cell that will be used.\n0 - Uses the main memory area of the OTP cell\n1 - Uses the test row of the OTP cell\nThe value of this configuration field can be modified only when the controller is in an inactive mode (PDOWN, DSTBY, STBY). The selection will take effect at the next programming or reading mode that will be enabled."]
138    #[inline(always)]
139    pub fn otpc_mode_use_tst_row(
140        self,
141    ) -> crate::common::RegisterFieldBool<4, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
142        crate::common::RegisterFieldBool::<4,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
143    }
144
145    #[doc = "Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows:\n0x0: PDOWN. The power supply of the OTP memory is OFF.\n0x1: DSTBY. The OTP memory is in deep standby mode (power supply ON and internal LDO OFF).\n0x2: STBY. The OTP memory is powered (power supply ON and internal LDO ON, but is not selected.\n0x3: READ. The OTP memory is in the normal read mode.\n0x4: PROG. The OTP memory is in programming mode.\n0x5: PVFY. The OTP memory is in programming verification mode (margin read after programming).\n0x6: RINI. The OTP memory is in initial read mode (initial margin read).\n0x7: Reserved.\n\nWhenever the OTPC_MODE_REG\\[MODE\\] is changing, the status bit OTPC_STAT_REG\\[OTPC_STAT_MRDY\\] gets the value zero. The new mode will be ready for use when the OTPC_STAT_MRDY become again 1. During the mode transition the OTPC_MODE_REG\\[MODE\\] become read only. Do not try to use or change any function of the controller until the OTPC_STAT_MRDY bit to become equal to 1."]
146    #[inline(always)]
147    pub fn otpc_mode_mode(
148        self,
149    ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, OtpcModeReg_SPEC, crate::common::RW>
150    {
151        crate::common::RegisterField::<0,0x7,1,0,u8,u8,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
152    }
153}
154impl ::core::default::Default for OtpcModeReg {
155    #[inline(always)]
156    fn default() -> OtpcModeReg {
157        <crate::RegValueT<OtpcModeReg_SPEC> as RegisterValue<_>>::new(0)
158    }
159}
160
161#[doc(hidden)]
162#[derive(Copy, Clone, Eq, PartialEq)]
163pub struct OtpcPaddrReg_SPEC;
164impl crate::sealed::RegSpec for OtpcPaddrReg_SPEC {
165    type DataType = u32;
166}
167
168#[doc = "The address of the word that will be programmed, when the PROG mode is used."]
169pub type OtpcPaddrReg = crate::RegValueT<OtpcPaddrReg_SPEC>;
170
171impl OtpcPaddrReg {
172    #[doc = "The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory.\nThe OTPC_PADDR_REG refers to a word address. The OTPC_PADDR_REG has to be writen after the OTP_PWORD_REG and only if the OTPC_STAT_REG\\[OTPC_STAT_PBUF_EMPTY\\]=1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG\\[OTPC_STAT_PBUF_EMPTY\\]=0). A writting to the OTPC_PADDR_REG triggers the controller to start the programming procedure (only if the PROG mode is active)."]
173    #[inline(always)]
174    pub fn otpc_paddr(
175        self,
176    ) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, OtpcPaddrReg_SPEC, crate::common::RW>
177    {
178        crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,OtpcPaddrReg_SPEC,crate::common::RW>::from_register(self,0)
179    }
180}
181impl ::core::default::Default for OtpcPaddrReg {
182    #[inline(always)]
183    fn default() -> OtpcPaddrReg {
184        <crate::RegValueT<OtpcPaddrReg_SPEC> as RegisterValue<_>>::new(0)
185    }
186}
187
188#[doc(hidden)]
189#[derive(Copy, Clone, Eq, PartialEq)]
190pub struct OtpcPwordReg_SPEC;
191impl crate::sealed::RegSpec for OtpcPwordReg_SPEC {
192    type DataType = u32;
193}
194
195#[doc = "The 32-bit word that will be programmed, when the PROG mode is used."]
196pub type OtpcPwordReg = crate::RegValueT<OtpcPwordReg_SPEC>;
197
198impl OtpcPwordReg {
199    #[doc = "The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP memory, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory.\nThe OTP_PWORD_REG must be written before the OTPC_PADDR_REG and only if OTPC_STAT_REG\\[OTPC_STAT_PBUF_EMPTY\\] = 1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG\\[OTPC_STAT_PBUF_EMPTY\\]=0)."]
200    #[inline(always)]
201    pub fn otpc_pword(
202        self,
203    ) -> crate::common::RegisterField<
204        0,
205        0xffffffff,
206        1,
207        0,
208        u32,
209        u32,
210        OtpcPwordReg_SPEC,
211        crate::common::RW,
212    > {
213        crate::common::RegisterField::<
214            0,
215            0xffffffff,
216            1,
217            0,
218            u32,
219            u32,
220            OtpcPwordReg_SPEC,
221            crate::common::RW,
222        >::from_register(self, 0)
223    }
224}
225impl ::core::default::Default for OtpcPwordReg {
226    #[inline(always)]
227    fn default() -> OtpcPwordReg {
228        <crate::RegValueT<OtpcPwordReg_SPEC> as RegisterValue<_>>::new(0)
229    }
230}
231
232#[doc(hidden)]
233#[derive(Copy, Clone, Eq, PartialEq)]
234pub struct OtpcStatReg_SPEC;
235impl crate::sealed::RegSpec for OtpcStatReg_SPEC {
236    type DataType = u32;
237}
238
239#[doc = "Status register"]
240pub type OtpcStatReg = crate::RegValueT<OtpcStatReg_SPEC>;
241
242impl OtpcStatReg {
243    #[doc = "Indicates the progress of the transition from a mode of operation to a new mode of operation.\n0 : There is a transition in progress in a new mode of operation . Wait until the transition to be completed.\n1 : The transition to the new mode of operation has been completed. The function that has been enabled by the new mode can be used. A new mode can be applied.\nThis status bit gets the value zero every time where the OTPC_MODE_REG\\[MODE\\] is changing. Do not try to use or change any function of the controller until this status bit to becomes equal to 1."]
244    #[inline(always)]
245    pub fn otpc_stat_mrdy(
246        self,
247    ) -> crate::common::RegisterFieldBool<2, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
248        crate::common::RegisterFieldBool::<2,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
249    }
250
251    #[doc = "Indicates the status of the programming buffer (PBUF).\n0 : The PBUF contains the address and the data of a programming request. The OTPC_PADDR_REG and the OTPC_PWORD_REG should not be written as long as this status bit is zero.\n1 : The PBUF is empty and a new programming request can be registered in the PBUF by using the OTPC_PADDR_REG and the OTPC_PWORD_REG registers.\nThis status bit gets the value zero every time where a progrmaming is triggered by the OTPC_PADDR_REG (only if the PROG mode is active)."]
252    #[inline(always)]
253    pub fn otpc_stat_pbuf_empty(
254        self,
255    ) -> crate::common::RegisterFieldBool<1, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
256        crate::common::RegisterFieldBool::<1,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
257    }
258
259    #[doc = "Indicates the state of the programming process.\n0: The controller is busy. A programming is in progress.\n1: The logic which performs programming is idle."]
260    #[inline(always)]
261    pub fn otpc_stat_prdy(
262        self,
263    ) -> crate::common::RegisterFieldBool<0, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
264        crate::common::RegisterFieldBool::<0,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
265    }
266}
267impl ::core::default::Default for OtpcStatReg {
268    #[inline(always)]
269    fn default() -> OtpcStatReg {
270        <crate::RegValueT<OtpcStatReg_SPEC> as RegisterValue<_>>::new(7)
271    }
272}
273
274#[doc(hidden)]
275#[derive(Copy, Clone, Eq, PartialEq)]
276pub struct OtpcTim1Reg_SPEC;
277impl crate::sealed::RegSpec for OtpcTim1Reg_SPEC {
278    type DataType = u32;
279}
280
281#[doc = "Various timing parameters of the OTP cell."]
282pub type OtpcTim1Reg = crate::RegValueT<OtpcTim1Reg_SPEC>;
283
284impl OtpcTim1Reg {
285    #[doc = "The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for programming. It must be :\n- at least 10us\n- no more than 100us"]
286    #[inline(always)]
287    pub fn otpc_tim1_us_t_csp(
288        self,
289    ) -> crate::common::RegisterField<24, 0x7f, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
290    {
291        crate::common::RegisterField::<24,0x7f,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
292    }
293
294    #[doc = "The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for any kind of read. It must be at least 10us."]
295    #[inline(always)]
296    pub fn otpc_tim1_us_t_cs(
297        self,
298    ) -> crate::common::RegisterField<20, 0xf, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
299    {
300        crate::common::RegisterField::<20,0xf,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
301    }
302
303    #[doc = "The number of microseconds (minus one) that are required until to be enabled the LDO of the OTP. It must be at least 10us."]
304    #[inline(always)]
305    pub fn otpc_tim1_us_t_pl(
306        self,
307    ) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
308    {
309        crate::common::RegisterField::<16,0xf,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
310    }
311
312    #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 60ns. This timing parameter refers to the access time of the OTP memory."]
313    #[inline(always)]
314    pub fn otpc_tim1_cc_t_rd(
315        self,
316    ) -> crate::common::RegisterField<12, 0x7, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
317    {
318        crate::common::RegisterField::<12,0x7,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
319    }
320
321    #[doc = "The number of hclk_c clock periods (minus one) that give a time interval that is at least higher than 20 ns."]
322    #[inline(always)]
323    pub fn otpc_tim1_cc_t_20ns(
324        self,
325    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
326    {
327        crate::common::RegisterField::<8,0x3,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
328    }
329
330    #[doc = "The number of hclk_c clock periods (minus one) that give a time interval equal to 1us. This setting affects all the timing parameters that refer to microseconds, due to that defines the correspondence of a microsecond to a number of hclk_c clock cycles."]
331    #[inline(always)]
332    pub fn otpc_tim1_cc_t_1us(
333        self,
334    ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
335    {
336        crate::common::RegisterField::<0,0x7f,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
337    }
338}
339impl ::core::default::Default for OtpcTim1Reg {
340    #[inline(always)]
341    fn default() -> OtpcTim1Reg {
342        <crate::RegValueT<OtpcTim1Reg_SPEC> as RegisterValue<_>>::new(161026079)
343    }
344}
345
346#[doc(hidden)]
347#[derive(Copy, Clone, Eq, PartialEq)]
348pub struct OtpcTim2Reg_SPEC;
349impl crate::sealed::RegSpec for OtpcTim2Reg_SPEC {
350    type DataType = u32;
351}
352
353#[doc = "Various timing parameters of the OTP cell."]
354pub type OtpcTim2Reg = crate::RegValueT<OtpcTim2Reg_SPEC>;
355
356impl OtpcTim2Reg {
357    #[doc = "Adds an additional hclk_c clock cycle at all the time intervals that count in microseconds.\n0 : The extra hclk_c clock cycle is not applied\n1 : The extra hclk_c clock cycle is applied"]
358    #[inline(always)]
359    pub fn otpc_tim2_us_add_cc_en(
360        self,
361    ) -> crate::common::RegisterFieldBool<31, 1, 0, OtpcTim2Reg_SPEC, crate::common::RW> {
362        crate::common::RegisterFieldBool::<31,1,0,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
363    }
364
365    #[doc = "The number of microseconds (minus one) that are required after the exit from the deep sleep standby mode and before to become ready to enter in an active mode (reading or programming). It must be at least 2us."]
366    #[inline(always)]
367    pub fn otpc_tim2_us_t_sas(
368        self,
369    ) -> crate::common::RegisterField<29, 0x3, 1, 0, u8, u8, OtpcTim2Reg_SPEC, crate::common::RW>
370    {
371        crate::common::RegisterField::<29,0x3,1,0,u8,u8,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
372    }
373
374    #[doc = "The number of microseconds (minus one) that are required after the last programming pulse and before to be disabled the programming mode in the OTP memory. It must be:\n- at least 5us\n- no more than 20us"]
375    #[inline(always)]
376    pub fn otpc_tim2_us_t_pph(
377        self,
378    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, OtpcTim2Reg_SPEC, crate::common::RW>
379    {
380        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
381    }
382
383    #[doc = "The number of microseconds (minus one) that are required after the enabling of the power supply of the OTP memory and before to become ready for the enabling of the internal LDO. It must be at least 1us."]
384    #[inline(always)]
385    pub fn otpc_tim2_us_t_vds(
386        self,
387    ) -> crate::common::RegisterField<21, 0x7, 1, 0, u8, u8, OtpcTim2Reg_SPEC, crate::common::RW>
388    {
389        crate::common::RegisterField::<21,0x7,1,0,u8,u8,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
390    }
391
392    #[doc = "The number of microseconds (minus one) that are required after the enabling of the programming in the OTP memory and before to be applied the first programming pulse. It must be :\n- at least 5us\n- no more than 20us"]
393    #[inline(always)]
394    pub fn otpc_tim2_us_t_pps(
395        self,
396    ) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, OtpcTim2Reg_SPEC, crate::common::RW>
397    {
398        crate::common::RegisterField::<16,0x1f,1,0,u8,u8,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
399    }
400
401    #[doc = "The number of microseconds (minus one) for recovery after a programming sequence. It must be :\n- at least 5us\n- no more than 100us"]
402    #[inline(always)]
403    pub fn otpc_tim2_us_t_ppr(
404        self,
405    ) -> crate::common::RegisterField<8, 0x7f, 1, 0, u8, u8, OtpcTim2Reg_SPEC, crate::common::RW>
406    {
407        crate::common::RegisterField::<8,0x7f,1,0,u8,u8,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
408    }
409
410    #[doc = "The number of microseconds (minus one) between two consecutive programming pulses. It must be :\n- at least 1us\n- no more than 5us"]
411    #[inline(always)]
412    pub fn otpc_tim2_us_t_pwi(
413        self,
414    ) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, OtpcTim2Reg_SPEC, crate::common::RW>
415    {
416        crate::common::RegisterField::<5,0x7,1,0,u8,u8,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
417    }
418
419    #[doc = "The number of microseconds (minus one) that lasts the programming of each bit. It must be :\n- at least 10us\n- no more than 20us"]
420    #[inline(always)]
421    pub fn otpc_tim2_us_t_pw(
422        self,
423    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, OtpcTim2Reg_SPEC, crate::common::RW>
424    {
425        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
426    }
427}
428impl ::core::default::Default for OtpcTim2Reg {
429    #[inline(always)]
430    fn default() -> OtpcTim2Reg {
431        <crate::RegValueT<OtpcTim2Reg_SPEC> as RegisterValue<_>>::new(2147483647)
432    }
433}
da14697_pac/otpc.rs

da14697_pac/
otpc.rs
