da14697_pac/
dw.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:38 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"DW registers"]
28unsafe impl ::core::marker::Send for super::Dw {}
29unsafe impl ::core::marker::Sync for super::Dw {}
30impl super::Dw {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "USB Master clock tokens (AHB DMA layer only)"]
38    #[inline(always)]
39    pub const fn ahb_dma_cclm1_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::AhbDmaCclm1Reg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::AhbDmaCclm1Reg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(84usize),
45            )
46        }
47    }
48
49    #[doc = "GenDMA Master clock tokens (AHB DMA layer only)"]
50    #[inline(always)]
51    pub const fn ahb_dma_cclm2_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::AhbDmaCclm2Reg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::AhbDmaCclm2Reg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(88usize),
57            )
58        }
59    }
60
61    #[doc = "CRYPTO Master clock tokens (AHB DMA layer only)"]
62    #[inline(always)]
63    pub const fn ahb_dma_cclm3_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::AhbDmaCclm3Reg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::AhbDmaCclm3Reg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(92usize),
69            )
70        }
71    }
72
73    #[doc = "CRYPTO Master clock tokens (AHB DMA layer only)"]
74    #[inline(always)]
75    pub const fn ahb_dma_cclm4_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::AhbDmaCclm4Reg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::AhbDmaCclm4Reg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(96usize),
81            )
82        }
83    }
84
85    #[doc = "Default master ID number (AHB DMA layer only)"]
86    #[inline(always)]
87    pub const fn ahb_dma_dflt_master_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::AhbDmaDfltMasterReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::AhbDmaDfltMasterReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(72usize),
93            )
94        }
95    }
96
97    #[doc = "AHB-DMA layer priority level for RFTP (AHB DMA layer only)"]
98    #[inline(always)]
99    pub const fn ahb_dma_pl1_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::AhbDmaPl1Reg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::AhbDmaPl1Reg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(0usize),
105            )
106        }
107    }
108
109    #[doc = "AHB-DMA layer priority level for LCD (AHB DMA layer only)"]
110    #[inline(always)]
111    pub const fn ahb_dma_pl2_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::AhbDmaPl2Reg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::AhbDmaPl2Reg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(4usize),
117            )
118        }
119    }
120
121    #[doc = "AHB-DMA layer Priority level for GEN-DMA (AHB DMA layer only)"]
122    #[inline(always)]
123    pub const fn ahb_dma_pl3_reg(
124        &self,
125    ) -> &'static crate::common::Reg<self::AhbDmaPl3Reg_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::AhbDmaPl3Reg_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(8usize),
129            )
130        }
131    }
132
133    #[doc = "AHB-DMA layer Priority level for CRYPTO-DMA (AHB DMA layer only)"]
134    #[inline(always)]
135    pub const fn ahb_dma_pl4_reg(
136        &self,
137    ) -> &'static crate::common::Reg<self::AhbDmaPl4Reg_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::AhbDmaPl4Reg_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(12usize),
141            )
142        }
143    }
144
145    #[doc = "Master clock refresh period (AHB DMA layer only)"]
146    #[inline(always)]
147    pub const fn ahb_dma_tcl_reg(
148        &self,
149    ) -> &'static crate::common::Reg<self::AhbDmaTclReg_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::AhbDmaTclReg_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(80usize),
153            )
154        }
155    }
156
157    #[doc = "Version ID (AHB DMA layer only)"]
158    #[inline(always)]
159    pub const fn ahb_dma_version_reg(
160        &self,
161    ) -> &'static crate::common::Reg<self::AhbDmaVersionReg_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::AhbDmaVersionReg_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(144usize),
165            )
166        }
167    }
168
169    #[doc = "Weighted-Token Arbitration Scheme Enable (AHB DMA layer only)"]
170    #[inline(always)]
171    pub const fn ahb_dma_wten_reg(
172        &self,
173    ) -> &'static crate::common::Reg<self::AhbDmaWtenReg_SPEC, crate::common::RW> {
174        unsafe {
175            crate::common::Reg::<self::AhbDmaWtenReg_SPEC, crate::common::RW>::from_ptr(
176                self._svd2pac_as_ptr().add(76usize),
177            )
178        }
179    }
180}
181#[doc(hidden)]
182#[derive(Copy, Clone, Eq, PartialEq)]
183pub struct AhbDmaCclm1Reg_SPEC;
184impl crate::sealed::RegSpec for AhbDmaCclm1Reg_SPEC {
185    type DataType = u32;
186}
187
188#[doc = "USB Master clock tokens (AHB DMA layer only)"]
189pub type AhbDmaCclm1Reg = crate::RegValueT<AhbDmaCclm1Reg_SPEC>;
190
191impl AhbDmaCclm1Reg {
192    #[doc = "Number of tokens (counted in AHB clock cycles) that a master can use on the bus before it has to arbitrate on a bus master with low priority and having tokens. Masters with tokens remaining have priority over masters that have used all of their tokens. User should configure all the token values ensuring that the sum does not exceeds the total allocated number of tokens. If a value of zero is configured, then the bus is deemed to have infinite tokens and will always operate in the upper-tier of arbitration."]
193    #[inline(always)]
194    pub fn ahb_dma_cclm(
195        self,
196    ) -> crate::common::RegisterField<
197        0,
198        0xffff,
199        1,
200        0,
201        u16,
202        u16,
203        AhbDmaCclm1Reg_SPEC,
204        crate::common::RW,
205    > {
206        crate::common::RegisterField::<
207            0,
208            0xffff,
209            1,
210            0,
211            u16,
212            u16,
213            AhbDmaCclm1Reg_SPEC,
214            crate::common::RW,
215        >::from_register(self, 0)
216    }
217}
218impl ::core::default::Default for AhbDmaCclm1Reg {
219    #[inline(always)]
220    fn default() -> AhbDmaCclm1Reg {
221        <crate::RegValueT<AhbDmaCclm1Reg_SPEC> as RegisterValue<_>>::new(15)
222    }
223}
224
225#[doc(hidden)]
226#[derive(Copy, Clone, Eq, PartialEq)]
227pub struct AhbDmaCclm2Reg_SPEC;
228impl crate::sealed::RegSpec for AhbDmaCclm2Reg_SPEC {
229    type DataType = u32;
230}
231
232#[doc = "GenDMA Master clock tokens (AHB DMA layer only)"]
233pub type AhbDmaCclm2Reg = crate::RegValueT<AhbDmaCclm2Reg_SPEC>;
234
235impl AhbDmaCclm2Reg {
236    #[doc = "Refer to AHB_DMA_CCLM1_REG"]
237    #[inline(always)]
238    pub fn ahb_dma_cclm(
239        self,
240    ) -> crate::common::RegisterField<
241        0,
242        0xffff,
243        1,
244        0,
245        u16,
246        u16,
247        AhbDmaCclm2Reg_SPEC,
248        crate::common::RW,
249    > {
250        crate::common::RegisterField::<
251            0,
252            0xffff,
253            1,
254            0,
255            u16,
256            u16,
257            AhbDmaCclm2Reg_SPEC,
258            crate::common::RW,
259        >::from_register(self, 0)
260    }
261}
262impl ::core::default::Default for AhbDmaCclm2Reg {
263    #[inline(always)]
264    fn default() -> AhbDmaCclm2Reg {
265        <crate::RegValueT<AhbDmaCclm2Reg_SPEC> as RegisterValue<_>>::new(15)
266    }
267}
268
269#[doc(hidden)]
270#[derive(Copy, Clone, Eq, PartialEq)]
271pub struct AhbDmaCclm3Reg_SPEC;
272impl crate::sealed::RegSpec for AhbDmaCclm3Reg_SPEC {
273    type DataType = u32;
274}
275
276#[doc = "CRYPTO Master clock tokens (AHB DMA layer only)"]
277pub type AhbDmaCclm3Reg = crate::RegValueT<AhbDmaCclm3Reg_SPEC>;
278
279impl AhbDmaCclm3Reg {
280    #[doc = "AHB_DMA_CCLM1_REG"]
281    #[inline(always)]
282    pub fn ahb_dma_cclm(
283        self,
284    ) -> crate::common::RegisterField<
285        0,
286        0xffff,
287        1,
288        0,
289        u16,
290        u16,
291        AhbDmaCclm3Reg_SPEC,
292        crate::common::RW,
293    > {
294        crate::common::RegisterField::<
295            0,
296            0xffff,
297            1,
298            0,
299            u16,
300            u16,
301            AhbDmaCclm3Reg_SPEC,
302            crate::common::RW,
303        >::from_register(self, 0)
304    }
305}
306impl ::core::default::Default for AhbDmaCclm3Reg {
307    #[inline(always)]
308    fn default() -> AhbDmaCclm3Reg {
309        <crate::RegValueT<AhbDmaCclm3Reg_SPEC> as RegisterValue<_>>::new(15)
310    }
311}
312
313#[doc(hidden)]
314#[derive(Copy, Clone, Eq, PartialEq)]
315pub struct AhbDmaCclm4Reg_SPEC;
316impl crate::sealed::RegSpec for AhbDmaCclm4Reg_SPEC {
317    type DataType = u32;
318}
319
320#[doc = "CRYPTO Master clock tokens (AHB DMA layer only)"]
321pub type AhbDmaCclm4Reg = crate::RegValueT<AhbDmaCclm4Reg_SPEC>;
322
323impl AhbDmaCclm4Reg {
324    #[doc = "AHB_DMA_CCLM1_REG"]
325    #[inline(always)]
326    pub fn ahb_dma_cclm(
327        self,
328    ) -> crate::common::RegisterField<
329        0,
330        0xffff,
331        1,
332        0,
333        u16,
334        u16,
335        AhbDmaCclm4Reg_SPEC,
336        crate::common::RW,
337    > {
338        crate::common::RegisterField::<
339            0,
340            0xffff,
341            1,
342            0,
343            u16,
344            u16,
345            AhbDmaCclm4Reg_SPEC,
346            crate::common::RW,
347        >::from_register(self, 0)
348    }
349}
350impl ::core::default::Default for AhbDmaCclm4Reg {
351    #[inline(always)]
352    fn default() -> AhbDmaCclm4Reg {
353        <crate::RegValueT<AhbDmaCclm4Reg_SPEC> as RegisterValue<_>>::new(15)
354    }
355}
356
357#[doc(hidden)]
358#[derive(Copy, Clone, Eq, PartialEq)]
359pub struct AhbDmaDfltMasterReg_SPEC;
360impl crate::sealed::RegSpec for AhbDmaDfltMasterReg_SPEC {
361    type DataType = u32;
362}
363
364#[doc = "Default master ID number (AHB DMA layer only)"]
365pub type AhbDmaDfltMasterReg = crate::RegValueT<AhbDmaDfltMasterReg_SPEC>;
366
367impl AhbDmaDfltMasterReg {
368    #[doc = "Default master ID number register. The default master is the master that is granted by the bus when no master has requested ownership.\n0: Dummy master\n1: RFPT\n2: LCD\n3: GEN-DMA\n3: CRYPTO-DMA"]
369    #[inline(always)]
370    pub fn ahb_dma_dflt_master(
371        self,
372    ) -> crate::common::RegisterField<
373        0,
374        0xf,
375        1,
376        0,
377        u8,
378        u8,
379        AhbDmaDfltMasterReg_SPEC,
380        crate::common::RW,
381    > {
382        crate::common::RegisterField::<
383            0,
384            0xf,
385            1,
386            0,
387            u8,
388            u8,
389            AhbDmaDfltMasterReg_SPEC,
390            crate::common::RW,
391        >::from_register(self, 0)
392    }
393}
394impl ::core::default::Default for AhbDmaDfltMasterReg {
395    #[inline(always)]
396    fn default() -> AhbDmaDfltMasterReg {
397        <crate::RegValueT<AhbDmaDfltMasterReg_SPEC> as RegisterValue<_>>::new(0)
398    }
399}
400
401#[doc(hidden)]
402#[derive(Copy, Clone, Eq, PartialEq)]
403pub struct AhbDmaPl1Reg_SPEC;
404impl crate::sealed::RegSpec for AhbDmaPl1Reg_SPEC {
405    type DataType = u32;
406}
407
408#[doc = "AHB-DMA layer priority level for RFTP (AHB DMA layer only)"]
409pub type AhbDmaPl1Reg = crate::RegValueT<AhbDmaPl1Reg_SPEC>;
410
411impl AhbDmaPl1Reg {
412    #[doc = "Arbitration priority for master RFPT. 0: lowest, 15: highest."]
413    #[inline(always)]
414    pub fn ahb_dma_pl1(
415        self,
416    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, AhbDmaPl1Reg_SPEC, crate::common::RW>
417    {
418        crate::common::RegisterField::<0,0xf,1,0,u8,u8,AhbDmaPl1Reg_SPEC,crate::common::RW>::from_register(self,0)
419    }
420}
421impl ::core::default::Default for AhbDmaPl1Reg {
422    #[inline(always)]
423    fn default() -> AhbDmaPl1Reg {
424        <crate::RegValueT<AhbDmaPl1Reg_SPEC> as RegisterValue<_>>::new(15)
425    }
426}
427
428#[doc(hidden)]
429#[derive(Copy, Clone, Eq, PartialEq)]
430pub struct AhbDmaPl2Reg_SPEC;
431impl crate::sealed::RegSpec for AhbDmaPl2Reg_SPEC {
432    type DataType = u32;
433}
434
435#[doc = "AHB-DMA layer priority level for LCD (AHB DMA layer only)"]
436pub type AhbDmaPl2Reg = crate::RegValueT<AhbDmaPl2Reg_SPEC>;
437
438impl AhbDmaPl2Reg {
439    #[doc = "Arbitration priority for master LCD. 0: lowest, 15: highest."]
440    #[inline(always)]
441    pub fn ahb_dma_pl2(
442        self,
443    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, AhbDmaPl2Reg_SPEC, crate::common::RW>
444    {
445        crate::common::RegisterField::<0,0xf,1,0,u8,u8,AhbDmaPl2Reg_SPEC,crate::common::RW>::from_register(self,0)
446    }
447}
448impl ::core::default::Default for AhbDmaPl2Reg {
449    #[inline(always)]
450    fn default() -> AhbDmaPl2Reg {
451        <crate::RegValueT<AhbDmaPl2Reg_SPEC> as RegisterValue<_>>::new(14)
452    }
453}
454
455#[doc(hidden)]
456#[derive(Copy, Clone, Eq, PartialEq)]
457pub struct AhbDmaPl3Reg_SPEC;
458impl crate::sealed::RegSpec for AhbDmaPl3Reg_SPEC {
459    type DataType = u32;
460}
461
462#[doc = "AHB-DMA layer Priority level for GEN-DMA (AHB DMA layer only)"]
463pub type AhbDmaPl3Reg = crate::RegValueT<AhbDmaPl3Reg_SPEC>;
464
465impl AhbDmaPl3Reg {
466    #[doc = "Arbitration priority for master GEN-DMA. 0: lowest, 15: highest."]
467    #[inline(always)]
468    pub fn ahb_dma_pl3(
469        self,
470    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, AhbDmaPl3Reg_SPEC, crate::common::RW>
471    {
472        crate::common::RegisterField::<0,0xf,1,0,u8,u8,AhbDmaPl3Reg_SPEC,crate::common::RW>::from_register(self,0)
473    }
474}
475impl ::core::default::Default for AhbDmaPl3Reg {
476    #[inline(always)]
477    fn default() -> AhbDmaPl3Reg {
478        <crate::RegValueT<AhbDmaPl3Reg_SPEC> as RegisterValue<_>>::new(13)
479    }
480}
481
482#[doc(hidden)]
483#[derive(Copy, Clone, Eq, PartialEq)]
484pub struct AhbDmaPl4Reg_SPEC;
485impl crate::sealed::RegSpec for AhbDmaPl4Reg_SPEC {
486    type DataType = u32;
487}
488
489#[doc = "AHB-DMA layer Priority level for CRYPTO-DMA (AHB DMA layer only)"]
490pub type AhbDmaPl4Reg = crate::RegValueT<AhbDmaPl4Reg_SPEC>;
491
492impl AhbDmaPl4Reg {
493    #[doc = "Arbitration priority for master CRYPTO-DMA. 0: lowest, 15: highest."]
494    #[inline(always)]
495    pub fn ahb_dma_pl4(
496        self,
497    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, AhbDmaPl4Reg_SPEC, crate::common::RW>
498    {
499        crate::common::RegisterField::<0,0xf,1,0,u8,u8,AhbDmaPl4Reg_SPEC,crate::common::RW>::from_register(self,0)
500    }
501}
502impl ::core::default::Default for AhbDmaPl4Reg {
503    #[inline(always)]
504    fn default() -> AhbDmaPl4Reg {
505        <crate::RegValueT<AhbDmaPl4Reg_SPEC> as RegisterValue<_>>::new(12)
506    }
507}
508
509#[doc(hidden)]
510#[derive(Copy, Clone, Eq, PartialEq)]
511pub struct AhbDmaTclReg_SPEC;
512impl crate::sealed::RegSpec for AhbDmaTclReg_SPEC {
513    type DataType = u32;
514}
515
516#[doc = "Master clock refresh period (AHB DMA layer only)"]
517pub type AhbDmaTclReg = crate::RegValueT<AhbDmaTclReg_SPEC>;
518
519impl AhbDmaTclReg {
520    #[doc = "Master clock refresh period, counting clock cycles. An arbitration period is defined over this number of tokens. When a new arbitration period starts, the master counters are reloaded. Recommended value is the sum of the AHB_DMA_CCLMx_REG valuesplus 2 tokens for each master, i.e. plus 6."]
521    #[inline(always)]
522    pub fn ahb_dma_tcl(
523        self,
524    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, AhbDmaTclReg_SPEC, crate::common::RW>
525    {
526        crate::common::RegisterField::<
527            0,
528            0xffff,
529            1,
530            0,
531            u16,
532            u16,
533            AhbDmaTclReg_SPEC,
534            crate::common::RW,
535        >::from_register(self, 0)
536    }
537}
538impl ::core::default::Default for AhbDmaTclReg {
539    #[inline(always)]
540    fn default() -> AhbDmaTclReg {
541        <crate::RegValueT<AhbDmaTclReg_SPEC> as RegisterValue<_>>::new(65535)
542    }
543}
544
545#[doc(hidden)]
546#[derive(Copy, Clone, Eq, PartialEq)]
547pub struct AhbDmaVersionReg_SPEC;
548impl crate::sealed::RegSpec for AhbDmaVersionReg_SPEC {
549    type DataType = u32;
550}
551
552#[doc = "Version ID (AHB DMA layer only)"]
553pub type AhbDmaVersionReg = crate::RegValueT<AhbDmaVersionReg_SPEC>;
554
555impl AhbDmaVersionReg {
556    #[inline(always)]
557    pub fn ahb_dma_version(
558        self,
559    ) -> crate::common::RegisterField<
560        0,
561        0xffffffff,
562        1,
563        0,
564        u32,
565        u32,
566        AhbDmaVersionReg_SPEC,
567        crate::common::R,
568    > {
569        crate::common::RegisterField::<
570            0,
571            0xffffffff,
572            1,
573            0,
574            u32,
575            u32,
576            AhbDmaVersionReg_SPEC,
577            crate::common::R,
578        >::from_register(self, 0)
579    }
580}
581impl ::core::default::Default for AhbDmaVersionReg {
582    #[inline(always)]
583    fn default() -> AhbDmaVersionReg {
584        <crate::RegValueT<AhbDmaVersionReg_SPEC> as RegisterValue<_>>::new(842085162)
585    }
586}
587
588#[doc(hidden)]
589#[derive(Copy, Clone, Eq, PartialEq)]
590pub struct AhbDmaWtenReg_SPEC;
591impl crate::sealed::RegSpec for AhbDmaWtenReg_SPEC {
592    type DataType = u32;
593}
594
595#[doc = "Weighted-Token Arbitration Scheme Enable (AHB DMA layer only)"]
596pub type AhbDmaWtenReg = crate::RegValueT<AhbDmaWtenReg_SPEC>;
597
598impl AhbDmaWtenReg {
599    #[doc = "Weighted-token arbitration scheme enable."]
600    #[inline(always)]
601    pub fn ahb_dma_wten(
602        self,
603    ) -> crate::common::RegisterFieldBool<0, 1, 0, AhbDmaWtenReg_SPEC, crate::common::RW> {
604        crate::common::RegisterFieldBool::<0,1,0,AhbDmaWtenReg_SPEC,crate::common::RW>::from_register(self,0)
605    }
606}
607impl ::core::default::Default for AhbDmaWtenReg {
608    #[inline(always)]
609    fn default() -> AhbDmaWtenReg {
610        <crate::RegValueT<AhbDmaWtenReg_SPEC> as RegisterValue<_>>::new(0)
611    }
612}
da14697_pac/dw.rs

da14697_pac/
dw.rs
