da14697_pac/
cache.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:38 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"CACHE registers"]
28unsafe impl ::core::marker::Send for super::Cache {}
29unsafe impl ::core::marker::Sync for super::Cache {}
30impl super::Cache {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Cache associativity configuration register"]
38    #[inline(always)]
39    pub const fn cache_assoccfg_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::CacheAssoccfgReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::CacheAssoccfgReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(8usize),
45            )
46        }
47    }
48
49    #[doc = "Cache control register 1"]
50    #[inline(always)]
51    pub const fn cache_ctrl1_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::CacheCtrl1Reg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::CacheCtrl1Reg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0usize),
57            )
58        }
59    }
60
61    #[doc = "Cache control register 2"]
62    #[inline(always)]
63    pub const fn cache_ctrl2_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::CacheCtrl2Reg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::CacheCtrl2Reg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(32usize),
69            )
70        }
71    }
72
73    #[doc = "Cache Flash program size and base address register"]
74    #[inline(always)]
75    pub const fn cache_flash_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::CacheFlashReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::CacheFlashReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(64usize),
81            )
82        }
83    }
84
85    #[doc = "Cache line size configuration register"]
86    #[inline(always)]
87    pub const fn cache_lnsizecfg_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::CacheLnsizecfgReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::CacheLnsizecfgReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(4usize),
93            )
94        }
95    }
96
97    #[doc = "Cache MRM (Miss Rate Monitor) CONTROL register"]
98    #[inline(always)]
99    pub const fn cache_mrm_ctrl_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::CacheMrmCtrlReg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::CacheMrmCtrlReg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(48usize),
105            )
106        }
107    }
108
109    #[doc = "Cache MRM (Miss Rate Monitor) HITS register"]
110    #[inline(always)]
111    pub const fn cache_mrm_hits_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::CacheMrmHitsReg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::CacheMrmHitsReg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(40usize),
117            )
118        }
119    }
120
121    #[doc = "Cache MRM (Miss Rate Monitor) HITS THRESHOLD register"]
122    #[inline(always)]
123    pub const fn cache_mrm_hits_thres_reg(
124        &self,
125    ) -> &'static crate::common::Reg<self::CacheMrmHitsThresReg_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::CacheMrmHitsThresReg_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(60usize),
129            )
130        }
131    }
132
133    #[doc = "Cache MRM (Miss Rate Monitor) MISSES register"]
134    #[inline(always)]
135    pub const fn cache_mrm_misses_reg(
136        &self,
137    ) -> &'static crate::common::Reg<self::CacheMrmMissesReg_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::CacheMrmMissesReg_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(44usize),
141            )
142        }
143    }
144
145    #[doc = "Cache MRM (Miss Rate Monitor) THRESHOLD register"]
146    #[inline(always)]
147    pub const fn cache_mrm_misses_thres_reg(
148        &self,
149    ) -> &'static crate::common::Reg<self::CacheMrmMissesThresReg_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::CacheMrmMissesThresReg_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(56usize),
153            )
154        }
155    }
156
157    #[doc = "Cache MRM (Miss Rate Monitor) TIME INTERVAL register"]
158    #[inline(always)]
159    pub const fn cache_mrm_tint_reg(
160        &self,
161    ) -> &'static crate::common::Reg<self::CacheMrmTintReg_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::CacheMrmTintReg_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(52usize),
165            )
166        }
167    }
168
169    #[doc = "SWD HW reset control register"]
170    #[inline(always)]
171    pub const fn swd_reset_reg(
172        &self,
173    ) -> &'static crate::common::Reg<self::SwdResetReg_SPEC, crate::common::RW> {
174        unsafe {
175            crate::common::Reg::<self::SwdResetReg_SPEC, crate::common::RW>::from_ptr(
176                self._svd2pac_as_ptr().add(80usize),
177            )
178        }
179    }
180}
181#[doc(hidden)]
182#[derive(Copy, Clone, Eq, PartialEq)]
183pub struct CacheAssoccfgReg_SPEC;
184impl crate::sealed::RegSpec for CacheAssoccfgReg_SPEC {
185    type DataType = u32;
186}
187
188#[doc = "Cache associativity configuration register"]
189pub type CacheAssoccfgReg = crate::RegValueT<CacheAssoccfgReg_SPEC>;
190
191impl CacheAssoccfgReg {
192    #[doc = "Cache associativity:\n0: 1-way (direct mapped)\n1: 2-way\n2: 4-way\n3: reserved."]
193    #[inline(always)]
194    pub fn cache_assoc(
195        self,
196    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, CacheAssoccfgReg_SPEC, crate::common::RW>
197    {
198        crate::common::RegisterField::<0,0x3,1,0,u8,u8,CacheAssoccfgReg_SPEC,crate::common::RW>::from_register(self,0)
199    }
200}
201impl ::core::default::Default for CacheAssoccfgReg {
202    #[inline(always)]
203    fn default() -> CacheAssoccfgReg {
204        <crate::RegValueT<CacheAssoccfgReg_SPEC> as RegisterValue<_>>::new(2)
205    }
206}
207
208#[doc(hidden)]
209#[derive(Copy, Clone, Eq, PartialEq)]
210pub struct CacheCtrl1Reg_SPEC;
211impl crate::sealed::RegSpec for CacheCtrl1Reg_SPEC {
212    type DataType = u32;
213}
214
215#[doc = "Cache control register 1"]
216pub type CacheCtrl1Reg = crate::RegValueT<CacheCtrl1Reg_SPEC>;
217
218impl CacheCtrl1Reg {
219    #[doc = "Reserved. Always keep 0."]
220    #[inline(always)]
221    pub fn cache_res1(
222        self,
223    ) -> crate::common::RegisterFieldBool<1, 1, 0, CacheCtrl1Reg_SPEC, crate::common::RW> {
224        crate::common::RegisterFieldBool::<1,1,0,CacheCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
225    }
226
227    #[doc = "Writing a \'1\' into this bit, flushes the contents of the tag memories which invalidates the content of the cache memory.\nThe read of this bit is always \'0\'.\nNote: The flushing of the cache TAG memory takes 0x100 or 0x200 HCLK cycles for a Cache Data RAM size of 8 KB resp. 16 KB."]
228    #[inline(always)]
229    pub fn cache_flush(
230        self,
231    ) -> crate::common::RegisterFieldBool<0, 1, 0, CacheCtrl1Reg_SPEC, crate::common::W> {
232        crate::common::RegisterFieldBool::<0,1,0,CacheCtrl1Reg_SPEC,crate::common::W>::from_register(self,0)
233    }
234}
235impl ::core::default::Default for CacheCtrl1Reg {
236    #[inline(always)]
237    fn default() -> CacheCtrl1Reg {
238        <crate::RegValueT<CacheCtrl1Reg_SPEC> as RegisterValue<_>>::new(0)
239    }
240}
241
242#[doc(hidden)]
243#[derive(Copy, Clone, Eq, PartialEq)]
244pub struct CacheCtrl2Reg_SPEC;
245impl crate::sealed::RegSpec for CacheCtrl2Reg_SPEC {
246    type DataType = u32;
247}
248
249#[doc = "Cache control register 2"]
250pub type CacheCtrl2Reg = crate::RegValueT<CacheCtrl2Reg_SPEC>;
251
252impl CacheCtrl2Reg {
253    #[doc = "0: Cache controller clock gating is not enabled.\n1: Cache controller clock gating is enabled (enabling power saving).\nNote: This bit must be set to \'0\' (default) when setting the CACHE_FLUSH bit while executing from other than QSPI FLASH cached, e.g. from Booter or SYSRAM."]
254    #[inline(always)]
255    pub fn cache_cgen(
256        self,
257    ) -> crate::common::RegisterFieldBool<10, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
258        crate::common::RegisterFieldBool::<10,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
259    }
260
261    #[doc = "0: Cache Data and TAG memory read only.\n1: Cache Data and TAG memory read/write.\nThe TAG and Data memory are only updated by the cache controller.\nThere is no HW protection to prevent unauthorized access by the ARM.\nNote: When accessing the memory mapped Cache Data and TAG memory (for debugging purposes) only 32 bits access is allowed to the Cache Data memory and only 16 bits access is allowed to the Cache TAG memory."]
262    #[inline(always)]
263    pub fn cache_wen(
264        self,
265    ) -> crate::common::RegisterFieldBool<9, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
266        crate::common::RegisterFieldBool::<9,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
267    }
268
269    #[doc = "Length of QSPI FLASH cacheable memory.\nN*64 KByte. N = 0 to 512 (max. of 32 Mbyte).\nSetting CACHE_LEN=0 disables the cache.\nNote 1: The max. relevant CACHE_LEN setting depends on the chosen Flash region (program) size.\nNote 2: The first block (CACHE_LEN=1) includes the memory space specified by CACHE_FLASH_REG\\[FLASH_REGION_OFFSET\\]."]
270    #[inline(always)]
271    pub fn cache_len(
272        self,
273    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, CacheCtrl2Reg_SPEC, crate::common::RW>
274    {
275        crate::common::RegisterField::<
276            0,
277            0x1ff,
278            1,
279            0,
280            u16,
281            u16,
282            CacheCtrl2Reg_SPEC,
283            crate::common::RW,
284        >::from_register(self, 0)
285    }
286}
287impl ::core::default::Default for CacheCtrl2Reg {
288    #[inline(always)]
289    fn default() -> CacheCtrl2Reg {
290        <crate::RegValueT<CacheCtrl2Reg_SPEC> as RegisterValue<_>>::new(0)
291    }
292}
293
294#[doc(hidden)]
295#[derive(Copy, Clone, Eq, PartialEq)]
296pub struct CacheFlashReg_SPEC;
297impl crate::sealed::RegSpec for CacheFlashReg_SPEC {
298    type DataType = u32;
299}
300
301#[doc = "Cache Flash program size and base address register"]
302pub type CacheFlashReg = crate::RegValueT<CacheFlashReg_SPEC>;
303
304impl CacheFlashReg {
305    #[doc = "These bits corresponds with the Flash region base address bits \\[31:16\\].\nDefault value is \'0x1600\'.\nThe Flash region base address bits \\[31:25\\] are fixed to \'0x16\' and bits \\[17:16\\] are fixed to \'0x0\'.\nThese register bits are retained.\nNote 1: The updated value takes effect only after a software reset.\nNote 2 The Flash region base address setting depends on the chosen Flash region size."]
306    #[inline(always)]
307    pub fn flash_region_base(
308        self,
309    ) -> crate::common::RegisterField<
310        16,
311        0xffff,
312        1,
313        0,
314        u16,
315        u16,
316        CacheFlashReg_SPEC,
317        crate::common::RW,
318    > {
319        crate::common::RegisterField::<
320            16,
321            0xffff,
322            1,
323            0,
324            u16,
325            u16,
326            CacheFlashReg_SPEC,
327            crate::common::RW,
328        >::from_register(self, 0)
329    }
330
331    #[doc = "Flash region offset address (in words).\nThis value is added to the Flash (CPU) address bits \\[13:2\\].\nThese register bits are retained.\nNote 1: The updated value takes effect only after a software reset."]
332    #[inline(always)]
333    pub fn flash_region_offset(
334        self,
335    ) -> crate::common::RegisterField<4, 0xfff, 1, 0, u16, u16, CacheFlashReg_SPEC, crate::common::RW>
336    {
337        crate::common::RegisterField::<
338            4,
339            0xfff,
340            1,
341            0,
342            u16,
343            u16,
344            CacheFlashReg_SPEC,
345            crate::common::RW,
346        >::from_register(self, 0)
347    }
348
349    #[doc = "Flash region size.\nDefault value is \'6\' (0.5 MBytes).\n0 = 32 MBytes,\n1 = 16 MBytes,\n2 = 8 MBytes,\n3 = 4 MBytes,\n4 = 2 MBytes,\n5 = 1 MBytes,\n6 = 0.5 MBytes,\n7 = 0.25 MBytes.\nThese register bits are retained.\nNote 1: The updated value takes effect only after a software reset.\nNote 2: See for the max. region (program) size the memory map."]
350    #[inline(always)]
351    pub fn flash_region_size(
352        self,
353    ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, CacheFlashReg_SPEC, crate::common::RW>
354    {
355        crate::common::RegisterField::<0,0x7,1,0,u8,u8,CacheFlashReg_SPEC,crate::common::RW>::from_register(self,0)
356    }
357}
358impl ::core::default::Default for CacheFlashReg {
359    #[inline(always)]
360    fn default() -> CacheFlashReg {
361        <crate::RegValueT<CacheFlashReg_SPEC> as RegisterValue<_>>::new(369098758)
362    }
363}
364
365#[doc(hidden)]
366#[derive(Copy, Clone, Eq, PartialEq)]
367pub struct CacheLnsizecfgReg_SPEC;
368impl crate::sealed::RegSpec for CacheLnsizecfgReg_SPEC {
369    type DataType = u32;
370}
371
372#[doc = "Cache line size configuration register"]
373pub type CacheLnsizecfgReg = crate::RegValueT<CacheLnsizecfgReg_SPEC>;
374
375impl CacheLnsizecfgReg {
376    #[doc = "Cache line size:\n0: 8 bytes,\n1: 16 bytes,\n2: 32 bytes,\n3: reserved.\nNote: Flush the cache just after the dynamic (run-time) reconfiguration of the cache with an 8 bytes cache line size: write the value \"01\" into the cache control register CACHE_CTRL1_REG just after the write of the value \"00\" into the cache line size configuration register CACHE_LNSIZECFG_REG."]
377    #[inline(always)]
378    pub fn cache_line(
379        self,
380    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, CacheLnsizecfgReg_SPEC, crate::common::RW>
381    {
382        crate::common::RegisterField::<
383            0,
384            0x3,
385            1,
386            0,
387            u8,
388            u8,
389            CacheLnsizecfgReg_SPEC,
390            crate::common::RW,
391        >::from_register(self, 0)
392    }
393}
394impl ::core::default::Default for CacheLnsizecfgReg {
395    #[inline(always)]
396    fn default() -> CacheLnsizecfgReg {
397        <crate::RegValueT<CacheLnsizecfgReg_SPEC> as RegisterValue<_>>::new(0)
398    }
399}
400
401#[doc(hidden)]
402#[derive(Copy, Clone, Eq, PartialEq)]
403pub struct CacheMrmCtrlReg_SPEC;
404impl crate::sealed::RegSpec for CacheMrmCtrlReg_SPEC {
405    type DataType = u32;
406}
407
408#[doc = "Cache MRM (Miss Rate Monitor) CONTROL register"]
409pub type CacheMrmCtrlReg = crate::RegValueT<CacheMrmCtrlReg_SPEC>;
410
411impl CacheMrmCtrlReg {
412    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the number of cache hits reached the programmed threshold (threshold != 0)."]
413    #[inline(always)]
414    pub fn mrm_irq_hits_thres_status(
415        self,
416    ) -> crate::common::RegisterFieldBool<4, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
417        crate::common::RegisterFieldBool::<4,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
418    }
419
420    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the number of cache misses reached the programmed threshold (threshold != 0)."]
421    #[inline(always)]
422    pub fn mrm_irq_misses_thres_status(
423        self,
424    ) -> crate::common::RegisterFieldBool<3, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
425        crate::common::RegisterFieldBool::<3,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
426    }
427
428    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the time interval counter reached the end (time interval != 0)."]
429    #[inline(always)]
430    pub fn mrm_irq_tint_status(
431        self,
432    ) -> crate::common::RegisterFieldBool<2, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
433        crate::common::RegisterFieldBool::<2,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
434    }
435
436    #[doc = "0: Disables interrupt generation.\n1: Enables interrupt generation.\nNote: The Cache MRM generates a pulse-sensitive interrupt towards the ARM processor,"]
437    #[inline(always)]
438    pub fn mrm_irq_mask(
439        self,
440    ) -> crate::common::RegisterFieldBool<1, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
441        crate::common::RegisterFieldBool::<1,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
442    }
443
444    #[doc = "0: Freeze the \"misses/hits\" counters and reset the time interval counter to the programmed value in CACHE_MRM_TINT_REG.\n1: Enables the counters.\nNote: In case CACHE_MRM_CTRL_REG\\[MRM_START\\] is set to \'1\' and CACHE_MRM_TINT_REG (!=0) is used for the MRM interrupt generation, the time interval counter counts down (on a fixed reference clock of 16 MHz) until it\'s \'0\'. At that time CACHE_MRM_CTRL_REG\\[MRM_START\\] will be reset automatically to \'0\' by the MRM hardware and the MRM interrupt will be generated."]
445    #[inline(always)]
446    pub fn mrm_start(
447        self,
448    ) -> crate::common::RegisterFieldBool<0, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
449        crate::common::RegisterFieldBool::<0,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
450    }
451}
452impl ::core::default::Default for CacheMrmCtrlReg {
453    #[inline(always)]
454    fn default() -> CacheMrmCtrlReg {
455        <crate::RegValueT<CacheMrmCtrlReg_SPEC> as RegisterValue<_>>::new(0)
456    }
457}
458
459#[doc(hidden)]
460#[derive(Copy, Clone, Eq, PartialEq)]
461pub struct CacheMrmHitsReg_SPEC;
462impl crate::sealed::RegSpec for CacheMrmHitsReg_SPEC {
463    type DataType = u32;
464}
465
466#[doc = "Cache MRM (Miss Rate Monitor) HITS register"]
467pub type CacheMrmHitsReg = crate::RegValueT<CacheMrmHitsReg_SPEC>;
468
469impl CacheMrmHitsReg {
470    #[doc = "Contains the amount of cache hits."]
471    #[inline(always)]
472    pub fn mrm_hits(
473        self,
474    ) -> crate::common::RegisterField<
475        0,
476        0xffffffff,
477        1,
478        0,
479        u32,
480        u32,
481        CacheMrmHitsReg_SPEC,
482        crate::common::RW,
483    > {
484        crate::common::RegisterField::<
485            0,
486            0xffffffff,
487            1,
488            0,
489            u32,
490            u32,
491            CacheMrmHitsReg_SPEC,
492            crate::common::RW,
493        >::from_register(self, 0)
494    }
495}
496impl ::core::default::Default for CacheMrmHitsReg {
497    #[inline(always)]
498    fn default() -> CacheMrmHitsReg {
499        <crate::RegValueT<CacheMrmHitsReg_SPEC> as RegisterValue<_>>::new(0)
500    }
501}
502
503#[doc(hidden)]
504#[derive(Copy, Clone, Eq, PartialEq)]
505pub struct CacheMrmHitsThresReg_SPEC;
506impl crate::sealed::RegSpec for CacheMrmHitsThresReg_SPEC {
507    type DataType = u32;
508}
509
510#[doc = "Cache MRM (Miss Rate Monitor) HITS THRESHOLD register"]
511pub type CacheMrmHitsThresReg = crate::RegValueT<CacheMrmHitsThresReg_SPEC>;
512
513impl CacheMrmHitsThresReg {
514    #[doc = "Defines the hits threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_HITS_THRES_STATUS\\].\nNote: When MRM_HITS_THRES=0 (unrealistic value), no interrupt will be generated."]
515    #[inline(always)]
516    pub fn mrm_hits_thres(
517        self,
518    ) -> crate::common::RegisterField<
519        0,
520        0xffffffff,
521        1,
522        0,
523        u32,
524        u32,
525        CacheMrmHitsThresReg_SPEC,
526        crate::common::RW,
527    > {
528        crate::common::RegisterField::<
529            0,
530            0xffffffff,
531            1,
532            0,
533            u32,
534            u32,
535            CacheMrmHitsThresReg_SPEC,
536            crate::common::RW,
537        >::from_register(self, 0)
538    }
539}
540impl ::core::default::Default for CacheMrmHitsThresReg {
541    #[inline(always)]
542    fn default() -> CacheMrmHitsThresReg {
543        <crate::RegValueT<CacheMrmHitsThresReg_SPEC> as RegisterValue<_>>::new(0)
544    }
545}
546
547#[doc(hidden)]
548#[derive(Copy, Clone, Eq, PartialEq)]
549pub struct CacheMrmMissesReg_SPEC;
550impl crate::sealed::RegSpec for CacheMrmMissesReg_SPEC {
551    type DataType = u32;
552}
553
554#[doc = "Cache MRM (Miss Rate Monitor) MISSES register"]
555pub type CacheMrmMissesReg = crate::RegValueT<CacheMrmMissesReg_SPEC>;
556
557impl CacheMrmMissesReg {
558    #[doc = "Contains the amount of cache misses."]
559    #[inline(always)]
560    pub fn mrm_misses(
561        self,
562    ) -> crate::common::RegisterField<
563        0,
564        0xffffffff,
565        1,
566        0,
567        u32,
568        u32,
569        CacheMrmMissesReg_SPEC,
570        crate::common::RW,
571    > {
572        crate::common::RegisterField::<
573            0,
574            0xffffffff,
575            1,
576            0,
577            u32,
578            u32,
579            CacheMrmMissesReg_SPEC,
580            crate::common::RW,
581        >::from_register(self, 0)
582    }
583}
584impl ::core::default::Default for CacheMrmMissesReg {
585    #[inline(always)]
586    fn default() -> CacheMrmMissesReg {
587        <crate::RegValueT<CacheMrmMissesReg_SPEC> as RegisterValue<_>>::new(0)
588    }
589}
590
591#[doc(hidden)]
592#[derive(Copy, Clone, Eq, PartialEq)]
593pub struct CacheMrmMissesThresReg_SPEC;
594impl crate::sealed::RegSpec for CacheMrmMissesThresReg_SPEC {
595    type DataType = u32;
596}
597
598#[doc = "Cache MRM (Miss Rate Monitor) THRESHOLD register"]
599pub type CacheMrmMissesThresReg = crate::RegValueT<CacheMrmMissesThresReg_SPEC>;
600
601impl CacheMrmMissesThresReg {
602    #[doc = "Defines the misses threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_MISSES_THRES_STATUS\\].\nNote: When MRM_MISSES_THRES=0 (unrealistic value), no interrupt will be generated."]
603    #[inline(always)]
604    pub fn mrm_misses_thres(
605        self,
606    ) -> crate::common::RegisterField<
607        0,
608        0xffffffff,
609        1,
610        0,
611        u32,
612        u32,
613        CacheMrmMissesThresReg_SPEC,
614        crate::common::RW,
615    > {
616        crate::common::RegisterField::<
617            0,
618            0xffffffff,
619            1,
620            0,
621            u32,
622            u32,
623            CacheMrmMissesThresReg_SPEC,
624            crate::common::RW,
625        >::from_register(self, 0)
626    }
627}
628impl ::core::default::Default for CacheMrmMissesThresReg {
629    #[inline(always)]
630    fn default() -> CacheMrmMissesThresReg {
631        <crate::RegValueT<CacheMrmMissesThresReg_SPEC> as RegisterValue<_>>::new(0)
632    }
633}
634
635#[doc(hidden)]
636#[derive(Copy, Clone, Eq, PartialEq)]
637pub struct CacheMrmTintReg_SPEC;
638impl crate::sealed::RegSpec for CacheMrmTintReg_SPEC {
639    type DataType = u32;
640}
641
642#[doc = "Cache MRM (Miss Rate Monitor) TIME INTERVAL register"]
643pub type CacheMrmTintReg = crate::RegValueT<CacheMrmTintReg_SPEC>;
644
645impl CacheMrmTintReg {
646    #[doc = "Defines the time interval for the monitoring in 32 MHz clock cycles. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_TINT_STATUS\\].\nNote: When MRM_TINT=0 (unrealistic value), no interrupt will be generated."]
647    #[inline(always)]
648    pub fn mrm_tint(
649        self,
650    ) -> crate::common::RegisterField<
651        0,
652        0x7ffff,
653        1,
654        0,
655        u32,
656        u32,
657        CacheMrmTintReg_SPEC,
658        crate::common::RW,
659    > {
660        crate::common::RegisterField::<
661            0,
662            0x7ffff,
663            1,
664            0,
665            u32,
666            u32,
667            CacheMrmTintReg_SPEC,
668            crate::common::RW,
669        >::from_register(self, 0)
670    }
671}
672impl ::core::default::Default for CacheMrmTintReg {
673    #[inline(always)]
674    fn default() -> CacheMrmTintReg {
675        <crate::RegValueT<CacheMrmTintReg_SPEC> as RegisterValue<_>>::new(0)
676    }
677}
678
679#[doc(hidden)]
680#[derive(Copy, Clone, Eq, PartialEq)]
681pub struct SwdResetReg_SPEC;
682impl crate::sealed::RegSpec for SwdResetReg_SPEC {
683    type DataType = u32;
684}
685
686#[doc = "SWD HW reset control register"]
687pub type SwdResetReg = crate::RegValueT<SwdResetReg_SPEC>;
688
689impl SwdResetReg {
690    #[doc = "0: default.\n1: HW reset request (from the debugger tool). The register is automatically reset with a HW_RESET.\nThis bit can only be accessed by the debugger software and not by the application."]
691    #[inline(always)]
692    pub fn swd_hw_reset_req(
693        self,
694    ) -> crate::common::RegisterFieldBool<0, 1, 0, SwdResetReg_SPEC, crate::common::W> {
695        crate::common::RegisterFieldBool::<0,1,0,SwdResetReg_SPEC,crate::common::W>::from_register(self,0)
696    }
697}
698impl ::core::default::Default for SwdResetReg {
699    #[inline(always)]
700    fn default() -> SwdResetReg {
701        <crate::RegValueT<SwdResetReg_SPEC> as RegisterValue<_>>::new(0)
702    }
703}
da14697_pac/cache.rs

da14697_pac/
cache.rs
