da14697_pac/
pdc.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:38 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"PDC registers"]
28unsafe impl ::core::marker::Send for super::Pdc {}
29unsafe impl ::core::marker::Sync for super::Pdc {}
30impl super::Pdc {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Clear a pending PDC bit"]
38    #[inline(always)]
39    pub const fn pdc_acknowledge_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::PdcAcknowledgeReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::PdcAcknowledgeReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(128usize),
45            )
46        }
47    }
48
49    #[doc = "PDC control register"]
50    #[inline(always)]
51    pub const fn pdc_ctrl0_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::PdcCtrl0Reg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::PdcCtrl0Reg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0usize),
57            )
58        }
59    }
60
61    #[doc = "PDC control register"]
62    #[inline(always)]
63    pub const fn pdc_ctrl10_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::PdcCtrl10Reg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::PdcCtrl10Reg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(40usize),
69            )
70        }
71    }
72
73    #[doc = "PDC control register"]
74    #[inline(always)]
75    pub const fn pdc_ctrl11_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::PdcCtrl11Reg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::PdcCtrl11Reg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(44usize),
81            )
82        }
83    }
84
85    #[doc = "PDC control register"]
86    #[inline(always)]
87    pub const fn pdc_ctrl12_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::PdcCtrl12Reg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::PdcCtrl12Reg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(48usize),
93            )
94        }
95    }
96
97    #[doc = "PDC control register"]
98    #[inline(always)]
99    pub const fn pdc_ctrl13_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::PdcCtrl13Reg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::PdcCtrl13Reg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(52usize),
105            )
106        }
107    }
108
109    #[doc = "PDC control register"]
110    #[inline(always)]
111    pub const fn pdc_ctrl14_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::PdcCtrl14Reg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::PdcCtrl14Reg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(56usize),
117            )
118        }
119    }
120
121    #[doc = "PDC control register"]
122    #[inline(always)]
123    pub const fn pdc_ctrl15_reg(
124        &self,
125    ) -> &'static crate::common::Reg<self::PdcCtrl15Reg_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::PdcCtrl15Reg_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(60usize),
129            )
130        }
131    }
132
133    #[doc = "PDC control register"]
134    #[inline(always)]
135    pub const fn pdc_ctrl1_reg(
136        &self,
137    ) -> &'static crate::common::Reg<self::PdcCtrl1Reg_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::PdcCtrl1Reg_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(4usize),
141            )
142        }
143    }
144
145    #[doc = "PDC control register"]
146    #[inline(always)]
147    pub const fn pdc_ctrl2_reg(
148        &self,
149    ) -> &'static crate::common::Reg<self::PdcCtrl2Reg_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::PdcCtrl2Reg_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(8usize),
153            )
154        }
155    }
156
157    #[doc = "PDC control register"]
158    #[inline(always)]
159    pub const fn pdc_ctrl3_reg(
160        &self,
161    ) -> &'static crate::common::Reg<self::PdcCtrl3Reg_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::PdcCtrl3Reg_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(12usize),
165            )
166        }
167    }
168
169    #[doc = "PDC control register"]
170    #[inline(always)]
171    pub const fn pdc_ctrl4_reg(
172        &self,
173    ) -> &'static crate::common::Reg<self::PdcCtrl4Reg_SPEC, crate::common::RW> {
174        unsafe {
175            crate::common::Reg::<self::PdcCtrl4Reg_SPEC, crate::common::RW>::from_ptr(
176                self._svd2pac_as_ptr().add(16usize),
177            )
178        }
179    }
180
181    #[doc = "PDC control register"]
182    #[inline(always)]
183    pub const fn pdc_ctrl5_reg(
184        &self,
185    ) -> &'static crate::common::Reg<self::PdcCtrl5Reg_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::PdcCtrl5Reg_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(20usize),
189            )
190        }
191    }
192
193    #[doc = "PDC control register"]
194    #[inline(always)]
195    pub const fn pdc_ctrl6_reg(
196        &self,
197    ) -> &'static crate::common::Reg<self::PdcCtrl6Reg_SPEC, crate::common::RW> {
198        unsafe {
199            crate::common::Reg::<self::PdcCtrl6Reg_SPEC, crate::common::RW>::from_ptr(
200                self._svd2pac_as_ptr().add(24usize),
201            )
202        }
203    }
204
205    #[doc = "PDC control register"]
206    #[inline(always)]
207    pub const fn pdc_ctrl7_reg(
208        &self,
209    ) -> &'static crate::common::Reg<self::PdcCtrl7Reg_SPEC, crate::common::RW> {
210        unsafe {
211            crate::common::Reg::<self::PdcCtrl7Reg_SPEC, crate::common::RW>::from_ptr(
212                self._svd2pac_as_ptr().add(28usize),
213            )
214        }
215    }
216
217    #[doc = "PDC control register"]
218    #[inline(always)]
219    pub const fn pdc_ctrl8_reg(
220        &self,
221    ) -> &'static crate::common::Reg<self::PdcCtrl8Reg_SPEC, crate::common::RW> {
222        unsafe {
223            crate::common::Reg::<self::PdcCtrl8Reg_SPEC, crate::common::RW>::from_ptr(
224                self._svd2pac_as_ptr().add(32usize),
225            )
226        }
227    }
228
229    #[doc = "PDC control register"]
230    #[inline(always)]
231    pub const fn pdc_ctrl9_reg(
232        &self,
233    ) -> &'static crate::common::Reg<self::PdcCtrl9Reg_SPEC, crate::common::RW> {
234        unsafe {
235            crate::common::Reg::<self::PdcCtrl9Reg_SPEC, crate::common::RW>::from_ptr(
236                self._svd2pac_as_ptr().add(36usize),
237            )
238        }
239    }
240
241    #[doc = "Shows any pending IRQ to CM33"]
242    #[inline(always)]
243    pub const fn pdc_pending_cm33_reg(
244        &self,
245    ) -> &'static crate::common::Reg<self::PdcPendingCm33Reg_SPEC, crate::common::RW> {
246        unsafe {
247            crate::common::Reg::<self::PdcPendingCm33Reg_SPEC, crate::common::RW>::from_ptr(
248                self._svd2pac_as_ptr().add(140usize),
249            )
250        }
251    }
252
253    #[doc = "Shows any pending IRQ to CM33"]
254    #[inline(always)]
255    pub const fn pdc_pending_cmac_reg(
256        &self,
257    ) -> &'static crate::common::Reg<self::PdcPendingCmacReg_SPEC, crate::common::RW> {
258        unsafe {
259            crate::common::Reg::<self::PdcPendingCmacReg_SPEC, crate::common::RW>::from_ptr(
260                self._svd2pac_as_ptr().add(144usize),
261            )
262        }
263    }
264
265    #[doc = "Shows any pending wakup event"]
266    #[inline(always)]
267    pub const fn pdc_pending_reg(
268        &self,
269    ) -> &'static crate::common::Reg<self::PdcPendingReg_SPEC, crate::common::RW> {
270        unsafe {
271            crate::common::Reg::<self::PdcPendingReg_SPEC, crate::common::RW>::from_ptr(
272                self._svd2pac_as_ptr().add(132usize),
273            )
274        }
275    }
276
277    #[doc = "Shows any pending IRQ to SNC"]
278    #[inline(always)]
279    pub const fn pdc_pending_snc_reg(
280        &self,
281    ) -> &'static crate::common::Reg<self::PdcPendingSncReg_SPEC, crate::common::RW> {
282        unsafe {
283            crate::common::Reg::<self::PdcPendingSncReg_SPEC, crate::common::RW>::from_ptr(
284                self._svd2pac_as_ptr().add(136usize),
285            )
286        }
287    }
288
289    #[doc = "Set a pending PDC bit"]
290    #[inline(always)]
291    pub const fn pdc_set_pending_reg(
292        &self,
293    ) -> &'static crate::common::Reg<self::PdcSetPendingReg_SPEC, crate::common::RW> {
294        unsafe {
295            crate::common::Reg::<self::PdcSetPendingReg_SPEC, crate::common::RW>::from_ptr(
296                self._svd2pac_as_ptr().add(148usize),
297            )
298        }
299    }
300}
301#[doc(hidden)]
302#[derive(Copy, Clone, Eq, PartialEq)]
303pub struct PdcAcknowledgeReg_SPEC;
304impl crate::sealed::RegSpec for PdcAcknowledgeReg_SPEC {
305    type DataType = u32;
306}
307
308#[doc = "Clear a pending PDC bit"]
309pub type PdcAcknowledgeReg = crate::RegValueT<PdcAcknowledgeReg_SPEC>;
310
311impl PdcAcknowledgeReg {
312    #[doc = "Writing to this field acknowledges the PDC IRQ request.\nThe data controls which request is acknowledged"]
313    #[inline(always)]
314    pub fn pdc_acknowledge(
315        self,
316    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, PdcAcknowledgeReg_SPEC, crate::common::W>
317    {
318        crate::common::RegisterField::<
319            0,
320            0x1f,
321            1,
322            0,
323            u8,
324            u8,
325            PdcAcknowledgeReg_SPEC,
326            crate::common::W,
327        >::from_register(self, 0)
328    }
329}
330impl ::core::default::Default for PdcAcknowledgeReg {
331    #[inline(always)]
332    fn default() -> PdcAcknowledgeReg {
333        <crate::RegValueT<PdcAcknowledgeReg_SPEC> as RegisterValue<_>>::new(0)
334    }
335}
336
337#[doc(hidden)]
338#[derive(Copy, Clone, Eq, PartialEq)]
339pub struct PdcCtrl0Reg_SPEC;
340impl crate::sealed::RegSpec for PdcCtrl0Reg_SPEC {
341    type DataType = u32;
342}
343
344#[doc = "PDC control register"]
345pub type PdcCtrl0Reg = crate::RegValueT<PdcCtrl0Reg_SPEC>;
346
347impl PdcCtrl0Reg {
348    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
349    #[inline(always)]
350    pub fn pdc_master(
351        self,
352    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl0Reg_SPEC, crate::common::RW>
353    {
354        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl0Reg_SPEC,crate::common::RW>::from_register(self,0)
355    }
356
357    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
358    #[inline(always)]
359    pub fn en_com(
360        self,
361    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl0Reg_SPEC, crate::common::RW> {
362        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl0Reg_SPEC,crate::common::RW>::from_register(self,0)
363    }
364
365    #[doc = "If set, enables PD_PER"]
366    #[inline(always)]
367    pub fn en_per(
368        self,
369    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl0Reg_SPEC, crate::common::RW> {
370        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl0Reg_SPEC,crate::common::RW>::from_register(self,0)
371    }
372
373    #[doc = "If set, enables PD_TMR"]
374    #[inline(always)]
375    pub fn en_tmr(
376        self,
377    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl0Reg_SPEC, crate::common::RW> {
378        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl0Reg_SPEC,crate::common::RW>::from_register(self,0)
379    }
380
381    #[doc = "If set, the XTAL32M will be started"]
382    #[inline(always)]
383    pub fn en_xtal(
384        self,
385    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl0Reg_SPEC, crate::common::RW> {
386        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl0Reg_SPEC,crate::common::RW>::from_register(self,0)
387    }
388
389    #[doc = "Selects which individual bit from the selected bank is used for wakup.\nFor the peripheral banks, selected with TRIG_SELECT = 0x2 or 0x3, only the lower 4 bits are considered."]
390    #[inline(always)]
391    pub fn trig_id(
392        self,
393    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl0Reg_SPEC, crate::common::RW>
394    {
395        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl0Reg_SPEC,crate::common::RW>::from_register(self,0)
396    }
397
398    #[doc = "Selects which bank is used as wakeup trigger\nWhen TRIG_SELECT is 0x0, selects GPIO port0 through the WAKEUP block.\nWhen TRIG_SELECT is 0x1, selects GPIO port1 through the WAKEUP block.\nWhen TRIG_SELECT is 0x2 or 0x3, selects the peripheral IRQ.\n\nperipheral IRQ table:\n0x0: Timer\n0x1: Timer2\n0x2: Timer3\n0x3: Timer4\n0x4: RTC Alarm/Rollover\n0x5: RTC Timer\n0x6: CMAC Timer OR wake up from CMAC debugger\n0x7: Motor Controller\n0x8: XTAL32MRDY_IRQ\n0x9: RFDIAG_IRQ\n0xA: CMAC2SYS_IRQ OR VBUS Present IRQ OR JTAG present OR Debounced IO\n0xB: Sensor Node Controller\n0xC to 0xE: reserved\n0xF: Software trigger only"]
399    #[inline(always)]
400    pub fn trig_select(
401        self,
402    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl0Reg_SPEC, crate::common::RW>
403    {
404        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl0Reg_SPEC,crate::common::RW>::from_register(self,0)
405    }
406}
407impl ::core::default::Default for PdcCtrl0Reg {
408    #[inline(always)]
409    fn default() -> PdcCtrl0Reg {
410        <crate::RegValueT<PdcCtrl0Reg_SPEC> as RegisterValue<_>>::new(0)
411    }
412}
413
414#[doc(hidden)]
415#[derive(Copy, Clone, Eq, PartialEq)]
416pub struct PdcCtrl10Reg_SPEC;
417impl crate::sealed::RegSpec for PdcCtrl10Reg_SPEC {
418    type DataType = u32;
419}
420
421#[doc = "PDC control register"]
422pub type PdcCtrl10Reg = crate::RegValueT<PdcCtrl10Reg_SPEC>;
423
424impl PdcCtrl10Reg {
425    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
426    #[inline(always)]
427    pub fn pdc_master(
428        self,
429    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl10Reg_SPEC, crate::common::RW>
430    {
431        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl10Reg_SPEC,crate::common::RW>::from_register(self,0)
432    }
433
434    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
435    #[inline(always)]
436    pub fn en_com(
437        self,
438    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl10Reg_SPEC, crate::common::RW> {
439        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl10Reg_SPEC,crate::common::RW>::from_register(self,0)
440    }
441
442    #[doc = "If set, enables PD_PER"]
443    #[inline(always)]
444    pub fn en_per(
445        self,
446    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl10Reg_SPEC, crate::common::RW> {
447        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl10Reg_SPEC,crate::common::RW>::from_register(self,0)
448    }
449
450    #[doc = "If set, enables PD_TMR"]
451    #[inline(always)]
452    pub fn en_tmr(
453        self,
454    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl10Reg_SPEC, crate::common::RW> {
455        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl10Reg_SPEC,crate::common::RW>::from_register(self,0)
456    }
457
458    #[doc = "If set, the XTAL32M will be started"]
459    #[inline(always)]
460    pub fn en_xtal(
461        self,
462    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl10Reg_SPEC, crate::common::RW> {
463        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl10Reg_SPEC,crate::common::RW>::from_register(self,0)
464    }
465
466    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
467    #[inline(always)]
468    pub fn trig_id(
469        self,
470    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl10Reg_SPEC, crate::common::RW>
471    {
472        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl10Reg_SPEC,crate::common::RW>::from_register(self,0)
473    }
474
475    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
476    #[inline(always)]
477    pub fn trig_select(
478        self,
479    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl10Reg_SPEC, crate::common::RW>
480    {
481        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl10Reg_SPEC,crate::common::RW>::from_register(self,0)
482    }
483}
484impl ::core::default::Default for PdcCtrl10Reg {
485    #[inline(always)]
486    fn default() -> PdcCtrl10Reg {
487        <crate::RegValueT<PdcCtrl10Reg_SPEC> as RegisterValue<_>>::new(0)
488    }
489}
490
491#[doc(hidden)]
492#[derive(Copy, Clone, Eq, PartialEq)]
493pub struct PdcCtrl11Reg_SPEC;
494impl crate::sealed::RegSpec for PdcCtrl11Reg_SPEC {
495    type DataType = u32;
496}
497
498#[doc = "PDC control register"]
499pub type PdcCtrl11Reg = crate::RegValueT<PdcCtrl11Reg_SPEC>;
500
501impl PdcCtrl11Reg {
502    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
503    #[inline(always)]
504    pub fn pdc_master(
505        self,
506    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl11Reg_SPEC, crate::common::RW>
507    {
508        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl11Reg_SPEC,crate::common::RW>::from_register(self,0)
509    }
510
511    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
512    #[inline(always)]
513    pub fn en_com(
514        self,
515    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl11Reg_SPEC, crate::common::RW> {
516        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl11Reg_SPEC,crate::common::RW>::from_register(self,0)
517    }
518
519    #[doc = "If set, enables PD_PER"]
520    #[inline(always)]
521    pub fn en_per(
522        self,
523    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl11Reg_SPEC, crate::common::RW> {
524        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl11Reg_SPEC,crate::common::RW>::from_register(self,0)
525    }
526
527    #[doc = "If set, enables PD_TMR"]
528    #[inline(always)]
529    pub fn en_tmr(
530        self,
531    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl11Reg_SPEC, crate::common::RW> {
532        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl11Reg_SPEC,crate::common::RW>::from_register(self,0)
533    }
534
535    #[doc = "If set, the XTAL32M will be started"]
536    #[inline(always)]
537    pub fn en_xtal(
538        self,
539    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl11Reg_SPEC, crate::common::RW> {
540        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl11Reg_SPEC,crate::common::RW>::from_register(self,0)
541    }
542
543    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
544    #[inline(always)]
545    pub fn trig_id(
546        self,
547    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl11Reg_SPEC, crate::common::RW>
548    {
549        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl11Reg_SPEC,crate::common::RW>::from_register(self,0)
550    }
551
552    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
553    #[inline(always)]
554    pub fn trig_select(
555        self,
556    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl11Reg_SPEC, crate::common::RW>
557    {
558        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl11Reg_SPEC,crate::common::RW>::from_register(self,0)
559    }
560}
561impl ::core::default::Default for PdcCtrl11Reg {
562    #[inline(always)]
563    fn default() -> PdcCtrl11Reg {
564        <crate::RegValueT<PdcCtrl11Reg_SPEC> as RegisterValue<_>>::new(0)
565    }
566}
567
568#[doc(hidden)]
569#[derive(Copy, Clone, Eq, PartialEq)]
570pub struct PdcCtrl12Reg_SPEC;
571impl crate::sealed::RegSpec for PdcCtrl12Reg_SPEC {
572    type DataType = u32;
573}
574
575#[doc = "PDC control register"]
576pub type PdcCtrl12Reg = crate::RegValueT<PdcCtrl12Reg_SPEC>;
577
578impl PdcCtrl12Reg {
579    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
580    #[inline(always)]
581    pub fn pdc_master(
582        self,
583    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl12Reg_SPEC, crate::common::RW>
584    {
585        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl12Reg_SPEC,crate::common::RW>::from_register(self,0)
586    }
587
588    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
589    #[inline(always)]
590    pub fn en_com(
591        self,
592    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl12Reg_SPEC, crate::common::RW> {
593        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl12Reg_SPEC,crate::common::RW>::from_register(self,0)
594    }
595
596    #[doc = "If set, enables PD_PER"]
597    #[inline(always)]
598    pub fn en_per(
599        self,
600    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl12Reg_SPEC, crate::common::RW> {
601        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl12Reg_SPEC,crate::common::RW>::from_register(self,0)
602    }
603
604    #[doc = "If set, enables PD_TMR"]
605    #[inline(always)]
606    pub fn en_tmr(
607        self,
608    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl12Reg_SPEC, crate::common::RW> {
609        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl12Reg_SPEC,crate::common::RW>::from_register(self,0)
610    }
611
612    #[doc = "If set, the XTAL32M will be started"]
613    #[inline(always)]
614    pub fn en_xtal(
615        self,
616    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl12Reg_SPEC, crate::common::RW> {
617        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl12Reg_SPEC,crate::common::RW>::from_register(self,0)
618    }
619
620    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
621    #[inline(always)]
622    pub fn trig_id(
623        self,
624    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl12Reg_SPEC, crate::common::RW>
625    {
626        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl12Reg_SPEC,crate::common::RW>::from_register(self,0)
627    }
628
629    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
630    #[inline(always)]
631    pub fn trig_select(
632        self,
633    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl12Reg_SPEC, crate::common::RW>
634    {
635        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl12Reg_SPEC,crate::common::RW>::from_register(self,0)
636    }
637}
638impl ::core::default::Default for PdcCtrl12Reg {
639    #[inline(always)]
640    fn default() -> PdcCtrl12Reg {
641        <crate::RegValueT<PdcCtrl12Reg_SPEC> as RegisterValue<_>>::new(0)
642    }
643}
644
645#[doc(hidden)]
646#[derive(Copy, Clone, Eq, PartialEq)]
647pub struct PdcCtrl13Reg_SPEC;
648impl crate::sealed::RegSpec for PdcCtrl13Reg_SPEC {
649    type DataType = u32;
650}
651
652#[doc = "PDC control register"]
653pub type PdcCtrl13Reg = crate::RegValueT<PdcCtrl13Reg_SPEC>;
654
655impl PdcCtrl13Reg {
656    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
657    #[inline(always)]
658    pub fn pdc_master(
659        self,
660    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl13Reg_SPEC, crate::common::RW>
661    {
662        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl13Reg_SPEC,crate::common::RW>::from_register(self,0)
663    }
664
665    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
666    #[inline(always)]
667    pub fn en_com(
668        self,
669    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl13Reg_SPEC, crate::common::RW> {
670        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl13Reg_SPEC,crate::common::RW>::from_register(self,0)
671    }
672
673    #[doc = "If set, enables PD_PER"]
674    #[inline(always)]
675    pub fn en_per(
676        self,
677    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl13Reg_SPEC, crate::common::RW> {
678        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl13Reg_SPEC,crate::common::RW>::from_register(self,0)
679    }
680
681    #[doc = "If set, enables PD_TMR"]
682    #[inline(always)]
683    pub fn en_tmr(
684        self,
685    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl13Reg_SPEC, crate::common::RW> {
686        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl13Reg_SPEC,crate::common::RW>::from_register(self,0)
687    }
688
689    #[doc = "If set, the XTAL32M will be started"]
690    #[inline(always)]
691    pub fn en_xtal(
692        self,
693    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl13Reg_SPEC, crate::common::RW> {
694        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl13Reg_SPEC,crate::common::RW>::from_register(self,0)
695    }
696
697    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
698    #[inline(always)]
699    pub fn trig_id(
700        self,
701    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl13Reg_SPEC, crate::common::RW>
702    {
703        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl13Reg_SPEC,crate::common::RW>::from_register(self,0)
704    }
705
706    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
707    #[inline(always)]
708    pub fn trig_select(
709        self,
710    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl13Reg_SPEC, crate::common::RW>
711    {
712        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl13Reg_SPEC,crate::common::RW>::from_register(self,0)
713    }
714}
715impl ::core::default::Default for PdcCtrl13Reg {
716    #[inline(always)]
717    fn default() -> PdcCtrl13Reg {
718        <crate::RegValueT<PdcCtrl13Reg_SPEC> as RegisterValue<_>>::new(0)
719    }
720}
721
722#[doc(hidden)]
723#[derive(Copy, Clone, Eq, PartialEq)]
724pub struct PdcCtrl14Reg_SPEC;
725impl crate::sealed::RegSpec for PdcCtrl14Reg_SPEC {
726    type DataType = u32;
727}
728
729#[doc = "PDC control register"]
730pub type PdcCtrl14Reg = crate::RegValueT<PdcCtrl14Reg_SPEC>;
731
732impl PdcCtrl14Reg {
733    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
734    #[inline(always)]
735    pub fn pdc_master(
736        self,
737    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl14Reg_SPEC, crate::common::RW>
738    {
739        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl14Reg_SPEC,crate::common::RW>::from_register(self,0)
740    }
741
742    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
743    #[inline(always)]
744    pub fn en_com(
745        self,
746    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl14Reg_SPEC, crate::common::RW> {
747        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl14Reg_SPEC,crate::common::RW>::from_register(self,0)
748    }
749
750    #[doc = "If set, enables PD_PER"]
751    #[inline(always)]
752    pub fn en_per(
753        self,
754    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl14Reg_SPEC, crate::common::RW> {
755        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl14Reg_SPEC,crate::common::RW>::from_register(self,0)
756    }
757
758    #[doc = "If set, enables PD_TMR"]
759    #[inline(always)]
760    pub fn en_tmr(
761        self,
762    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl14Reg_SPEC, crate::common::RW> {
763        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl14Reg_SPEC,crate::common::RW>::from_register(self,0)
764    }
765
766    #[doc = "If set, the XTAL32M will be started"]
767    #[inline(always)]
768    pub fn en_xtal(
769        self,
770    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl14Reg_SPEC, crate::common::RW> {
771        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl14Reg_SPEC,crate::common::RW>::from_register(self,0)
772    }
773
774    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
775    #[inline(always)]
776    pub fn trig_id(
777        self,
778    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl14Reg_SPEC, crate::common::RW>
779    {
780        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl14Reg_SPEC,crate::common::RW>::from_register(self,0)
781    }
782
783    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
784    #[inline(always)]
785    pub fn trig_select(
786        self,
787    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl14Reg_SPEC, crate::common::RW>
788    {
789        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl14Reg_SPEC,crate::common::RW>::from_register(self,0)
790    }
791}
792impl ::core::default::Default for PdcCtrl14Reg {
793    #[inline(always)]
794    fn default() -> PdcCtrl14Reg {
795        <crate::RegValueT<PdcCtrl14Reg_SPEC> as RegisterValue<_>>::new(0)
796    }
797}
798
799#[doc(hidden)]
800#[derive(Copy, Clone, Eq, PartialEq)]
801pub struct PdcCtrl15Reg_SPEC;
802impl crate::sealed::RegSpec for PdcCtrl15Reg_SPEC {
803    type DataType = u32;
804}
805
806#[doc = "PDC control register"]
807pub type PdcCtrl15Reg = crate::RegValueT<PdcCtrl15Reg_SPEC>;
808
809impl PdcCtrl15Reg {
810    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
811    #[inline(always)]
812    pub fn pdc_master(
813        self,
814    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl15Reg_SPEC, crate::common::RW>
815    {
816        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl15Reg_SPEC,crate::common::RW>::from_register(self,0)
817    }
818
819    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
820    #[inline(always)]
821    pub fn en_com(
822        self,
823    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl15Reg_SPEC, crate::common::RW> {
824        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl15Reg_SPEC,crate::common::RW>::from_register(self,0)
825    }
826
827    #[doc = "If set, enables PD_PER"]
828    #[inline(always)]
829    pub fn en_per(
830        self,
831    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl15Reg_SPEC, crate::common::RW> {
832        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl15Reg_SPEC,crate::common::RW>::from_register(self,0)
833    }
834
835    #[doc = "If set, enables PD_TMR"]
836    #[inline(always)]
837    pub fn en_tmr(
838        self,
839    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl15Reg_SPEC, crate::common::RW> {
840        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl15Reg_SPEC,crate::common::RW>::from_register(self,0)
841    }
842
843    #[doc = "If set, the XTAL32M will be started"]
844    #[inline(always)]
845    pub fn en_xtal(
846        self,
847    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl15Reg_SPEC, crate::common::RW> {
848        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl15Reg_SPEC,crate::common::RW>::from_register(self,0)
849    }
850
851    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
852    #[inline(always)]
853    pub fn trig_id(
854        self,
855    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl15Reg_SPEC, crate::common::RW>
856    {
857        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl15Reg_SPEC,crate::common::RW>::from_register(self,0)
858    }
859
860    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
861    #[inline(always)]
862    pub fn trig_select(
863        self,
864    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl15Reg_SPEC, crate::common::RW>
865    {
866        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl15Reg_SPEC,crate::common::RW>::from_register(self,0)
867    }
868}
869impl ::core::default::Default for PdcCtrl15Reg {
870    #[inline(always)]
871    fn default() -> PdcCtrl15Reg {
872        <crate::RegValueT<PdcCtrl15Reg_SPEC> as RegisterValue<_>>::new(0)
873    }
874}
875
876#[doc(hidden)]
877#[derive(Copy, Clone, Eq, PartialEq)]
878pub struct PdcCtrl1Reg_SPEC;
879impl crate::sealed::RegSpec for PdcCtrl1Reg_SPEC {
880    type DataType = u32;
881}
882
883#[doc = "PDC control register"]
884pub type PdcCtrl1Reg = crate::RegValueT<PdcCtrl1Reg_SPEC>;
885
886impl PdcCtrl1Reg {
887    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
888    #[inline(always)]
889    pub fn pdc_master(
890        self,
891    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl1Reg_SPEC, crate::common::RW>
892    {
893        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
894    }
895
896    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
897    #[inline(always)]
898    pub fn en_com(
899        self,
900    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl1Reg_SPEC, crate::common::RW> {
901        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
902    }
903
904    #[doc = "If set, enables PD_PER"]
905    #[inline(always)]
906    pub fn en_per(
907        self,
908    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl1Reg_SPEC, crate::common::RW> {
909        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
910    }
911
912    #[doc = "If set, enables PD_TMR"]
913    #[inline(always)]
914    pub fn en_tmr(
915        self,
916    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl1Reg_SPEC, crate::common::RW> {
917        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
918    }
919
920    #[doc = "If set, the XTAL32M will be started"]
921    #[inline(always)]
922    pub fn en_xtal(
923        self,
924    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl1Reg_SPEC, crate::common::RW> {
925        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
926    }
927
928    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
929    #[inline(always)]
930    pub fn trig_id(
931        self,
932    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl1Reg_SPEC, crate::common::RW>
933    {
934        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
935    }
936
937    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
938    #[inline(always)]
939    pub fn trig_select(
940        self,
941    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl1Reg_SPEC, crate::common::RW>
942    {
943        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
944    }
945}
946impl ::core::default::Default for PdcCtrl1Reg {
947    #[inline(always)]
948    fn default() -> PdcCtrl1Reg {
949        <crate::RegValueT<PdcCtrl1Reg_SPEC> as RegisterValue<_>>::new(0)
950    }
951}
952
953#[doc(hidden)]
954#[derive(Copy, Clone, Eq, PartialEq)]
955pub struct PdcCtrl2Reg_SPEC;
956impl crate::sealed::RegSpec for PdcCtrl2Reg_SPEC {
957    type DataType = u32;
958}
959
960#[doc = "PDC control register"]
961pub type PdcCtrl2Reg = crate::RegValueT<PdcCtrl2Reg_SPEC>;
962
963impl PdcCtrl2Reg {
964    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
965    #[inline(always)]
966    pub fn pdc_master(
967        self,
968    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl2Reg_SPEC, crate::common::RW>
969    {
970        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
971    }
972
973    #[doc = "IIf set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
974    #[inline(always)]
975    pub fn en_com(
976        self,
977    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl2Reg_SPEC, crate::common::RW> {
978        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
979    }
980
981    #[doc = "If set, enables PD_PER"]
982    #[inline(always)]
983    pub fn en_per(
984        self,
985    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl2Reg_SPEC, crate::common::RW> {
986        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
987    }
988
989    #[doc = "If set, enables PD_TMR"]
990    #[inline(always)]
991    pub fn en_tmr(
992        self,
993    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl2Reg_SPEC, crate::common::RW> {
994        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
995    }
996
997    #[doc = "If set, the XTAL32M will be started"]
998    #[inline(always)]
999    pub fn en_xtal(
1000        self,
1001    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl2Reg_SPEC, crate::common::RW> {
1002        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
1003    }
1004
1005    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
1006    #[inline(always)]
1007    pub fn trig_id(
1008        self,
1009    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl2Reg_SPEC, crate::common::RW>
1010    {
1011        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
1012    }
1013
1014    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
1015    #[inline(always)]
1016    pub fn trig_select(
1017        self,
1018    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl2Reg_SPEC, crate::common::RW>
1019    {
1020        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
1021    }
1022}
1023impl ::core::default::Default for PdcCtrl2Reg {
1024    #[inline(always)]
1025    fn default() -> PdcCtrl2Reg {
1026        <crate::RegValueT<PdcCtrl2Reg_SPEC> as RegisterValue<_>>::new(0)
1027    }
1028}
1029
1030#[doc(hidden)]
1031#[derive(Copy, Clone, Eq, PartialEq)]
1032pub struct PdcCtrl3Reg_SPEC;
1033impl crate::sealed::RegSpec for PdcCtrl3Reg_SPEC {
1034    type DataType = u32;
1035}
1036
1037#[doc = "PDC control register"]
1038pub type PdcCtrl3Reg = crate::RegValueT<PdcCtrl3Reg_SPEC>;
1039
1040impl PdcCtrl3Reg {
1041    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
1042    #[inline(always)]
1043    pub fn pdc_master(
1044        self,
1045    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl3Reg_SPEC, crate::common::RW>
1046    {
1047        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
1048    }
1049
1050    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
1051    #[inline(always)]
1052    pub fn en_com(
1053        self,
1054    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl3Reg_SPEC, crate::common::RW> {
1055        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
1056    }
1057
1058    #[doc = "If set, enables PD_PER"]
1059    #[inline(always)]
1060    pub fn en_per(
1061        self,
1062    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl3Reg_SPEC, crate::common::RW> {
1063        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
1064    }
1065
1066    #[doc = "If set, enables PD_TMR"]
1067    #[inline(always)]
1068    pub fn en_tmr(
1069        self,
1070    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl3Reg_SPEC, crate::common::RW> {
1071        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
1072    }
1073
1074    #[doc = "If set, the XTAL32M will be started"]
1075    #[inline(always)]
1076    pub fn en_xtal(
1077        self,
1078    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl3Reg_SPEC, crate::common::RW> {
1079        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
1080    }
1081
1082    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
1083    #[inline(always)]
1084    pub fn trig_id(
1085        self,
1086    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl3Reg_SPEC, crate::common::RW>
1087    {
1088        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
1089    }
1090
1091    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
1092    #[inline(always)]
1093    pub fn trig_select(
1094        self,
1095    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl3Reg_SPEC, crate::common::RW>
1096    {
1097        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
1098    }
1099}
1100impl ::core::default::Default for PdcCtrl3Reg {
1101    #[inline(always)]
1102    fn default() -> PdcCtrl3Reg {
1103        <crate::RegValueT<PdcCtrl3Reg_SPEC> as RegisterValue<_>>::new(0)
1104    }
1105}
1106
1107#[doc(hidden)]
1108#[derive(Copy, Clone, Eq, PartialEq)]
1109pub struct PdcCtrl4Reg_SPEC;
1110impl crate::sealed::RegSpec for PdcCtrl4Reg_SPEC {
1111    type DataType = u32;
1112}
1113
1114#[doc = "PDC control register"]
1115pub type PdcCtrl4Reg = crate::RegValueT<PdcCtrl4Reg_SPEC>;
1116
1117impl PdcCtrl4Reg {
1118    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
1119    #[inline(always)]
1120    pub fn pdc_master(
1121        self,
1122    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl4Reg_SPEC, crate::common::RW>
1123    {
1124        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl4Reg_SPEC,crate::common::RW>::from_register(self,0)
1125    }
1126
1127    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
1128    #[inline(always)]
1129    pub fn en_com(
1130        self,
1131    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl4Reg_SPEC, crate::common::RW> {
1132        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl4Reg_SPEC,crate::common::RW>::from_register(self,0)
1133    }
1134
1135    #[doc = "If set, enables PD_PER"]
1136    #[inline(always)]
1137    pub fn en_per(
1138        self,
1139    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl4Reg_SPEC, crate::common::RW> {
1140        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl4Reg_SPEC,crate::common::RW>::from_register(self,0)
1141    }
1142
1143    #[doc = "If set, enables PD_TMR"]
1144    #[inline(always)]
1145    pub fn en_tmr(
1146        self,
1147    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl4Reg_SPEC, crate::common::RW> {
1148        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl4Reg_SPEC,crate::common::RW>::from_register(self,0)
1149    }
1150
1151    #[doc = "If set, the XTAL32M will be started"]
1152    #[inline(always)]
1153    pub fn en_xtal(
1154        self,
1155    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl4Reg_SPEC, crate::common::RW> {
1156        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl4Reg_SPEC,crate::common::RW>::from_register(self,0)
1157    }
1158
1159    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
1160    #[inline(always)]
1161    pub fn trig_id(
1162        self,
1163    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl4Reg_SPEC, crate::common::RW>
1164    {
1165        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl4Reg_SPEC,crate::common::RW>::from_register(self,0)
1166    }
1167
1168    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
1169    #[inline(always)]
1170    pub fn trig_select(
1171        self,
1172    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl4Reg_SPEC, crate::common::RW>
1173    {
1174        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl4Reg_SPEC,crate::common::RW>::from_register(self,0)
1175    }
1176}
1177impl ::core::default::Default for PdcCtrl4Reg {
1178    #[inline(always)]
1179    fn default() -> PdcCtrl4Reg {
1180        <crate::RegValueT<PdcCtrl4Reg_SPEC> as RegisterValue<_>>::new(0)
1181    }
1182}
1183
1184#[doc(hidden)]
1185#[derive(Copy, Clone, Eq, PartialEq)]
1186pub struct PdcCtrl5Reg_SPEC;
1187impl crate::sealed::RegSpec for PdcCtrl5Reg_SPEC {
1188    type DataType = u32;
1189}
1190
1191#[doc = "PDC control register"]
1192pub type PdcCtrl5Reg = crate::RegValueT<PdcCtrl5Reg_SPEC>;
1193
1194impl PdcCtrl5Reg {
1195    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
1196    #[inline(always)]
1197    pub fn pdc_master(
1198        self,
1199    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl5Reg_SPEC, crate::common::RW>
1200    {
1201        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl5Reg_SPEC,crate::common::RW>::from_register(self,0)
1202    }
1203
1204    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
1205    #[inline(always)]
1206    pub fn en_com(
1207        self,
1208    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl5Reg_SPEC, crate::common::RW> {
1209        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl5Reg_SPEC,crate::common::RW>::from_register(self,0)
1210    }
1211
1212    #[doc = "If set, enables PD_PER"]
1213    #[inline(always)]
1214    pub fn en_per(
1215        self,
1216    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl5Reg_SPEC, crate::common::RW> {
1217        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl5Reg_SPEC,crate::common::RW>::from_register(self,0)
1218    }
1219
1220    #[doc = "If set, enables PD_TMR"]
1221    #[inline(always)]
1222    pub fn en_tmr(
1223        self,
1224    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl5Reg_SPEC, crate::common::RW> {
1225        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl5Reg_SPEC,crate::common::RW>::from_register(self,0)
1226    }
1227
1228    #[doc = "If set, the XTAL32M will be started"]
1229    #[inline(always)]
1230    pub fn en_xtal(
1231        self,
1232    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl5Reg_SPEC, crate::common::RW> {
1233        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl5Reg_SPEC,crate::common::RW>::from_register(self,0)
1234    }
1235
1236    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
1237    #[inline(always)]
1238    pub fn trig_id(
1239        self,
1240    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl5Reg_SPEC, crate::common::RW>
1241    {
1242        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl5Reg_SPEC,crate::common::RW>::from_register(self,0)
1243    }
1244
1245    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
1246    #[inline(always)]
1247    pub fn trig_select(
1248        self,
1249    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl5Reg_SPEC, crate::common::RW>
1250    {
1251        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl5Reg_SPEC,crate::common::RW>::from_register(self,0)
1252    }
1253}
1254impl ::core::default::Default for PdcCtrl5Reg {
1255    #[inline(always)]
1256    fn default() -> PdcCtrl5Reg {
1257        <crate::RegValueT<PdcCtrl5Reg_SPEC> as RegisterValue<_>>::new(0)
1258    }
1259}
1260
1261#[doc(hidden)]
1262#[derive(Copy, Clone, Eq, PartialEq)]
1263pub struct PdcCtrl6Reg_SPEC;
1264impl crate::sealed::RegSpec for PdcCtrl6Reg_SPEC {
1265    type DataType = u32;
1266}
1267
1268#[doc = "PDC control register"]
1269pub type PdcCtrl6Reg = crate::RegValueT<PdcCtrl6Reg_SPEC>;
1270
1271impl PdcCtrl6Reg {
1272    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
1273    #[inline(always)]
1274    pub fn pdc_master(
1275        self,
1276    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl6Reg_SPEC, crate::common::RW>
1277    {
1278        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl6Reg_SPEC,crate::common::RW>::from_register(self,0)
1279    }
1280
1281    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
1282    #[inline(always)]
1283    pub fn en_com(
1284        self,
1285    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl6Reg_SPEC, crate::common::RW> {
1286        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl6Reg_SPEC,crate::common::RW>::from_register(self,0)
1287    }
1288
1289    #[doc = "If set, enables PD_PER"]
1290    #[inline(always)]
1291    pub fn en_per(
1292        self,
1293    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl6Reg_SPEC, crate::common::RW> {
1294        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl6Reg_SPEC,crate::common::RW>::from_register(self,0)
1295    }
1296
1297    #[doc = "If set, enables PD_TMR"]
1298    #[inline(always)]
1299    pub fn en_tmr(
1300        self,
1301    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl6Reg_SPEC, crate::common::RW> {
1302        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl6Reg_SPEC,crate::common::RW>::from_register(self,0)
1303    }
1304
1305    #[doc = "If set, the XTAL32M will be started"]
1306    #[inline(always)]
1307    pub fn en_xtal(
1308        self,
1309    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl6Reg_SPEC, crate::common::RW> {
1310        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl6Reg_SPEC,crate::common::RW>::from_register(self,0)
1311    }
1312
1313    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
1314    #[inline(always)]
1315    pub fn trig_id(
1316        self,
1317    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl6Reg_SPEC, crate::common::RW>
1318    {
1319        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl6Reg_SPEC,crate::common::RW>::from_register(self,0)
1320    }
1321
1322    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
1323    #[inline(always)]
1324    pub fn trig_select(
1325        self,
1326    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl6Reg_SPEC, crate::common::RW>
1327    {
1328        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl6Reg_SPEC,crate::common::RW>::from_register(self,0)
1329    }
1330}
1331impl ::core::default::Default for PdcCtrl6Reg {
1332    #[inline(always)]
1333    fn default() -> PdcCtrl6Reg {
1334        <crate::RegValueT<PdcCtrl6Reg_SPEC> as RegisterValue<_>>::new(0)
1335    }
1336}
1337
1338#[doc(hidden)]
1339#[derive(Copy, Clone, Eq, PartialEq)]
1340pub struct PdcCtrl7Reg_SPEC;
1341impl crate::sealed::RegSpec for PdcCtrl7Reg_SPEC {
1342    type DataType = u32;
1343}
1344
1345#[doc = "PDC control register"]
1346pub type PdcCtrl7Reg = crate::RegValueT<PdcCtrl7Reg_SPEC>;
1347
1348impl PdcCtrl7Reg {
1349    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
1350    #[inline(always)]
1351    pub fn pdc_master(
1352        self,
1353    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl7Reg_SPEC, crate::common::RW>
1354    {
1355        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl7Reg_SPEC,crate::common::RW>::from_register(self,0)
1356    }
1357
1358    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
1359    #[inline(always)]
1360    pub fn en_com(
1361        self,
1362    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl7Reg_SPEC, crate::common::RW> {
1363        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl7Reg_SPEC,crate::common::RW>::from_register(self,0)
1364    }
1365
1366    #[doc = "If set, enables PD_PER"]
1367    #[inline(always)]
1368    pub fn en_per(
1369        self,
1370    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl7Reg_SPEC, crate::common::RW> {
1371        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl7Reg_SPEC,crate::common::RW>::from_register(self,0)
1372    }
1373
1374    #[doc = "If set, enables PD_TMR"]
1375    #[inline(always)]
1376    pub fn en_tmr(
1377        self,
1378    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl7Reg_SPEC, crate::common::RW> {
1379        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl7Reg_SPEC,crate::common::RW>::from_register(self,0)
1380    }
1381
1382    #[doc = "If set, the XTAL32M will be started"]
1383    #[inline(always)]
1384    pub fn en_xtal(
1385        self,
1386    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl7Reg_SPEC, crate::common::RW> {
1387        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl7Reg_SPEC,crate::common::RW>::from_register(self,0)
1388    }
1389
1390    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
1391    #[inline(always)]
1392    pub fn trig_id(
1393        self,
1394    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl7Reg_SPEC, crate::common::RW>
1395    {
1396        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl7Reg_SPEC,crate::common::RW>::from_register(self,0)
1397    }
1398
1399    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
1400    #[inline(always)]
1401    pub fn trig_select(
1402        self,
1403    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl7Reg_SPEC, crate::common::RW>
1404    {
1405        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl7Reg_SPEC,crate::common::RW>::from_register(self,0)
1406    }
1407}
1408impl ::core::default::Default for PdcCtrl7Reg {
1409    #[inline(always)]
1410    fn default() -> PdcCtrl7Reg {
1411        <crate::RegValueT<PdcCtrl7Reg_SPEC> as RegisterValue<_>>::new(0)
1412    }
1413}
1414
1415#[doc(hidden)]
1416#[derive(Copy, Clone, Eq, PartialEq)]
1417pub struct PdcCtrl8Reg_SPEC;
1418impl crate::sealed::RegSpec for PdcCtrl8Reg_SPEC {
1419    type DataType = u32;
1420}
1421
1422#[doc = "PDC control register"]
1423pub type PdcCtrl8Reg = crate::RegValueT<PdcCtrl8Reg_SPEC>;
1424
1425impl PdcCtrl8Reg {
1426    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
1427    #[inline(always)]
1428    pub fn pdc_master(
1429        self,
1430    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl8Reg_SPEC, crate::common::RW>
1431    {
1432        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl8Reg_SPEC,crate::common::RW>::from_register(self,0)
1433    }
1434
1435    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
1436    #[inline(always)]
1437    pub fn en_com(
1438        self,
1439    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl8Reg_SPEC, crate::common::RW> {
1440        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl8Reg_SPEC,crate::common::RW>::from_register(self,0)
1441    }
1442
1443    #[doc = "If set, enables PD_PER"]
1444    #[inline(always)]
1445    pub fn en_per(
1446        self,
1447    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl8Reg_SPEC, crate::common::RW> {
1448        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl8Reg_SPEC,crate::common::RW>::from_register(self,0)
1449    }
1450
1451    #[doc = "If set, enables PD_TMR"]
1452    #[inline(always)]
1453    pub fn en_tmr(
1454        self,
1455    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl8Reg_SPEC, crate::common::RW> {
1456        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl8Reg_SPEC,crate::common::RW>::from_register(self,0)
1457    }
1458
1459    #[doc = "If set, the XTAL32M will be started"]
1460    #[inline(always)]
1461    pub fn en_xtal(
1462        self,
1463    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl8Reg_SPEC, crate::common::RW> {
1464        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl8Reg_SPEC,crate::common::RW>::from_register(self,0)
1465    }
1466
1467    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
1468    #[inline(always)]
1469    pub fn trig_id(
1470        self,
1471    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl8Reg_SPEC, crate::common::RW>
1472    {
1473        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl8Reg_SPEC,crate::common::RW>::from_register(self,0)
1474    }
1475
1476    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
1477    #[inline(always)]
1478    pub fn trig_select(
1479        self,
1480    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl8Reg_SPEC, crate::common::RW>
1481    {
1482        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl8Reg_SPEC,crate::common::RW>::from_register(self,0)
1483    }
1484}
1485impl ::core::default::Default for PdcCtrl8Reg {
1486    #[inline(always)]
1487    fn default() -> PdcCtrl8Reg {
1488        <crate::RegValueT<PdcCtrl8Reg_SPEC> as RegisterValue<_>>::new(0)
1489    }
1490}
1491
1492#[doc(hidden)]
1493#[derive(Copy, Clone, Eq, PartialEq)]
1494pub struct PdcCtrl9Reg_SPEC;
1495impl crate::sealed::RegSpec for PdcCtrl9Reg_SPEC {
1496    type DataType = u32;
1497}
1498
1499#[doc = "PDC control register"]
1500pub type PdcCtrl9Reg = crate::RegValueT<PdcCtrl9Reg_SPEC>;
1501
1502impl PdcCtrl9Reg {
1503    #[doc = "Chooses which master is triggered when waking up\n0x0: entry is disabled.\n0x1: PD_SYS is woken up and CM33 is triggered\n0x2: PD_RAD is woken up and CMAC is triggered\n0x3: PD_COM is woken up and SNC is triggered"]
1504    #[inline(always)]
1505    pub fn pdc_master(
1506        self,
1507    ) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, PdcCtrl9Reg_SPEC, crate::common::RW>
1508    {
1509        crate::common::RegisterField::<11,0x3,1,0,u8,u8,PdcCtrl9Reg_SPEC,crate::common::RW>::from_register(self,0)
1510    }
1511
1512    #[doc = "If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC"]
1513    #[inline(always)]
1514    pub fn en_com(
1515        self,
1516    ) -> crate::common::RegisterFieldBool<10, 1, 0, PdcCtrl9Reg_SPEC, crate::common::RW> {
1517        crate::common::RegisterFieldBool::<10,1,0,PdcCtrl9Reg_SPEC,crate::common::RW>::from_register(self,0)
1518    }
1519
1520    #[doc = "If set, enables PD_PER"]
1521    #[inline(always)]
1522    pub fn en_per(
1523        self,
1524    ) -> crate::common::RegisterFieldBool<9, 1, 0, PdcCtrl9Reg_SPEC, crate::common::RW> {
1525        crate::common::RegisterFieldBool::<9,1,0,PdcCtrl9Reg_SPEC,crate::common::RW>::from_register(self,0)
1526    }
1527
1528    #[doc = "If set, enables PD_TMR"]
1529    #[inline(always)]
1530    pub fn en_tmr(
1531        self,
1532    ) -> crate::common::RegisterFieldBool<8, 1, 0, PdcCtrl9Reg_SPEC, crate::common::RW> {
1533        crate::common::RegisterFieldBool::<8,1,0,PdcCtrl9Reg_SPEC,crate::common::RW>::from_register(self,0)
1534    }
1535
1536    #[doc = "If set, the XTAL32M will be started"]
1537    #[inline(always)]
1538    pub fn en_xtal(
1539        self,
1540    ) -> crate::common::RegisterFieldBool<7, 1, 0, PdcCtrl9Reg_SPEC, crate::common::RW> {
1541        crate::common::RegisterFieldBool::<7,1,0,PdcCtrl9Reg_SPEC,crate::common::RW>::from_register(self,0)
1542    }
1543
1544    #[doc = "For description, see PDC_CTRL0_REG.TRIG_ID"]
1545    #[inline(always)]
1546    pub fn trig_id(
1547        self,
1548    ) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, PdcCtrl9Reg_SPEC, crate::common::RW>
1549    {
1550        crate::common::RegisterField::<2,0x1f,1,0,u8,u8,PdcCtrl9Reg_SPEC,crate::common::RW>::from_register(self,0)
1551    }
1552
1553    #[doc = "For description, see PDC_CTRL0_REG.TRIG_SELECT"]
1554    #[inline(always)]
1555    pub fn trig_select(
1556        self,
1557    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, PdcCtrl9Reg_SPEC, crate::common::RW>
1558    {
1559        crate::common::RegisterField::<0,0x3,1,0,u8,u8,PdcCtrl9Reg_SPEC,crate::common::RW>::from_register(self,0)
1560    }
1561}
1562impl ::core::default::Default for PdcCtrl9Reg {
1563    #[inline(always)]
1564    fn default() -> PdcCtrl9Reg {
1565        <crate::RegValueT<PdcCtrl9Reg_SPEC> as RegisterValue<_>>::new(0)
1566    }
1567}
1568
1569#[doc(hidden)]
1570#[derive(Copy, Clone, Eq, PartialEq)]
1571pub struct PdcPendingCm33Reg_SPEC;
1572impl crate::sealed::RegSpec for PdcPendingCm33Reg_SPEC {
1573    type DataType = u32;
1574}
1575
1576#[doc = "Shows any pending IRQ to CM33"]
1577pub type PdcPendingCm33Reg = crate::RegValueT<PdcPendingCm33Reg_SPEC>;
1578
1579impl PdcPendingCm33Reg {
1580    #[doc = "Indicates which IRQ ids are pending towards the CM33"]
1581    #[inline(always)]
1582    pub fn pdc_pending(
1583        self,
1584    ) -> crate::common::RegisterField<
1585        0,
1586        0xffff,
1587        1,
1588        0,
1589        u16,
1590        u16,
1591        PdcPendingCm33Reg_SPEC,
1592        crate::common::R,
1593    > {
1594        crate::common::RegisterField::<
1595            0,
1596            0xffff,
1597            1,
1598            0,
1599            u16,
1600            u16,
1601            PdcPendingCm33Reg_SPEC,
1602            crate::common::R,
1603        >::from_register(self, 0)
1604    }
1605}
1606impl ::core::default::Default for PdcPendingCm33Reg {
1607    #[inline(always)]
1608    fn default() -> PdcPendingCm33Reg {
1609        <crate::RegValueT<PdcPendingCm33Reg_SPEC> as RegisterValue<_>>::new(0)
1610    }
1611}
1612
1613#[doc(hidden)]
1614#[derive(Copy, Clone, Eq, PartialEq)]
1615pub struct PdcPendingCmacReg_SPEC;
1616impl crate::sealed::RegSpec for PdcPendingCmacReg_SPEC {
1617    type DataType = u32;
1618}
1619
1620#[doc = "Shows any pending IRQ to CM33"]
1621pub type PdcPendingCmacReg = crate::RegValueT<PdcPendingCmacReg_SPEC>;
1622
1623impl PdcPendingCmacReg {
1624    #[doc = "Indicates which IRQ ids are pending towards the CMAC"]
1625    #[inline(always)]
1626    pub fn pdc_pending(
1627        self,
1628    ) -> crate::common::RegisterField<
1629        0,
1630        0xffff,
1631        1,
1632        0,
1633        u16,
1634        u16,
1635        PdcPendingCmacReg_SPEC,
1636        crate::common::R,
1637    > {
1638        crate::common::RegisterField::<
1639            0,
1640            0xffff,
1641            1,
1642            0,
1643            u16,
1644            u16,
1645            PdcPendingCmacReg_SPEC,
1646            crate::common::R,
1647        >::from_register(self, 0)
1648    }
1649}
1650impl ::core::default::Default for PdcPendingCmacReg {
1651    #[inline(always)]
1652    fn default() -> PdcPendingCmacReg {
1653        <crate::RegValueT<PdcPendingCmacReg_SPEC> as RegisterValue<_>>::new(0)
1654    }
1655}
1656
1657#[doc(hidden)]
1658#[derive(Copy, Clone, Eq, PartialEq)]
1659pub struct PdcPendingReg_SPEC;
1660impl crate::sealed::RegSpec for PdcPendingReg_SPEC {
1661    type DataType = u32;
1662}
1663
1664#[doc = "Shows any pending wakup event"]
1665pub type PdcPendingReg = crate::RegValueT<PdcPendingReg_SPEC>;
1666
1667impl PdcPendingReg {
1668    #[doc = "Indicates which IRQ ids are pending"]
1669    #[inline(always)]
1670    pub fn pdc_pending(
1671        self,
1672    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, PdcPendingReg_SPEC, crate::common::R>
1673    {
1674        crate::common::RegisterField::<
1675            0,
1676            0xffff,
1677            1,
1678            0,
1679            u16,
1680            u16,
1681            PdcPendingReg_SPEC,
1682            crate::common::R,
1683        >::from_register(self, 0)
1684    }
1685}
1686impl ::core::default::Default for PdcPendingReg {
1687    #[inline(always)]
1688    fn default() -> PdcPendingReg {
1689        <crate::RegValueT<PdcPendingReg_SPEC> as RegisterValue<_>>::new(0)
1690    }
1691}
1692
1693#[doc(hidden)]
1694#[derive(Copy, Clone, Eq, PartialEq)]
1695pub struct PdcPendingSncReg_SPEC;
1696impl crate::sealed::RegSpec for PdcPendingSncReg_SPEC {
1697    type DataType = u32;
1698}
1699
1700#[doc = "Shows any pending IRQ to SNC"]
1701pub type PdcPendingSncReg = crate::RegValueT<PdcPendingSncReg_SPEC>;
1702
1703impl PdcPendingSncReg {
1704    #[doc = "Indicates which IRQ ids are pending towards the SensorNodeController"]
1705    #[inline(always)]
1706    pub fn pdc_pending(
1707        self,
1708    ) -> crate::common::RegisterField<
1709        0,
1710        0xffff,
1711        1,
1712        0,
1713        u16,
1714        u16,
1715        PdcPendingSncReg_SPEC,
1716        crate::common::R,
1717    > {
1718        crate::common::RegisterField::<
1719            0,
1720            0xffff,
1721            1,
1722            0,
1723            u16,
1724            u16,
1725            PdcPendingSncReg_SPEC,
1726            crate::common::R,
1727        >::from_register(self, 0)
1728    }
1729}
1730impl ::core::default::Default for PdcPendingSncReg {
1731    #[inline(always)]
1732    fn default() -> PdcPendingSncReg {
1733        <crate::RegValueT<PdcPendingSncReg_SPEC> as RegisterValue<_>>::new(0)
1734    }
1735}
1736
1737#[doc(hidden)]
1738#[derive(Copy, Clone, Eq, PartialEq)]
1739pub struct PdcSetPendingReg_SPEC;
1740impl crate::sealed::RegSpec for PdcSetPendingReg_SPEC {
1741    type DataType = u32;
1742}
1743
1744#[doc = "Set a pending PDC bit"]
1745pub type PdcSetPendingReg = crate::RegValueT<PdcSetPendingReg_SPEC>;
1746
1747impl PdcSetPendingReg {
1748    #[doc = "Writing to this field sets the PDC wakeup request and IRQ.\nThe data controls which request is acknowledged"]
1749    #[inline(always)]
1750    pub fn pdc_set_pending(
1751        self,
1752    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, PdcSetPendingReg_SPEC, crate::common::W>
1753    {
1754        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,PdcSetPendingReg_SPEC,crate::common::W>::from_register(self,0)
1755    }
1756}
1757impl ::core::default::Default for PdcSetPendingReg {
1758    #[inline(always)]
1759    fn default() -> PdcSetPendingReg {
1760        <crate::RegValueT<PdcSetPendingReg_SPEC> as RegisterValue<_>>::new(0)
1761    }
1762}
da14697_pac/pdc.rs

da14697_pac/
pdc.rs
