da14682_pac/
quad.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:10 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"QUAD registers"]
28unsafe impl ::core::marker::Send for super::Quad {}
29unsafe impl ::core::marker::Sync for super::Quad {}
30impl super::Quad {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Quad decoder clock divider register"]
38    #[inline(always)]
39    pub const fn qdec_clockdiv_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::QdecClockdivReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::QdecClockdivReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(8usize),
45            )
46        }
47    }
48
49    #[doc = "Quad decoder control register"]
50    #[inline(always)]
51    pub const fn qdec_ctrl_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::QdecCtrlReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::QdecCtrlReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0usize),
57            )
58        }
59    }
60
61    #[doc = "Counter value of the X Axis"]
62    #[inline(always)]
63    pub const fn qdec_xcnt_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::QdecXcntReg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::QdecXcntReg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(2usize),
69            )
70        }
71    }
72
73    #[doc = "Counter value of the Y Axis"]
74    #[inline(always)]
75    pub const fn qdec_ycnt_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::QdecYcntReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::QdecYcntReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(4usize),
81            )
82        }
83    }
84
85    #[doc = "Counter value of the Z Axis"]
86    #[inline(always)]
87    pub const fn qdec_zcnt_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::QdecZcntReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::QdecZcntReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(6usize),
93            )
94        }
95    }
96}
97#[doc(hidden)]
98#[derive(Copy, Clone, Eq, PartialEq)]
99pub struct QdecClockdivReg_SPEC;
100impl crate::sealed::RegSpec for QdecClockdivReg_SPEC {
101    type DataType = u16;
102}
103
104#[doc = "Quad decoder clock divider register"]
105pub type QdecClockdivReg = crate::RegValueT<QdecClockdivReg_SPEC>;
106
107impl QdecClockdivReg {
108    #[doc = "Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle."]
109    #[inline(always)]
110    pub fn clock_divider(
111        self,
112    ) -> crate::common::RegisterField<
113        0,
114        0x3ff,
115        1,
116        0,
117        u16,
118        u16,
119        QdecClockdivReg_SPEC,
120        crate::common::RW,
121    > {
122        crate::common::RegisterField::<
123            0,
124            0x3ff,
125            1,
126            0,
127            u16,
128            u16,
129            QdecClockdivReg_SPEC,
130            crate::common::RW,
131        >::from_register(self, 0)
132    }
133}
134impl ::core::default::Default for QdecClockdivReg {
135    #[inline(always)]
136    fn default() -> QdecClockdivReg {
137        <crate::RegValueT<QdecClockdivReg_SPEC> as RegisterValue<_>>::new(0)
138    }
139}
140
141#[doc(hidden)]
142#[derive(Copy, Clone, Eq, PartialEq)]
143pub struct QdecCtrlReg_SPEC;
144impl crate::sealed::RegSpec for QdecCtrlReg_SPEC {
145    type DataType = u16;
146}
147
148#[doc = "Quad decoder control register"]
149pub type QdecCtrlReg = crate::RegValueT<QdecCtrlReg_SPEC>;
150
151impl QdecCtrlReg {
152    #[doc = "\'1\' : Enable channel"]
153    #[inline(always)]
154    pub fn chz_port_en(
155        self,
156    ) -> crate::common::RegisterFieldBool<12, 1, 0, QdecCtrlReg_SPEC, crate::common::RW> {
157        crate::common::RegisterFieldBool::<12,1,0,QdecCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
158    }
159
160    #[doc = "\'1\' : Enable channel"]
161    #[inline(always)]
162    pub fn chy_port_en(
163        self,
164    ) -> crate::common::RegisterFieldBool<11, 1, 0, QdecCtrlReg_SPEC, crate::common::RW> {
165        crate::common::RegisterFieldBool::<11,1,0,QdecCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
166    }
167
168    #[doc = "\'1\' : Enable channel"]
169    #[inline(always)]
170    pub fn chx_port_en(
171        self,
172    ) -> crate::common::RegisterFieldBool<10, 1, 0, QdecCtrlReg_SPEC, crate::common::RW> {
173        crate::common::RegisterFieldBool::<10,1,0,QdecCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
174    }
175
176    #[doc = "The number of events on either counter (X or Y or Z) that need to be reached before an interrupt is generated. If 0 is written, then threshold is considered to be 1."]
177    #[inline(always)]
178    pub fn qd_irq_thres(
179        self,
180    ) -> crate::common::RegisterField<3, 0x7f, 1, 0, u8, u8, QdecCtrlReg_SPEC, crate::common::RW>
181    {
182        crate::common::RegisterField::<3,0x7f,1,0,u8,u8,QdecCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
183    }
184
185    #[doc = "Interrupt Status. If 1 an interrupt has occured."]
186    #[inline(always)]
187    pub fn qd_irq_status(
188        self,
189    ) -> crate::common::RegisterFieldBool<2, 1, 0, QdecCtrlReg_SPEC, crate::common::R> {
190        crate::common::RegisterFieldBool::<2,1,0,QdecCtrlReg_SPEC,crate::common::R>::from_register(self,0)
191    }
192
193    #[doc = "Writing 1 to this bit clears the interrupt. This bit is autocleared"]
194    #[inline(always)]
195    pub fn qd_irq_clr(
196        self,
197    ) -> crate::common::RegisterFieldBool<1, 1, 0, QdecCtrlReg_SPEC, crate::common::RW> {
198        crate::common::RegisterFieldBool::<1,1,0,QdecCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
199    }
200
201    #[doc = "0: interrupt is masked\n1: interrupt is enabled"]
202    #[inline(always)]
203    pub fn qd_irq_mask(
204        self,
205    ) -> crate::common::RegisterFieldBool<0, 1, 0, QdecCtrlReg_SPEC, crate::common::RW> {
206        crate::common::RegisterFieldBool::<0,1,0,QdecCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
207    }
208}
209impl ::core::default::Default for QdecCtrlReg {
210    #[inline(always)]
211    fn default() -> QdecCtrlReg {
212        <crate::RegValueT<QdecCtrlReg_SPEC> as RegisterValue<_>>::new(16)
213    }
214}
215
216#[doc(hidden)]
217#[derive(Copy, Clone, Eq, PartialEq)]
218pub struct QdecXcntReg_SPEC;
219impl crate::sealed::RegSpec for QdecXcntReg_SPEC {
220    type DataType = u16;
221}
222
223#[doc = "Counter value of the X Axis"]
224pub type QdecXcntReg = crate::RegValueT<QdecXcntReg_SPEC>;
225
226impl QdecXcntReg {
227    #[doc = "Contains a signed value of the events. Zero when channel is disabled"]
228    #[inline(always)]
229    pub fn x_counter(
230        self,
231    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, QdecXcntReg_SPEC, crate::common::R>
232    {
233        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,QdecXcntReg_SPEC,crate::common::R>::from_register(self,0)
234    }
235}
236impl ::core::default::Default for QdecXcntReg {
237    #[inline(always)]
238    fn default() -> QdecXcntReg {
239        <crate::RegValueT<QdecXcntReg_SPEC> as RegisterValue<_>>::new(0)
240    }
241}
242
243#[doc(hidden)]
244#[derive(Copy, Clone, Eq, PartialEq)]
245pub struct QdecYcntReg_SPEC;
246impl crate::sealed::RegSpec for QdecYcntReg_SPEC {
247    type DataType = u16;
248}
249
250#[doc = "Counter value of the Y Axis"]
251pub type QdecYcntReg = crate::RegValueT<QdecYcntReg_SPEC>;
252
253impl QdecYcntReg {
254    #[doc = "Contains a signed value of the events. Zero when channel is disabled"]
255    #[inline(always)]
256    pub fn y_counter(
257        self,
258    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, QdecYcntReg_SPEC, crate::common::R>
259    {
260        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,QdecYcntReg_SPEC,crate::common::R>::from_register(self,0)
261    }
262}
263impl ::core::default::Default for QdecYcntReg {
264    #[inline(always)]
265    fn default() -> QdecYcntReg {
266        <crate::RegValueT<QdecYcntReg_SPEC> as RegisterValue<_>>::new(0)
267    }
268}
269
270#[doc(hidden)]
271#[derive(Copy, Clone, Eq, PartialEq)]
272pub struct QdecZcntReg_SPEC;
273impl crate::sealed::RegSpec for QdecZcntReg_SPEC {
274    type DataType = u16;
275}
276
277#[doc = "Counter value of the Z Axis"]
278pub type QdecZcntReg = crate::RegValueT<QdecZcntReg_SPEC>;
279
280impl QdecZcntReg {
281    #[doc = "Contains a signed value of the events. Zero when channel is disabled"]
282    #[inline(always)]
283    pub fn z_counter(
284        self,
285    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, QdecZcntReg_SPEC, crate::common::R>
286    {
287        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,QdecZcntReg_SPEC,crate::common::R>::from_register(self,0)
288    }
289}
290impl ::core::default::Default for QdecZcntReg {
291    #[inline(always)]
292    fn default() -> QdecZcntReg {
293        <crate::RegValueT<QdecZcntReg_SPEC> as RegisterValue<_>>::new(0)
294    }
295}
da14682_pac/quad.rs

da14682_pac/
quad.rs
