da14682_pac/
gpreg.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:10 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"GPREG registers"]
28unsafe impl ::core::marker::Send for super::Gpreg {}
29unsafe impl ::core::marker::Sync for super::Gpreg {}
30impl super::Gpreg {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "BLE FINECNT sampled value while in deep sleep state."]
38    #[inline(always)]
39    pub const fn ble_finecnt_samp_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::BleFinecntSampReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::BleFinecntSampReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(14usize),
45            )
46        }
47    }
48
49    #[doc = "Various debug information register."]
50    #[inline(always)]
51    pub const fn debug_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::DebugReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::DebugReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(4usize),
57            )
58        }
59    }
60
61    #[doc = "Base address of the ECC Crypto memory register."]
62    #[inline(always)]
63    pub const fn ecc_base_addr_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::EccBaseAddrReg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::EccBaseAddrReg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(10usize),
69            )
70        }
71    }
72
73    #[doc = "General purpose system control register."]
74    #[inline(always)]
75    pub const fn gp_control_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::GpControlReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::GpControlReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(8usize),
81            )
82        }
83    }
84
85    #[doc = "General purpose system status register."]
86    #[inline(always)]
87    pub const fn gp_status_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::GpStatusReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::GpStatusReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(6usize),
93            )
94        }
95    }
96
97    #[doc = "Controls muxing and enabling of the LEDs."]
98    #[inline(always)]
99    pub const fn led_control_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::LedControlReg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::LedControlReg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(12usize),
105            )
106        }
107    }
108
109    #[doc = "System PLL control register 1."]
110    #[inline(always)]
111    pub const fn pll_sys_ctrl1_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::PllSysCtrl1Reg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::PllSysCtrl1Reg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(16usize),
117            )
118        }
119    }
120
121    #[doc = "System PLL control register 2."]
122    #[inline(always)]
123    pub const fn pll_sys_ctrl2_reg(
124        &self,
125    ) -> &'static crate::common::Reg<self::PllSysCtrl2Reg_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::PllSysCtrl2Reg_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(18usize),
129            )
130        }
131    }
132
133    #[doc = "System PLL control register 3."]
134    #[inline(always)]
135    pub const fn pll_sys_ctrl3_reg(
136        &self,
137    ) -> &'static crate::common::Reg<self::PllSysCtrl3Reg_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::PllSysCtrl3Reg_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(20usize),
141            )
142        }
143    }
144
145    #[doc = "System PLL status register."]
146    #[inline(always)]
147    pub const fn pll_sys_status_reg(
148        &self,
149    ) -> &'static crate::common::Reg<self::PllSysStatusReg_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::PllSysStatusReg_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(22usize),
153            )
154        }
155    }
156
157    #[doc = "System PLL test register."]
158    #[inline(always)]
159    pub const fn pll_sys_test_reg(
160        &self,
161    ) -> &'static crate::common::Reg<self::PllSysTestReg_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::PllSysTestReg_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(24usize),
165            )
166        }
167    }
168
169    #[doc = "Controls unfreezing of various timers/counters (incl. DMA and USB)."]
170    #[inline(always)]
171    pub const fn reset_freeze_reg(
172        &self,
173    ) -> &'static crate::common::Reg<self::ResetFreezeReg_SPEC, crate::common::RW> {
174        unsafe {
175            crate::common::Reg::<self::ResetFreezeReg_SPEC, crate::common::RW>::from_ptr(
176                self._svd2pac_as_ptr().add(2usize),
177            )
178        }
179    }
180
181    #[doc = "Controls freezing of various timers/counters (incl. DMA and USB)."]
182    #[inline(always)]
183    pub const fn set_freeze_reg(
184        &self,
185    ) -> &'static crate::common::Reg<self::SetFreezeReg_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::SetFreezeReg_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(0usize),
189            )
190        }
191    }
192}
193#[doc(hidden)]
194#[derive(Copy, Clone, Eq, PartialEq)]
195pub struct BleFinecntSampReg_SPEC;
196impl crate::sealed::RegSpec for BleFinecntSampReg_SPEC {
197    type DataType = u16;
198}
199
200#[doc = "BLE FINECNT sampled value while in deep sleep state."]
201pub type BleFinecntSampReg = crate::RegValueT<BleFinecntSampReg_SPEC>;
202
203impl BleFinecntSampReg {
204    #[doc = "This register is located at the Always On Power Domain and it holds the automatically sampled value of the BLE FINECNT timer\nThe HW automatically samples the value into this register during the sequence of \"BLE Sleep On\" and restores automatically the value during the BLE Wake up sequence.\nThe Software may read and modify the value while the BLE is in Sleep state. While the BLE is awake, the value of the register has no meaning, while changing the value by writing another one will have no effect in the operation of the BLE core."]
205    #[inline(always)]
206    pub fn ble_finecnt_samp(
207        self,
208    ) -> crate::common::RegisterField<
209        0,
210        0x3ff,
211        1,
212        0,
213        u16,
214        u16,
215        BleFinecntSampReg_SPEC,
216        crate::common::RW,
217    > {
218        crate::common::RegisterField::<
219            0,
220            0x3ff,
221            1,
222            0,
223            u16,
224            u16,
225            BleFinecntSampReg_SPEC,
226            crate::common::RW,
227        >::from_register(self, 0)
228    }
229}
230impl ::core::default::Default for BleFinecntSampReg {
231    #[inline(always)]
232    fn default() -> BleFinecntSampReg {
233        <crate::RegValueT<BleFinecntSampReg_SPEC> as RegisterValue<_>>::new(0)
234    }
235}
236
237#[doc(hidden)]
238#[derive(Copy, Clone, Eq, PartialEq)]
239pub struct DebugReg_SPEC;
240impl crate::sealed::RegSpec for DebugReg_SPEC {
241    type DataType = u16;
242}
243
244#[doc = "Various debug information register."]
245pub type DebugReg = crate::RegValueT<DebugReg_SPEC>;
246
247impl DebugReg {
248    #[doc = "Default \'1\', freezing of the on-chip timers is enabled when the Cortex-M0 is halted in DEBUG State.\nIf \'0\', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex-M0 is halted in DEBUG State except the watchdog timer. The watchdog timer is always frozen when the Cortex-M0 is halted in DEBUG State.\nNote: This bit is retained."]
249    #[inline(always)]
250    pub fn debugs_freeze_en(
251        self,
252    ) -> crate::common::RegisterFieldBool<0, 1, 0, DebugReg_SPEC, crate::common::RW> {
253        crate::common::RegisterFieldBool::<0, 1, 0, DebugReg_SPEC, crate::common::RW>::from_register(
254            self, 0,
255        )
256    }
257}
258impl ::core::default::Default for DebugReg {
259    #[inline(always)]
260    fn default() -> DebugReg {
261        <crate::RegValueT<DebugReg_SPEC> as RegisterValue<_>>::new(1)
262    }
263}
264
265#[doc(hidden)]
266#[derive(Copy, Clone, Eq, PartialEq)]
267pub struct EccBaseAddrReg_SPEC;
268impl crate::sealed::RegSpec for EccBaseAddrReg_SPEC {
269    type DataType = u16;
270}
271
272#[doc = "Base address of the ECC Crypto memory register."]
273pub type EccBaseAddrReg = crate::RegValueT<EccBaseAddrReg_SPEC>;
274
275impl EccBaseAddrReg {
276    #[doc = "Contains the base address of the ECC Crypto memory.\nMemory allocation is in pages of 1KB and up to 127KB.\nSince the ECC has an address range of 2KB and the total addressable memory range is 128KB, the maximum value of 0x7F (127KB offset) will result in 1KB at the top of the memory range and the other 1KB at the bottom of the memory range."]
277    #[inline(always)]
278    pub fn ecc_base_addr(
279        self,
280    ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, EccBaseAddrReg_SPEC, crate::common::RW>
281    {
282        crate::common::RegisterField::<0,0x7f,1,0,u8,u8,EccBaseAddrReg_SPEC,crate::common::RW>::from_register(self,0)
283    }
284}
285impl ::core::default::Default for EccBaseAddrReg {
286    #[inline(always)]
287    fn default() -> EccBaseAddrReg {
288        <crate::RegValueT<EccBaseAddrReg_SPEC> as RegisterValue<_>>::new(0)
289    }
290}
291
292#[doc(hidden)]
293#[derive(Copy, Clone, Eq, PartialEq)]
294pub struct GpControlReg_SPEC;
295impl crate::sealed::RegSpec for GpControlReg_SPEC {
296    type DataType = u16;
297}
298
299#[doc = "General purpose system control register."]
300pub type GpControlReg = crate::RegValueT<GpControlReg_SPEC>;
301
302impl GpControlReg {
303    #[doc = "The current value of the BLE_WAKEUP_LP_IRQ interrupt request."]
304    #[inline(always)]
305    pub fn ble_wakeup_lp_irq(
306        self,
307    ) -> crate::common::RegisterFieldBool<2, 1, 0, GpControlReg_SPEC, crate::common::R> {
308        crate::common::RegisterFieldBool::<2,1,0,GpControlReg_SPEC,crate::common::R>::from_register(self,0)
309    }
310
311    #[doc = "If \'1\', the AHB-to-AHB bridge is bypassed, needed to access the BLE Register file, only when the system clock source is the XTAL and both hclk and ble_hclk are running at 16MHz, i.e. at the XTAL clock rate."]
312    #[inline(always)]
313    pub fn ble_h2h_bridge_bypass(
314        self,
315    ) -> crate::common::RegisterFieldBool<1, 1, 0, GpControlReg_SPEC, crate::common::RW> {
316        crate::common::RegisterFieldBool::<1,1,0,GpControlReg_SPEC,crate::common::RW>::from_register(self,0)
317    }
318
319    #[doc = "If \'1\', the BLE wakes up. Must be kept high at least for 1 low power clock period. \nIf the BLE is in deep sleep state, then by setting this bit it will cause the wakeup LP IRQ to be asserted with a delay of 3 to 4 low power cycles."]
320    #[inline(always)]
321    pub fn ble_wakeup_req(
322        self,
323    ) -> crate::common::RegisterFieldBool<0, 1, 0, GpControlReg_SPEC, crate::common::RW> {
324        crate::common::RegisterFieldBool::<0,1,0,GpControlReg_SPEC,crate::common::RW>::from_register(self,0)
325    }
326}
327impl ::core::default::Default for GpControlReg {
328    #[inline(always)]
329    fn default() -> GpControlReg {
330        <crate::RegValueT<GpControlReg_SPEC> as RegisterValue<_>>::new(0)
331    }
332}
333
334#[doc(hidden)]
335#[derive(Copy, Clone, Eq, PartialEq)]
336pub struct GpStatusReg_SPEC;
337impl crate::sealed::RegSpec for GpStatusReg_SPEC {
338    type DataType = u16;
339}
340
341#[doc = "General purpose system status register."]
342pub type GpStatusReg = crate::RegValueT<GpStatusReg_SPEC>;
343
344impl GpStatusReg {
345    #[doc = "If \'1\', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured."]
346    #[inline(always)]
347    pub fn cal_phase(
348        self,
349    ) -> crate::common::RegisterFieldBool<0, 1, 0, GpStatusReg_SPEC, crate::common::RW> {
350        crate::common::RegisterFieldBool::<0,1,0,GpStatusReg_SPEC,crate::common::RW>::from_register(self,0)
351    }
352}
353impl ::core::default::Default for GpStatusReg {
354    #[inline(always)]
355    fn default() -> GpStatusReg {
356        <crate::RegValueT<GpStatusReg_SPEC> as RegisterValue<_>>::new(0)
357    }
358}
359
360#[doc(hidden)]
361#[derive(Copy, Clone, Eq, PartialEq)]
362pub struct LedControlReg_SPEC;
363impl crate::sealed::RegSpec for LedControlReg_SPEC {
364    type DataType = u16;
365}
366
367#[doc = "Controls muxing and enabling of the LEDs."]
368pub type LedControlReg = crate::RegValueT<LedControlReg_SPEC>;
369
370impl LedControlReg {
371    #[doc = "LED current trimming bits."]
372    #[inline(always)]
373    pub fn led_trim(
374        self,
375    ) -> crate::common::RegisterField<6, 0xf, 1, 0, u8, u8, LedControlReg_SPEC, crate::common::RW>
376    {
377        crate::common::RegisterField::<6,0xf,1,0,u8,u8,LedControlReg_SPEC,crate::common::RW>::from_register(self,0)
378    }
379
380    #[doc = "0: LED3 disabled,\n1: LED3 enabled."]
381    #[inline(always)]
382    pub fn led3_en(
383        self,
384    ) -> crate::common::RegisterFieldBool<5, 1, 0, LedControlReg_SPEC, crate::common::RW> {
385        crate::common::RegisterFieldBool::<5,1,0,LedControlReg_SPEC,crate::common::RW>::from_register(self,0)
386    }
387
388    #[doc = "0: LED2 disabled,\n1: LED2 enabled."]
389    #[inline(always)]
390    pub fn led2_en(
391        self,
392    ) -> crate::common::RegisterFieldBool<4, 1, 0, LedControlReg_SPEC, crate::common::RW> {
393        crate::common::RegisterFieldBool::<4,1,0,LedControlReg_SPEC,crate::common::RW>::from_register(self,0)
394    }
395
396    #[doc = "0: LED1 disabled,\n1: LED1 enabled."]
397    #[inline(always)]
398    pub fn led1_en(
399        self,
400    ) -> crate::common::RegisterFieldBool<3, 1, 0, LedControlReg_SPEC, crate::common::RW> {
401        crate::common::RegisterFieldBool::<3,1,0,LedControlReg_SPEC,crate::common::RW>::from_register(self,0)
402    }
403
404    #[doc = "0: LED3 = PWM4,\n1: LED3 = Breathing Timer."]
405    #[inline(always)]
406    pub fn led3_src_sel(
407        self,
408    ) -> crate::common::RegisterFieldBool<2, 1, 0, LedControlReg_SPEC, crate::common::RW> {
409        crate::common::RegisterFieldBool::<2,1,0,LedControlReg_SPEC,crate::common::RW>::from_register(self,0)
410    }
411
412    #[doc = "0: LED2 = PWM3,\n1: LED2 = Breathing Timer."]
413    #[inline(always)]
414    pub fn led2_src_sel(
415        self,
416    ) -> crate::common::RegisterFieldBool<1, 1, 0, LedControlReg_SPEC, crate::common::RW> {
417        crate::common::RegisterFieldBool::<1,1,0,LedControlReg_SPEC,crate::common::RW>::from_register(self,0)
418    }
419
420    #[doc = "0: LED1 = PWM2,\n1: LED1 = Breathing Timer.\nNote: The PWM2/3/4 can also be routed to GPIOs using PID 25/26/27 respectively."]
421    #[inline(always)]
422    pub fn led1_src_sel(
423        self,
424    ) -> crate::common::RegisterFieldBool<0, 1, 0, LedControlReg_SPEC, crate::common::RW> {
425        crate::common::RegisterFieldBool::<0,1,0,LedControlReg_SPEC,crate::common::RW>::from_register(self,0)
426    }
427}
428impl ::core::default::Default for LedControlReg {
429    #[inline(always)]
430    fn default() -> LedControlReg {
431        <crate::RegValueT<LedControlReg_SPEC> as RegisterValue<_>>::new(0)
432    }
433}
434
435#[doc(hidden)]
436#[derive(Copy, Clone, Eq, PartialEq)]
437pub struct PllSysCtrl1Reg_SPEC;
438impl crate::sealed::RegSpec for PllSysCtrl1Reg_SPEC {
439    type DataType = u16;
440}
441
442#[doc = "System PLL control register 1."]
443pub type PllSysCtrl1Reg = crate::RegValueT<PllSysCtrl1Reg_SPEC>;
444
445impl PllSysCtrl1Reg {
446    #[doc = "PLL Output dvider R (x means divide by x, 0 means divide by 1)"]
447    #[inline(always)]
448    pub fn pll_r_div(
449        self,
450    ) -> crate::common::RegisterField<8, 0x7f, 1, 0, u8, u8, PllSysCtrl1Reg_SPEC, crate::common::RW>
451    {
452        crate::common::RegisterField::<8,0x7f,1,0,u8,u8,PllSysCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
453    }
454
455    #[doc = "0: indicates that the reference input is tracked,\n1: indicates that the reference input is sampled."]
456    #[inline(always)]
457    pub fn ldo_pll_vref_hold(
458        self,
459    ) -> crate::common::RegisterFieldBool<2, 1, 0, PllSysCtrl1Reg_SPEC, crate::common::RW> {
460        crate::common::RegisterFieldBool::<2,1,0,PllSysCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
461    }
462
463    #[doc = "0: LDO PLL off,\n1: LDO PLL on."]
464    #[inline(always)]
465    pub fn ldo_pll_enable(
466        self,
467    ) -> crate::common::RegisterFieldBool<1, 1, 0, PllSysCtrl1Reg_SPEC, crate::common::RW> {
468        crate::common::RegisterFieldBool::<1,1,0,PllSysCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
469    }
470
471    #[doc = "0: Power down\n1: PLL on"]
472    #[inline(always)]
473    pub fn pll_en(
474        self,
475    ) -> crate::common::RegisterFieldBool<0, 1, 0, PllSysCtrl1Reg_SPEC, crate::common::RW> {
476        crate::common::RegisterFieldBool::<0,1,0,PllSysCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
477    }
478}
479impl ::core::default::Default for PllSysCtrl1Reg {
480    #[inline(always)]
481    fn default() -> PllSysCtrl1Reg {
482        <crate::RegValueT<PllSysCtrl1Reg_SPEC> as RegisterValue<_>>::new(256)
483    }
484}
485
486#[doc(hidden)]
487#[derive(Copy, Clone, Eq, PartialEq)]
488pub struct PllSysCtrl2Reg_SPEC;
489impl crate::sealed::RegSpec for PllSysCtrl2Reg_SPEC {
490    type DataType = u16;
491}
492
493#[doc = "System PLL control register 2."]
494pub type PllSysCtrl2Reg = crate::RegValueT<PllSysCtrl2Reg_SPEC>;
495
496impl PllSysCtrl2Reg {
497    #[doc = "0: VCO current read from min_current <5:0>,\n1: VCO current is internally determined with a calibration algoritm."]
498    #[inline(always)]
499    pub fn pll_sel_min_cur_int(
500        self,
501    ) -> crate::common::RegisterFieldBool<14, 1, 0, PllSysCtrl2Reg_SPEC, crate::common::RW> {
502        crate::common::RegisterFieldBool::<14,1,0,PllSysCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
503    }
504
505    #[doc = "PLL manual delay value for Phase Frequency Detector.\n0: 0.493\n1: 0.814\n2: 1.13 ns <- default\n3: 1.44 ns"]
506    #[inline(always)]
507    pub fn pll_del_sel(
508        self,
509    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, PllSysCtrl2Reg_SPEC, crate::common::RW>
510    {
511        crate::common::RegisterField::<12,0x3,1,0,u8,u8,PllSysCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
512    }
513
514    #[doc = "PLL Loop divider N (x means divide by x, 0 means divide by 1)"]
515    #[inline(always)]
516    pub fn pll_n_div(
517        self,
518    ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, PllSysCtrl2Reg_SPEC, crate::common::RW>
519    {
520        crate::common::RegisterField::<0,0x7f,1,0,u8,u8,PllSysCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
521    }
522}
523impl ::core::default::Default for PllSysCtrl2Reg {
524    #[inline(always)]
525    fn default() -> PllSysCtrl2Reg {
526        <crate::RegValueT<PllSysCtrl2Reg_SPEC> as RegisterValue<_>>::new(8198)
527    }
528}
529
530#[doc(hidden)]
531#[derive(Copy, Clone, Eq, PartialEq)]
532pub struct PllSysCtrl3Reg_SPEC;
533impl crate::sealed::RegSpec for PllSysCtrl3Reg_SPEC {
534    type DataType = u16;
535}
536
537#[doc = "System PLL control register 3."]
538pub type PllSysCtrl3Reg = crate::RegValueT<PllSysCtrl3Reg_SPEC>;
539
540impl PllSysCtrl3Reg {
541    #[doc = "Recalibrate"]
542    #[inline(always)]
543    pub fn pll_recalib(
544        self,
545    ) -> crate::common::RegisterFieldBool<15, 1, 0, PllSysCtrl3Reg_SPEC, crate::common::RW> {
546        crate::common::RegisterFieldBool::<15,1,0,PllSysCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
547    }
548
549    #[doc = "Programmable delay time for the loop filter voltage preset value. After PLL_EN is set, the loopfilter precharge resistors are disabled after this delay time. One LSB is 48 ns"]
550    #[inline(always)]
551    pub fn pll_start_del(
552        self,
553    ) -> crate::common::RegisterField<10, 0x1f, 1, 0, u8, u8, PllSysCtrl3Reg_SPEC, crate::common::RW>
554    {
555        crate::common::RegisterField::<10,0x1f,1,0,u8,u8,PllSysCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
556    }
557
558    #[doc = "PLL charge pump current select\nOne LSB is 5uA."]
559    #[inline(always)]
560    pub fn pll_icp_sel(
561        self,
562    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, PllSysCtrl3Reg_SPEC, crate::common::RW>
563    {
564        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,PllSysCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
565    }
566}
567impl ::core::default::Default for PllSysCtrl3Reg {
568    #[inline(always)]
569    fn default() -> PllSysCtrl3Reg {
570        <crate::RegValueT<PllSysCtrl3Reg_SPEC> as RegisterValue<_>>::new(15369)
571    }
572}
573
574#[doc(hidden)]
575#[derive(Copy, Clone, Eq, PartialEq)]
576pub struct PllSysStatusReg_SPEC;
577impl crate::sealed::RegSpec for PllSysStatusReg_SPEC {
578    type DataType = u16;
579}
580
581#[doc = "System PLL status register."]
582pub type PllSysStatusReg = crate::RegValueT<PllSysStatusReg_SPEC>;
583
584impl PllSysStatusReg {
585    #[doc = "Indicates that calibration has finished."]
586    #[inline(always)]
587    pub fn pll_calibr_end(
588        self,
589    ) -> crate::common::RegisterFieldBool<11, 1, 0, PllSysStatusReg_SPEC, crate::common::R> {
590        crate::common::RegisterFieldBool::<11,1,0,PllSysStatusReg_SPEC,crate::common::R>::from_register(self,0)
591    }
592
593    #[doc = "Calibrated VCO frequency band."]
594    #[inline(always)]
595    pub fn pll_pll_best_min_cur(
596        self,
597    ) -> crate::common::RegisterField<5, 0x3f, 1, 0, u8, u8, PllSysStatusReg_SPEC, crate::common::R>
598    {
599        crate::common::RegisterField::<5,0x3f,1,0,u8,u8,PllSysStatusReg_SPEC,crate::common::R>::from_register(self,0)
600    }
601
602    #[doc = "1: Indicates that LDO PLL is in regulation."]
603    #[inline(always)]
604    pub fn ldo_pll_ok(
605        self,
606    ) -> crate::common::RegisterFieldBool<1, 1, 0, PllSysStatusReg_SPEC, crate::common::R> {
607        crate::common::RegisterFieldBool::<1,1,0,PllSysStatusReg_SPEC,crate::common::R>::from_register(self,0)
608    }
609
610    #[doc = "1: PLL locked"]
611    #[inline(always)]
612    pub fn pll_lock_fine(
613        self,
614    ) -> crate::common::RegisterFieldBool<0, 1, 0, PllSysStatusReg_SPEC, crate::common::R> {
615        crate::common::RegisterFieldBool::<0,1,0,PllSysStatusReg_SPEC,crate::common::R>::from_register(self,0)
616    }
617}
618impl ::core::default::Default for PllSysStatusReg {
619    #[inline(always)]
620    fn default() -> PllSysStatusReg {
621        <crate::RegValueT<PllSysStatusReg_SPEC> as RegisterValue<_>>::new(0)
622    }
623}
624
625#[doc(hidden)]
626#[derive(Copy, Clone, Eq, PartialEq)]
627pub struct PllSysTestReg_SPEC;
628impl crate::sealed::RegSpec for PllSysTestReg_SPEC {
629    type DataType = u16;
630}
631
632#[doc = "System PLL test register."]
633pub type PllSysTestReg = crate::RegValueT<PllSysTestReg_SPEC>;
634
635impl PllSysTestReg {
636    #[doc = "Lock measurement time in <tbd> clock cycle of xx usec. After this period PLL_LOCK_FINE is calculated based on the difference of the M and N counted pulses in that period. If PLL_LOCK_FINE is still 0, the lock state machine restarts until PLL_LOCK_FINE gets 1\n0: <tbd> usec\n7: <tbd> usec"]
637    #[inline(always)]
638    pub fn pll_lock_det_res_cnt(
639        self,
640    ) -> crate::common::RegisterField<13, 0x7, 1, 0, u8, u8, PllSysTestReg_SPEC, crate::common::RW>
641    {
642        crate::common::RegisterField::<13,0x7,1,0,u8,u8,PllSysTestReg_SPEC,crate::common::RW>::from_register(self,0)
643    }
644
645    #[doc = "Select test mode for output divider R\nMaps PLL_R_DIV input on pins <tbd> and divider output on pin <tbd>"]
646    #[inline(always)]
647    pub fn pll_sel_r_div_test(
648        self,
649    ) -> crate::common::RegisterFieldBool<11, 1, 0, PllSysTestReg_SPEC, crate::common::RW> {
650        crate::common::RegisterFieldBool::<11,1,0,PllSysTestReg_SPEC,crate::common::RW>::from_register(self,0)
651    }
652
653    #[doc = "Select test mode for loop divider N.\nMaps PLL_N_DIV input on pins <tbd> and divider output on pin <tbd>"]
654    #[inline(always)]
655    pub fn pll_sel_n_div_test(
656        self,
657    ) -> crate::common::RegisterFieldBool<10, 1, 0, PllSysTestReg_SPEC, crate::common::RW> {
658        crate::common::RegisterFieldBool::<10,1,0,PllSysTestReg_SPEC,crate::common::RW>::from_register(self,0)
659    }
660
661    #[doc = "0: normal value\n1: reverse charge pump up/down signals"]
662    #[inline(always)]
663    pub fn pll_change(
664        self,
665    ) -> crate::common::RegisterFieldBool<9, 1, 0, PllSysTestReg_SPEC, crate::common::RW> {
666        crate::common::RegisterFieldBool::<9,1,0,PllSysTestReg_SPEC,crate::common::RW>::from_register(self,0)
667    }
668
669    #[doc = "1: set to open loop to termine max frequency"]
670    #[inline(always)]
671    pub fn pll_open_loop(
672        self,
673    ) -> crate::common::RegisterFieldBool<8, 1, 0, PllSysTestReg_SPEC, crate::common::RW> {
674        crate::common::RegisterFieldBool::<8,1,0,PllSysTestReg_SPEC,crate::common::RW>::from_register(self,0)
675    }
676
677    #[doc = "1: map loopfilter voltage on external pin <tbd>"]
678    #[inline(always)]
679    pub fn pll_test_vctr(
680        self,
681    ) -> crate::common::RegisterFieldBool<7, 1, 0, PllSysTestReg_SPEC, crate::common::RW> {
682        crate::common::RegisterFieldBool::<7,1,0,PllSysTestReg_SPEC,crate::common::RW>::from_register(self,0)
683    }
684
685    #[doc = "VCO current trimming."]
686    #[inline(always)]
687    pub fn pll_min_current(
688        self,
689    ) -> crate::common::RegisterField<1, 0x3f, 1, 0, u8, u8, PllSysTestReg_SPEC, crate::common::RW>
690    {
691        crate::common::RegisterField::<1,0x3f,1,0,u8,u8,PllSysTestReg_SPEC,crate::common::RW>::from_register(self,0)
692    }
693
694    #[doc = "1: disable PLL internal loop filter"]
695    #[inline(always)]
696    pub fn pll_dis_loopfilt(
697        self,
698    ) -> crate::common::RegisterFieldBool<0, 1, 0, PllSysTestReg_SPEC, crate::common::RW> {
699        crate::common::RegisterFieldBool::<0,1,0,PllSysTestReg_SPEC,crate::common::RW>::from_register(self,0)
700    }
701}
702impl ::core::default::Default for PllSysTestReg {
703    #[inline(always)]
704    fn default() -> PllSysTestReg {
705        <crate::RegValueT<PllSysTestReg_SPEC> as RegisterValue<_>>::new(112)
706    }
707}
708
709#[doc(hidden)]
710#[derive(Copy, Clone, Eq, PartialEq)]
711pub struct ResetFreezeReg_SPEC;
712impl crate::sealed::RegSpec for ResetFreezeReg_SPEC {
713    type DataType = u16;
714}
715
716#[doc = "Controls unfreezing of various timers/counters (incl. DMA and USB)."]
717pub type ResetFreezeReg = crate::RegValueT<ResetFreezeReg_SPEC>;
718
719impl ResetFreezeReg {
720    #[doc = "If \'1\', the SW Timer (TIMER2) continues, \'0\' is discarded."]
721    #[inline(always)]
722    pub fn frz_swtim2(
723        self,
724    ) -> crate::common::RegisterFieldBool<7, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
725        crate::common::RegisterFieldBool::<7,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
726    }
727
728    #[doc = "If \'1\', the SW Timer (TIMER1) continues, \'0\' is discarded."]
729    #[inline(always)]
730    pub fn frz_swtim1(
731        self,
732    ) -> crate::common::RegisterFieldBool<6, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
733        crate::common::RegisterFieldBool::<6,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
734    }
735
736    #[doc = "If \'1\', the DMA continues, \'0\' is discarded."]
737    #[inline(always)]
738    pub fn frz_dma(
739        self,
740    ) -> crate::common::RegisterFieldBool<5, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
741        crate::common::RegisterFieldBool::<5,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
742    }
743
744    #[doc = "If \'1\', the USB continues, \'0\' is discarded."]
745    #[inline(always)]
746    pub fn frz_usb(
747        self,
748    ) -> crate::common::RegisterFieldBool<4, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
749        crate::common::RegisterFieldBool::<4,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
750    }
751
752    #[doc = "If \'1\', the watchdog timer continues, \'0\' is discarded."]
753    #[inline(always)]
754    pub fn frz_wdog(
755        self,
756    ) -> crate::common::RegisterFieldBool<3, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
757        crate::common::RegisterFieldBool::<3,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
758    }
759
760    #[doc = "If \'1\', the BLE master clock continues, \'0\' is discarded."]
761    #[inline(always)]
762    pub fn frz_bletim(
763        self,
764    ) -> crate::common::RegisterFieldBool<2, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
765        crate::common::RegisterFieldBool::<2,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
766    }
767
768    #[doc = "If \'1\', the SW Timer (TIMER0) continues, \'0\' is discarded."]
769    #[inline(always)]
770    pub fn frz_swtim0(
771        self,
772    ) -> crate::common::RegisterFieldBool<1, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
773        crate::common::RegisterFieldBool::<1,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
774    }
775
776    #[doc = "If \'1\', the Wake Up Timer continues, \'0\' is discarded."]
777    #[inline(always)]
778    pub fn frz_wkuptim(
779        self,
780    ) -> crate::common::RegisterFieldBool<0, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
781        crate::common::RegisterFieldBool::<0,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
782    }
783}
784impl ::core::default::Default for ResetFreezeReg {
785    #[inline(always)]
786    fn default() -> ResetFreezeReg {
787        <crate::RegValueT<ResetFreezeReg_SPEC> as RegisterValue<_>>::new(0)
788    }
789}
790
791#[doc(hidden)]
792#[derive(Copy, Clone, Eq, PartialEq)]
793pub struct SetFreezeReg_SPEC;
794impl crate::sealed::RegSpec for SetFreezeReg_SPEC {
795    type DataType = u16;
796}
797
798#[doc = "Controls freezing of various timers/counters (incl. DMA and USB)."]
799pub type SetFreezeReg = crate::RegValueT<SetFreezeReg_SPEC>;
800
801impl SetFreezeReg {
802    #[doc = "If \'1\', the SW Timer (TIMER2) is frozen, \'0\' is discarded."]
803    #[inline(always)]
804    pub fn frz_swtim2(
805        self,
806    ) -> crate::common::RegisterFieldBool<7, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
807        crate::common::RegisterFieldBool::<7,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
808    }
809
810    #[doc = "If \'1\', the SW Timer (TIMER1) is frozen, \'0\' is discarded."]
811    #[inline(always)]
812    pub fn frz_swtim1(
813        self,
814    ) -> crate::common::RegisterFieldBool<6, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
815        crate::common::RegisterFieldBool::<6,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
816    }
817
818    #[doc = "If \'1\', the DMA is frozen, \'0\' is discarded."]
819    #[inline(always)]
820    pub fn frz_dma(
821        self,
822    ) -> crate::common::RegisterFieldBool<5, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
823        crate::common::RegisterFieldBool::<5,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
824    }
825
826    #[doc = "If \'1\', the USB is frozen, \'0\' is discarded."]
827    #[inline(always)]
828    pub fn frz_usb(
829        self,
830    ) -> crate::common::RegisterFieldBool<4, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
831        crate::common::RegisterFieldBool::<4,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
832    }
833
834    #[doc = "If \'1\', the watchdog timer is frozen, \'0\' is discarded. WATCHDOG_CTRL_REG\\[NMI_RST\\] must be \'0\' to allow the freeze function."]
835    #[inline(always)]
836    pub fn frz_wdog(
837        self,
838    ) -> crate::common::RegisterFieldBool<3, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
839        crate::common::RegisterFieldBool::<3,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
840    }
841
842    #[doc = "If \'1\', the BLE master clock is frozen, \'0\' is discarded."]
843    #[inline(always)]
844    pub fn frz_bletim(
845        self,
846    ) -> crate::common::RegisterFieldBool<2, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
847        crate::common::RegisterFieldBool::<2,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
848    }
849
850    #[doc = "If \'1\', the SW Timer (TIMER0) is frozen, \'0\' is discarded."]
851    #[inline(always)]
852    pub fn frz_swtim0(
853        self,
854    ) -> crate::common::RegisterFieldBool<1, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
855        crate::common::RegisterFieldBool::<1,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
856    }
857
858    #[doc = "If \'1\', the Wake Up Timer is frozen, \'0\' is discarded."]
859    #[inline(always)]
860    pub fn frz_wkuptim(
861        self,
862    ) -> crate::common::RegisterFieldBool<0, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
863        crate::common::RegisterFieldBool::<0,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
864    }
865}
866impl ::core::default::Default for SetFreezeReg {
867    #[inline(always)]
868    fn default() -> SetFreezeReg {
869        <crate::RegValueT<SetFreezeReg_SPEC> as RegisterValue<_>>::new(0)
870    }
871}
da14682_pac/gpreg.rs

da14682_pac/
gpreg.rs
