da14682_pac/
cache.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:10 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"CACHE registers"]
28unsafe impl ::core::marker::Send for super::Cache {}
29unsafe impl ::core::marker::Sync for super::Cache {}
30impl super::Cache {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Cache associativity configuration register"]
38    #[inline(always)]
39    pub const fn cache_assoccfg_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::CacheAssoccfgReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::CacheAssoccfgReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(8usize),
45            )
46        }
47    }
48
49    #[doc = "Cache control register 1"]
50    #[inline(always)]
51    pub const fn cache_ctrl1_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::CacheCtrl1Reg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::CacheCtrl1Reg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0usize),
57            )
58        }
59    }
60
61    #[doc = "Cache control register 2"]
62    #[inline(always)]
63    pub const fn cache_ctrl2_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::CacheCtrl2Reg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::CacheCtrl2Reg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(32usize),
69            )
70        }
71    }
72
73    #[doc = "Cache line size configuration register"]
74    #[inline(always)]
75    pub const fn cache_lnsizecfg_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::CacheLnsizecfgReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::CacheLnsizecfgReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(4usize),
81            )
82        }
83    }
84
85    #[doc = "Cache MRM (Miss Rate Monitor) CONTROL register"]
86    #[inline(always)]
87    pub const fn cache_mrm_ctrl_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::CacheMrmCtrlReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::CacheMrmCtrlReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(48usize),
93            )
94        }
95    }
96
97    #[doc = "Cache MRM (Miss Rate Monitor) HITS register"]
98    #[inline(always)]
99    pub const fn cache_mrm_hits_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::CacheMrmHitsReg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::CacheMrmHitsReg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(40usize),
105            )
106        }
107    }
108
109    #[doc = "Cache MRM (Miss Rate Monitor) MISSES register"]
110    #[inline(always)]
111    pub const fn cache_mrm_misses_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::CacheMrmMissesReg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::CacheMrmMissesReg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(44usize),
117            )
118        }
119    }
120
121    #[doc = "Cache MRM (Miss Rate Monitor) THRESHOLD register"]
122    #[inline(always)]
123    pub const fn cache_mrm_thres_reg(
124        &self,
125    ) -> &'static crate::common::Reg<self::CacheMrmThresReg_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::CacheMrmThresReg_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(56usize),
129            )
130        }
131    }
132
133    #[doc = "Cache MRM (Miss Rate Monitor) TIME INTERVAL register"]
134    #[inline(always)]
135    pub const fn cache_mrm_tint_reg(
136        &self,
137    ) -> &'static crate::common::Reg<self::CacheMrmTintReg_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::CacheMrmTintReg_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(52usize),
141            )
142        }
143    }
144
145    #[doc = "SWD HW reset control register"]
146    #[inline(always)]
147    pub const fn swd_reset_reg(
148        &self,
149    ) -> &'static crate::common::Reg<self::SwdResetReg_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::SwdResetReg_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(80usize),
153            )
154        }
155    }
156}
157#[doc(hidden)]
158#[derive(Copy, Clone, Eq, PartialEq)]
159pub struct CacheAssoccfgReg_SPEC;
160impl crate::sealed::RegSpec for CacheAssoccfgReg_SPEC {
161    type DataType = u32;
162}
163
164#[doc = "Cache associativity configuration register"]
165pub type CacheAssoccfgReg = crate::RegValueT<CacheAssoccfgReg_SPEC>;
166
167impl CacheAssoccfgReg {
168    #[doc = "Cache associativity:\n0: 1-way (direct mapped)\n1: 2-way\n2: 4-way\n3: reserved.\nNote: Flush the cache controller before dynamically decreasing the associativity."]
169    #[inline(always)]
170    pub fn cache_assoc(
171        self,
172    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, CacheAssoccfgReg_SPEC, crate::common::RW>
173    {
174        crate::common::RegisterField::<0,0x3,1,0,u8,u8,CacheAssoccfgReg_SPEC,crate::common::RW>::from_register(self,0)
175    }
176}
177impl ::core::default::Default for CacheAssoccfgReg {
178    #[inline(always)]
179    fn default() -> CacheAssoccfgReg {
180        <crate::RegValueT<CacheAssoccfgReg_SPEC> as RegisterValue<_>>::new(2)
181    }
182}
183
184#[doc(hidden)]
185#[derive(Copy, Clone, Eq, PartialEq)]
186pub struct CacheCtrl1Reg_SPEC;
187impl crate::sealed::RegSpec for CacheCtrl1Reg_SPEC {
188    type DataType = u32;
189}
190
191#[doc = "Cache control register 1"]
192pub type CacheCtrl1Reg = crate::RegValueT<CacheCtrl1Reg_SPEC>;
193
194impl CacheCtrl1Reg {
195    #[doc = "Reserved. Always keep 0."]
196    #[inline(always)]
197    pub fn cache_res1(
198        self,
199    ) -> crate::common::RegisterFieldBool<1, 1, 0, CacheCtrl1Reg_SPEC, crate::common::RW> {
200        crate::common::RegisterFieldBool::<1,1,0,CacheCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
201    }
202
203    #[doc = "Writing a \'1\' into this bit, flushes the contents of the tag memories which invalidates the content of the cache memory.\nThe read of this bit is always \'0\'.\nNote: The flushing of the cache TAG memory takes 0x100 or 0x200 HCLK cycles for a Cache Data RAM size of 8 KB resp. 16 KB."]
204    #[inline(always)]
205    pub fn cache_flush(
206        self,
207    ) -> crate::common::RegisterFieldBool<0, 1, 0, CacheCtrl1Reg_SPEC, crate::common::W> {
208        crate::common::RegisterFieldBool::<0,1,0,CacheCtrl1Reg_SPEC,crate::common::W>::from_register(self,0)
209    }
210}
211impl ::core::default::Default for CacheCtrl1Reg {
212    #[inline(always)]
213    fn default() -> CacheCtrl1Reg {
214        <crate::RegValueT<CacheCtrl1Reg_SPEC> as RegisterValue<_>>::new(0)
215    }
216}
217
218#[doc(hidden)]
219#[derive(Copy, Clone, Eq, PartialEq)]
220pub struct CacheCtrl2Reg_SPEC;
221impl crate::sealed::RegSpec for CacheCtrl2Reg_SPEC {
222    type DataType = u32;
223}
224
225#[doc = "Cache control register 2"]
226pub type CacheCtrl2Reg = crate::RegValueT<CacheCtrl2Reg_SPEC>;
227
228impl CacheCtrl2Reg {
229    #[doc = "Enable also the QSPI FLASH cacheability when remapped to OTP (cached).\nSee also the notes at \"CACHE_LEN\"."]
230    #[inline(always)]
231    pub fn enable_also_qspiflash_cached(
232        self,
233    ) -> crate::common::RegisterFieldBool<12, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
234        crate::common::RegisterFieldBool::<12,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
235    }
236
237    #[doc = "Enable also the OTP cacheability when remapped to QSPI FLASH (cached).\nSee also the notes at \"CACHE_LEN\"."]
238    #[inline(always)]
239    pub fn enable_also_otp_cached(
240        self,
241    ) -> crate::common::RegisterFieldBool<11, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
242        crate::common::RegisterFieldBool::<11,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
243    }
244
245    #[doc = "0: Cache controller clock gating is not enabled.\n1: Cache controller clock gating is enabled (enabling power saving).\nNote: This bit must be set to \'0\' (default) when setting the CACHE_FLUSH bit while executing from other than QSPI FLASH cached or OTP cached, e.g. from Booter or SYSRAM."]
246    #[inline(always)]
247    pub fn cache_cgen(
248        self,
249    ) -> crate::common::RegisterFieldBool<10, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
250        crate::common::RegisterFieldBool::<10,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
251    }
252
253    #[doc = "0: Cache Data and TAG memory read only.\n1: Cache Data and TAG memory read/write.\nThe TAG and Data memory are only updated by the cache controller.\nThere is no HW protection to prevent unauthorized access by the ARM.\nNote: When accessing the memory mapped Cache Data and TAG memory (for debugging purposes) only 32 bits access is allowed to the Cache Data memory and only 16 bits access is allowed to the Cache TAG memory."]
254    #[inline(always)]
255    pub fn cache_wen(
256        self,
257    ) -> crate::common::RegisterFieldBool<9, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
258        crate::common::RegisterFieldBool::<9,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
259    }
260
261    #[doc = "Length of QSPI FLASH cacheable memory.\n(N+1)*64kbyte. N=1 to 512 (Max of 32 Mbyte).\nSetting CACHE_LEN=0 disables the cache.\nNote 1: The OTP memory is completely cacheable (when enabled).\nNote 2: The max. size/length of QSPI FLASH cacheable memory is 16 Mbyte when also OTP is cached."]
262    #[inline(always)]
263    pub fn cache_len(
264        self,
265    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, CacheCtrl2Reg_SPEC, crate::common::RW>
266    {
267        crate::common::RegisterField::<
268            0,
269            0x1ff,
270            1,
271            0,
272            u16,
273            u16,
274            CacheCtrl2Reg_SPEC,
275            crate::common::RW,
276        >::from_register(self, 0)
277    }
278}
279impl ::core::default::Default for CacheCtrl2Reg {
280    #[inline(always)]
281    fn default() -> CacheCtrl2Reg {
282        <crate::RegValueT<CacheCtrl2Reg_SPEC> as RegisterValue<_>>::new(0)
283    }
284}
285
286#[doc(hidden)]
287#[derive(Copy, Clone, Eq, PartialEq)]
288pub struct CacheLnsizecfgReg_SPEC;
289impl crate::sealed::RegSpec for CacheLnsizecfgReg_SPEC {
290    type DataType = u32;
291}
292
293#[doc = "Cache line size configuration register"]
294pub type CacheLnsizecfgReg = crate::RegValueT<CacheLnsizecfgReg_SPEC>;
295
296impl CacheLnsizecfgReg {
297    #[doc = "Cache line size:\n0: 8 bytes,\n1: 16 bytes,\n2: 32 bytes,\n3: reserved.\nNote: Flush the cache just after the dynamic (run-time) reconfiguration of the cache with an 8 bytes cache line size: write the value \"01\" into the cache control register CACHE_CTRL1_REG just after the write of the value \"00\" into the cache line size configuration register CACHE_LNSIZECFG_REG."]
298    #[inline(always)]
299    pub fn cache_line(
300        self,
301    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, CacheLnsizecfgReg_SPEC, crate::common::RW>
302    {
303        crate::common::RegisterField::<
304            0,
305            0x3,
306            1,
307            0,
308            u8,
309            u8,
310            CacheLnsizecfgReg_SPEC,
311            crate::common::RW,
312        >::from_register(self, 0)
313    }
314}
315impl ::core::default::Default for CacheLnsizecfgReg {
316    #[inline(always)]
317    fn default() -> CacheLnsizecfgReg {
318        <crate::RegValueT<CacheLnsizecfgReg_SPEC> as RegisterValue<_>>::new(0)
319    }
320}
321
322#[doc(hidden)]
323#[derive(Copy, Clone, Eq, PartialEq)]
324pub struct CacheMrmCtrlReg_SPEC;
325impl crate::sealed::RegSpec for CacheMrmCtrlReg_SPEC {
326    type DataType = u32;
327}
328
329#[doc = "Cache MRM (Miss Rate Monitor) CONTROL register"]
330pub type CacheMrmCtrlReg = crate::RegValueT<CacheMrmCtrlReg_SPEC>;
331
332impl CacheMrmCtrlReg {
333    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the number of cache misses reached the programmed threshold (threshold != 0)."]
334    #[inline(always)]
335    pub fn mrm_irq_thres_status(
336        self,
337    ) -> crate::common::RegisterFieldBool<3, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
338        crate::common::RegisterFieldBool::<3,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
339    }
340
341    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the time interval counter reached the end (time interval != 0)."]
342    #[inline(always)]
343    pub fn mrm_irq_tint_status(
344        self,
345    ) -> crate::common::RegisterFieldBool<2, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
346        crate::common::RegisterFieldBool::<2,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
347    }
348
349    #[doc = "0: Disables interrupt generation.\n1: Enables interrupt generation.\nNote: The Cache MRM generates a pulse-sensitive interrupt towards the ARM processor,"]
350    #[inline(always)]
351    pub fn mrm_irq_mask(
352        self,
353    ) -> crate::common::RegisterFieldBool<1, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
354        crate::common::RegisterFieldBool::<1,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
355    }
356
357    #[doc = "0: Freeze the \"misses/hits\" counters and reset the time interval counter to the programmed value in CACHE_MRM_TINT_REG.\n1: Enables the counters.\nNote: In case CACHE_MRM_CTRL_REG\\[MRM_START\\] is set to \'1\' and CACHE_MRM_TINT_REG (!=0) is used for the MRM interrupt generation, the time interval counter counts down (on a fixed reference clock of 16 MHz) until it\'s \'0\'. At that time CACHE_MRM_CTRL_REG\\[MRM_START\\] will be reset automatically to \'0\' by the MRM hardware and the MRM interrupt will be generated."]
358    #[inline(always)]
359    pub fn mrm_start(
360        self,
361    ) -> crate::common::RegisterFieldBool<0, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
362        crate::common::RegisterFieldBool::<0,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
363    }
364}
365impl ::core::default::Default for CacheMrmCtrlReg {
366    #[inline(always)]
367    fn default() -> CacheMrmCtrlReg {
368        <crate::RegValueT<CacheMrmCtrlReg_SPEC> as RegisterValue<_>>::new(0)
369    }
370}
371
372#[doc(hidden)]
373#[derive(Copy, Clone, Eq, PartialEq)]
374pub struct CacheMrmHitsReg_SPEC;
375impl crate::sealed::RegSpec for CacheMrmHitsReg_SPEC {
376    type DataType = u32;
377}
378
379#[doc = "Cache MRM (Miss Rate Monitor) HITS register"]
380pub type CacheMrmHitsReg = crate::RegValueT<CacheMrmHitsReg_SPEC>;
381
382impl CacheMrmHitsReg {
383    #[doc = "Contains the amount of cache hits."]
384    #[inline(always)]
385    pub fn mrm_hits(
386        self,
387    ) -> crate::common::RegisterField<
388        0,
389        0x7ffff,
390        1,
391        0,
392        u32,
393        u32,
394        CacheMrmHitsReg_SPEC,
395        crate::common::RW,
396    > {
397        crate::common::RegisterField::<
398            0,
399            0x7ffff,
400            1,
401            0,
402            u32,
403            u32,
404            CacheMrmHitsReg_SPEC,
405            crate::common::RW,
406        >::from_register(self, 0)
407    }
408}
409impl ::core::default::Default for CacheMrmHitsReg {
410    #[inline(always)]
411    fn default() -> CacheMrmHitsReg {
412        <crate::RegValueT<CacheMrmHitsReg_SPEC> as RegisterValue<_>>::new(0)
413    }
414}
415
416#[doc(hidden)]
417#[derive(Copy, Clone, Eq, PartialEq)]
418pub struct CacheMrmMissesReg_SPEC;
419impl crate::sealed::RegSpec for CacheMrmMissesReg_SPEC {
420    type DataType = u32;
421}
422
423#[doc = "Cache MRM (Miss Rate Monitor) MISSES register"]
424pub type CacheMrmMissesReg = crate::RegValueT<CacheMrmMissesReg_SPEC>;
425
426impl CacheMrmMissesReg {
427    #[doc = "Contains the amount of cache misses."]
428    #[inline(always)]
429    pub fn mrm_misses(
430        self,
431    ) -> crate::common::RegisterField<
432        0,
433        0x3ffff,
434        1,
435        0,
436        u32,
437        u32,
438        CacheMrmMissesReg_SPEC,
439        crate::common::RW,
440    > {
441        crate::common::RegisterField::<
442            0,
443            0x3ffff,
444            1,
445            0,
446            u32,
447            u32,
448            CacheMrmMissesReg_SPEC,
449            crate::common::RW,
450        >::from_register(self, 0)
451    }
452}
453impl ::core::default::Default for CacheMrmMissesReg {
454    #[inline(always)]
455    fn default() -> CacheMrmMissesReg {
456        <crate::RegValueT<CacheMrmMissesReg_SPEC> as RegisterValue<_>>::new(0)
457    }
458}
459
460#[doc(hidden)]
461#[derive(Copy, Clone, Eq, PartialEq)]
462pub struct CacheMrmThresReg_SPEC;
463impl crate::sealed::RegSpec for CacheMrmThresReg_SPEC {
464    type DataType = u32;
465}
466
467#[doc = "Cache MRM (Miss Rate Monitor) THRESHOLD register"]
468pub type CacheMrmThresReg = crate::RegValueT<CacheMrmThresReg_SPEC>;
469
470impl CacheMrmThresReg {
471    #[doc = "Defines the threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_THRES_STATUS\\].\nNote: When MRM_THRES=0 (unrealistic value), no interrupt will be generated."]
472    #[inline(always)]
473    pub fn mrm_thres(
474        self,
475    ) -> crate::common::RegisterField<
476        0,
477        0x3ffff,
478        1,
479        0,
480        u32,
481        u32,
482        CacheMrmThresReg_SPEC,
483        crate::common::RW,
484    > {
485        crate::common::RegisterField::<
486            0,
487            0x3ffff,
488            1,
489            0,
490            u32,
491            u32,
492            CacheMrmThresReg_SPEC,
493            crate::common::RW,
494        >::from_register(self, 0)
495    }
496}
497impl ::core::default::Default for CacheMrmThresReg {
498    #[inline(always)]
499    fn default() -> CacheMrmThresReg {
500        <crate::RegValueT<CacheMrmThresReg_SPEC> as RegisterValue<_>>::new(0)
501    }
502}
503
504#[doc(hidden)]
505#[derive(Copy, Clone, Eq, PartialEq)]
506pub struct CacheMrmTintReg_SPEC;
507impl crate::sealed::RegSpec for CacheMrmTintReg_SPEC {
508    type DataType = u32;
509}
510
511#[doc = "Cache MRM (Miss Rate Monitor) TIME INTERVAL register"]
512pub type CacheMrmTintReg = crate::RegValueT<CacheMrmTintReg_SPEC>;
513
514impl CacheMrmTintReg {
515    #[doc = "Defines the time interval for the monitoring in 16 MHz clock cycles. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_TINT_STATUS\\].\nNote: When MRM_TINT=0 (unrealistic value), no interrupt will be generated."]
516    #[inline(always)]
517    pub fn mrm_tint(
518        self,
519    ) -> crate::common::RegisterField<
520        0,
521        0x3ffff,
522        1,
523        0,
524        u32,
525        u32,
526        CacheMrmTintReg_SPEC,
527        crate::common::RW,
528    > {
529        crate::common::RegisterField::<
530            0,
531            0x3ffff,
532            1,
533            0,
534            u32,
535            u32,
536            CacheMrmTintReg_SPEC,
537            crate::common::RW,
538        >::from_register(self, 0)
539    }
540}
541impl ::core::default::Default for CacheMrmTintReg {
542    #[inline(always)]
543    fn default() -> CacheMrmTintReg {
544        <crate::RegValueT<CacheMrmTintReg_SPEC> as RegisterValue<_>>::new(0)
545    }
546}
547
548#[doc(hidden)]
549#[derive(Copy, Clone, Eq, PartialEq)]
550pub struct SwdResetReg_SPEC;
551impl crate::sealed::RegSpec for SwdResetReg_SPEC {
552    type DataType = u32;
553}
554
555#[doc = "SWD HW reset control register"]
556pub type SwdResetReg = crate::RegValueT<SwdResetReg_SPEC>;
557
558impl SwdResetReg {
559    #[doc = "0: default.\n1: HW reset request without resetting the SWD and DAP controller. The register is automatically reset with a HW_RESET.\nThis bit can only be accessed by the debugger software and not by the application."]
560    #[inline(always)]
561    pub fn swd_hw_reset_req(
562        self,
563    ) -> crate::common::RegisterFieldBool<0, 1, 0, SwdResetReg_SPEC, crate::common::W> {
564        crate::common::RegisterFieldBool::<0,1,0,SwdResetReg_SPEC,crate::common::W>::from_register(self,0)
565    }
566}
567impl ::core::default::Default for SwdResetReg {
568    #[inline(always)]
569    fn default() -> SwdResetReg {
570        <crate::RegValueT<SwdResetReg_SPEC> as RegisterValue<_>>::new(0)
571    }
572}
da14682_pac/cache.rs

da14682_pac/
cache.rs
