1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"APU registers"]
28unsafe impl ::core::marker::Send for super::Apu {}
29unsafe impl ::core::marker::Sync for super::Apu {}
30impl super::Apu {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "APU mux register"]
38 #[inline(always)]
39 pub const fn apu_mux_reg(
40 &self,
41 ) -> &'static crate::common::Reg<self::ApuMuxReg_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::ApuMuxReg_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(28usize),
45 )
46 }
47 }
48
49 #[doc = "SRC coefficient 10 set 1"]
50 #[inline(always)]
51 pub const fn coef0a_set1_reg(
52 &self,
53 ) -> &'static crate::common::Reg<self::Coef0ASet1Reg_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::Coef0ASet1Reg_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(52usize),
57 )
58 }
59 }
60
61 #[doc = "SRC coefficient 1,0 set 1"]
62 #[inline(always)]
63 pub const fn coef10_set1_reg(
64 &self,
65 ) -> &'static crate::common::Reg<self::Coef10Set1Reg_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::Coef10Set1Reg_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(32usize),
69 )
70 }
71 }
72
73 #[doc = "SRC coefficient 3,2 set 1"]
74 #[inline(always)]
75 pub const fn coef32_set1_reg(
76 &self,
77 ) -> &'static crate::common::Reg<self::Coef32Set1Reg_SPEC, crate::common::RW> {
78 unsafe {
79 crate::common::Reg::<self::Coef32Set1Reg_SPEC, crate::common::RW>::from_ptr(
80 self._svd2pac_as_ptr().add(36usize),
81 )
82 }
83 }
84
85 #[doc = "SRC coefficient 5,4 set 1"]
86 #[inline(always)]
87 pub const fn coef54_set1_reg(
88 &self,
89 ) -> &'static crate::common::Reg<self::Coef54Set1Reg_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::Coef54Set1Reg_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(40usize),
93 )
94 }
95 }
96
97 #[doc = "SRC coefficient 7,6 set 1"]
98 #[inline(always)]
99 pub const fn coef76_set1_reg(
100 &self,
101 ) -> &'static crate::common::Reg<self::Coef76Set1Reg_SPEC, crate::common::RW> {
102 unsafe {
103 crate::common::Reg::<self::Coef76Set1Reg_SPEC, crate::common::RW>::from_ptr(
104 self._svd2pac_as_ptr().add(44usize),
105 )
106 }
107 }
108
109 #[doc = "SRC coefficient 9,8 set 1"]
110 #[inline(always)]
111 pub const fn coef98_set1_reg(
112 &self,
113 ) -> &'static crate::common::Reg<self::Coef98Set1Reg_SPEC, crate::common::RW> {
114 unsafe {
115 crate::common::Reg::<self::Coef98Set1Reg_SPEC, crate::common::RW>::from_ptr(
116 self._svd2pac_as_ptr().add(48usize),
117 )
118 }
119 }
120
121 #[doc = "PCM1 Control register"]
122 #[inline(always)]
123 pub const fn pcm1_ctrl_reg(
124 &self,
125 ) -> &'static crate::common::Reg<self::Pcm1CtrlReg_SPEC, crate::common::RW> {
126 unsafe {
127 crate::common::Reg::<self::Pcm1CtrlReg_SPEC, crate::common::RW>::from_ptr(
128 self._svd2pac_as_ptr().add(256usize),
129 )
130 }
131 }
132
133 #[doc = "PCM1 data in 1"]
134 #[inline(always)]
135 pub const fn pcm1_in1_reg(
136 &self,
137 ) -> &'static crate::common::Reg<self::Pcm1In1Reg_SPEC, crate::common::RW> {
138 unsafe {
139 crate::common::Reg::<self::Pcm1In1Reg_SPEC, crate::common::RW>::from_ptr(
140 self._svd2pac_as_ptr().add(260usize),
141 )
142 }
143 }
144
145 #[doc = "PCM1 data in 2"]
146 #[inline(always)]
147 pub const fn pcm1_in2_reg(
148 &self,
149 ) -> &'static crate::common::Reg<self::Pcm1In2Reg_SPEC, crate::common::RW> {
150 unsafe {
151 crate::common::Reg::<self::Pcm1In2Reg_SPEC, crate::common::RW>::from_ptr(
152 self._svd2pac_as_ptr().add(264usize),
153 )
154 }
155 }
156
157 #[doc = "PCM1 data out 1"]
158 #[inline(always)]
159 pub const fn pcm1_out1_reg(
160 &self,
161 ) -> &'static crate::common::Reg<self::Pcm1Out1Reg_SPEC, crate::common::RW> {
162 unsafe {
163 crate::common::Reg::<self::Pcm1Out1Reg_SPEC, crate::common::RW>::from_ptr(
164 self._svd2pac_as_ptr().add(268usize),
165 )
166 }
167 }
168
169 #[doc = "PCM1 data out 2"]
170 #[inline(always)]
171 pub const fn pcm1_out2_reg(
172 &self,
173 ) -> &'static crate::common::Reg<self::Pcm1Out2Reg_SPEC, crate::common::RW> {
174 unsafe {
175 crate::common::Reg::<self::Pcm1Out2Reg_SPEC, crate::common::RW>::from_ptr(
176 self._svd2pac_as_ptr().add(272usize),
177 )
178 }
179 }
180
181 #[doc = "SRC1 control register"]
182 #[inline(always)]
183 pub const fn src1_ctrl_reg(
184 &self,
185 ) -> &'static crate::common::Reg<self::Src1CtrlReg_SPEC, crate::common::RW> {
186 unsafe {
187 crate::common::Reg::<self::Src1CtrlReg_SPEC, crate::common::RW>::from_ptr(
188 self._svd2pac_as_ptr().add(0usize),
189 )
190 }
191 }
192
193 #[doc = "SRC1 data in 1"]
194 #[inline(always)]
195 pub const fn src1_in1_reg(
196 &self,
197 ) -> &'static crate::common::Reg<self::Src1In1Reg_SPEC, crate::common::RW> {
198 unsafe {
199 crate::common::Reg::<self::Src1In1Reg_SPEC, crate::common::RW>::from_ptr(
200 self._svd2pac_as_ptr().add(12usize),
201 )
202 }
203 }
204
205 #[doc = "SRC1 data in 2"]
206 #[inline(always)]
207 pub const fn src1_in2_reg(
208 &self,
209 ) -> &'static crate::common::Reg<self::Src1In2Reg_SPEC, crate::common::RW> {
210 unsafe {
211 crate::common::Reg::<self::Src1In2Reg_SPEC, crate::common::RW>::from_ptr(
212 self._svd2pac_as_ptr().add(16usize),
213 )
214 }
215 }
216
217 #[doc = "SRC1 Sample input rate"]
218 #[inline(always)]
219 pub const fn src1_in_fs_reg(
220 &self,
221 ) -> &'static crate::common::Reg<self::Src1InFsReg_SPEC, crate::common::RW> {
222 unsafe {
223 crate::common::Reg::<self::Src1InFsReg_SPEC, crate::common::RW>::from_ptr(
224 self._svd2pac_as_ptr().add(4usize),
225 )
226 }
227 }
228
229 #[doc = "SRC1 data out 1"]
230 #[inline(always)]
231 pub const fn src1_out1_reg(
232 &self,
233 ) -> &'static crate::common::Reg<self::Src1Out1Reg_SPEC, crate::common::RW> {
234 unsafe {
235 crate::common::Reg::<self::Src1Out1Reg_SPEC, crate::common::RW>::from_ptr(
236 self._svd2pac_as_ptr().add(20usize),
237 )
238 }
239 }
240
241 #[doc = "SRC1 data out 2"]
242 #[inline(always)]
243 pub const fn src1_out2_reg(
244 &self,
245 ) -> &'static crate::common::Reg<self::Src1Out2Reg_SPEC, crate::common::RW> {
246 unsafe {
247 crate::common::Reg::<self::Src1Out2Reg_SPEC, crate::common::RW>::from_ptr(
248 self._svd2pac_as_ptr().add(24usize),
249 )
250 }
251 }
252
253 #[doc = "SRC1 Sample output rate"]
254 #[inline(always)]
255 pub const fn src1_out_fs_reg(
256 &self,
257 ) -> &'static crate::common::Reg<self::Src1OutFsReg_SPEC, crate::common::RW> {
258 unsafe {
259 crate::common::Reg::<self::Src1OutFsReg_SPEC, crate::common::RW>::from_ptr(
260 self._svd2pac_as_ptr().add(8usize),
261 )
262 }
263 }
264}
265#[doc(hidden)]
266#[derive(Copy, Clone, Eq, PartialEq)]
267pub struct ApuMuxReg_SPEC;
268impl crate::sealed::RegSpec for ApuMuxReg_SPEC {
269 type DataType = u32;
270}
271
272#[doc = "APU mux register"]
273pub type ApuMuxReg = crate::RegValueT<ApuMuxReg_SPEC>;
274
275impl ApuMuxReg {
276 #[doc = "PDM1 input mux\n0 = SRC1_MUX_IN\n1 = PDM input"]
277 #[inline(always)]
278 pub fn pdm1_mux_in(
279 self,
280 ) -> crate::common::RegisterFieldBool<6, 1, 0, ApuMuxReg_SPEC, crate::common::RW> {
281 crate::common::RegisterFieldBool::<6,1,0,ApuMuxReg_SPEC,crate::common::RW>::from_register(self,0)
282 }
283
284 #[doc = "PCM1 input mux\n0 = off\n1 = SRC1 output\n2 = PCM output registers"]
285 #[inline(always)]
286 pub fn pcm1_mux_in(
287 self,
288 ) -> crate::common::RegisterField<3, 0x7, 1, 0, u8, u8, ApuMuxReg_SPEC, crate::common::RW> {
289 crate::common::RegisterField::<3,0x7,1,0,u8,u8,ApuMuxReg_SPEC,crate::common::RW>::from_register(self,0)
290 }
291
292 #[doc = "SRC1 input mux\n0 = off\n1 = PCM output\n2 = SRC1 input registers"]
293 #[inline(always)]
294 pub fn src1_mux_in(
295 self,
296 ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, ApuMuxReg_SPEC, crate::common::RW> {
297 crate::common::RegisterField::<0,0x7,1,0,u8,u8,ApuMuxReg_SPEC,crate::common::RW>::from_register(self,0)
298 }
299}
300impl ::core::default::Default for ApuMuxReg {
301 #[inline(always)]
302 fn default() -> ApuMuxReg {
303 <crate::RegValueT<ApuMuxReg_SPEC> as RegisterValue<_>>::new(0)
304 }
305}
306
307#[doc(hidden)]
308#[derive(Copy, Clone, Eq, PartialEq)]
309pub struct Coef0ASet1Reg_SPEC;
310impl crate::sealed::RegSpec for Coef0ASet1Reg_SPEC {
311 type DataType = u32;
312}
313
314#[doc = "SRC coefficient 10 set 1"]
315pub type Coef0ASet1Reg = crate::RegValueT<Coef0ASet1Reg_SPEC>;
316
317impl Coef0ASet1Reg {
318 #[doc = "coefficient 10"]
319 #[inline(always)]
320 pub fn src_coef10(
321 self,
322 ) -> crate::common::RegisterField<
323 0,
324 0xffff,
325 1,
326 0,
327 u16,
328 u16,
329 Coef0ASet1Reg_SPEC,
330 crate::common::RW,
331 > {
332 crate::common::RegisterField::<
333 0,
334 0xffff,
335 1,
336 0,
337 u16,
338 u16,
339 Coef0ASet1Reg_SPEC,
340 crate::common::RW,
341 >::from_register(self, 0)
342 }
343}
344impl ::core::default::Default for Coef0ASet1Reg {
345 #[inline(always)]
346 fn default() -> Coef0ASet1Reg {
347 <crate::RegValueT<Coef0ASet1Reg_SPEC> as RegisterValue<_>>::new(16882)
348 }
349}
350
351#[doc(hidden)]
352#[derive(Copy, Clone, Eq, PartialEq)]
353pub struct Coef10Set1Reg_SPEC;
354impl crate::sealed::RegSpec for Coef10Set1Reg_SPEC {
355 type DataType = u32;
356}
357
358#[doc = "SRC coefficient 1,0 set 1"]
359pub type Coef10Set1Reg = crate::RegValueT<Coef10Set1Reg_SPEC>;
360
361impl Coef10Set1Reg {
362 #[doc = "coefficient 1"]
363 #[inline(always)]
364 pub fn src_coef1(
365 self,
366 ) -> crate::common::RegisterField<
367 16,
368 0xffff,
369 1,
370 0,
371 u16,
372 u16,
373 Coef10Set1Reg_SPEC,
374 crate::common::RW,
375 > {
376 crate::common::RegisterField::<
377 16,
378 0xffff,
379 1,
380 0,
381 u16,
382 u16,
383 Coef10Set1Reg_SPEC,
384 crate::common::RW,
385 >::from_register(self, 0)
386 }
387
388 #[doc = "coefficient 0"]
389 #[inline(always)]
390 pub fn src_coef0(
391 self,
392 ) -> crate::common::RegisterField<
393 0,
394 0xffff,
395 1,
396 0,
397 u16,
398 u16,
399 Coef10Set1Reg_SPEC,
400 crate::common::RW,
401 > {
402 crate::common::RegisterField::<
403 0,
404 0xffff,
405 1,
406 0,
407 u16,
408 u16,
409 Coef10Set1Reg_SPEC,
410 crate::common::RW,
411 >::from_register(self, 0)
412 }
413}
414impl ::core::default::Default for Coef10Set1Reg {
415 #[inline(always)]
416 fn default() -> Coef10Set1Reg {
417 <crate::RegValueT<Coef10Set1Reg_SPEC> as RegisterValue<_>>::new(2041156216)
418 }
419}
420
421#[doc(hidden)]
422#[derive(Copy, Clone, Eq, PartialEq)]
423pub struct Coef32Set1Reg_SPEC;
424impl crate::sealed::RegSpec for Coef32Set1Reg_SPEC {
425 type DataType = u32;
426}
427
428#[doc = "SRC coefficient 3,2 set 1"]
429pub type Coef32Set1Reg = crate::RegValueT<Coef32Set1Reg_SPEC>;
430
431impl Coef32Set1Reg {
432 #[doc = "coefficient 3"]
433 #[inline(always)]
434 pub fn src_coef3(
435 self,
436 ) -> crate::common::RegisterField<
437 16,
438 0xffff,
439 1,
440 0,
441 u16,
442 u16,
443 Coef32Set1Reg_SPEC,
444 crate::common::RW,
445 > {
446 crate::common::RegisterField::<
447 16,
448 0xffff,
449 1,
450 0,
451 u16,
452 u16,
453 Coef32Set1Reg_SPEC,
454 crate::common::RW,
455 >::from_register(self, 0)
456 }
457
458 #[doc = "coefficient 2"]
459 #[inline(always)]
460 pub fn src_coef2(
461 self,
462 ) -> crate::common::RegisterField<
463 0,
464 0xffff,
465 1,
466 0,
467 u16,
468 u16,
469 Coef32Set1Reg_SPEC,
470 crate::common::RW,
471 > {
472 crate::common::RegisterField::<
473 0,
474 0xffff,
475 1,
476 0,
477 u16,
478 u16,
479 Coef32Set1Reg_SPEC,
480 crate::common::RW,
481 >::from_register(self, 0)
482 }
483}
484impl ::core::default::Default for Coef32Set1Reg {
485 #[inline(always)]
486 fn default() -> Coef32Set1Reg {
487 <crate::RegValueT<Coef32Set1Reg_SPEC> as RegisterValue<_>>::new(1834388289)
488 }
489}
490
491#[doc(hidden)]
492#[derive(Copy, Clone, Eq, PartialEq)]
493pub struct Coef54Set1Reg_SPEC;
494impl crate::sealed::RegSpec for Coef54Set1Reg_SPEC {
495 type DataType = u32;
496}
497
498#[doc = "SRC coefficient 5,4 set 1"]
499pub type Coef54Set1Reg = crate::RegValueT<Coef54Set1Reg_SPEC>;
500
501impl Coef54Set1Reg {
502 #[doc = "coefficient 5"]
503 #[inline(always)]
504 pub fn src_coef5(
505 self,
506 ) -> crate::common::RegisterField<
507 16,
508 0xffff,
509 1,
510 0,
511 u16,
512 u16,
513 Coef54Set1Reg_SPEC,
514 crate::common::RW,
515 > {
516 crate::common::RegisterField::<
517 16,
518 0xffff,
519 1,
520 0,
521 u16,
522 u16,
523 Coef54Set1Reg_SPEC,
524 crate::common::RW,
525 >::from_register(self, 0)
526 }
527
528 #[doc = "coefficient 4"]
529 #[inline(always)]
530 pub fn src_coef4(
531 self,
532 ) -> crate::common::RegisterField<
533 0,
534 0xffff,
535 1,
536 0,
537 u16,
538 u16,
539 Coef54Set1Reg_SPEC,
540 crate::common::RW,
541 > {
542 crate::common::RegisterField::<
543 0,
544 0xffff,
545 1,
546 0,
547 u16,
548 u16,
549 Coef54Set1Reg_SPEC,
550 crate::common::RW,
551 >::from_register(self, 0)
552 }
553}
554impl ::core::default::Default for Coef54Set1Reg {
555 #[inline(always)]
556 fn default() -> Coef54Set1Reg {
557 <crate::RegValueT<Coef54Set1Reg_SPEC> as RegisterValue<_>>::new(2147483647)
558 }
559}
560
561#[doc(hidden)]
562#[derive(Copy, Clone, Eq, PartialEq)]
563pub struct Coef76Set1Reg_SPEC;
564impl crate::sealed::RegSpec for Coef76Set1Reg_SPEC {
565 type DataType = u32;
566}
567
568#[doc = "SRC coefficient 7,6 set 1"]
569pub type Coef76Set1Reg = crate::RegValueT<Coef76Set1Reg_SPEC>;
570
571impl Coef76Set1Reg {
572 #[doc = "coefficient 7"]
573 #[inline(always)]
574 pub fn src_coef7(
575 self,
576 ) -> crate::common::RegisterField<
577 16,
578 0xffff,
579 1,
580 0,
581 u16,
582 u16,
583 Coef76Set1Reg_SPEC,
584 crate::common::RW,
585 > {
586 crate::common::RegisterField::<
587 16,
588 0xffff,
589 1,
590 0,
591 u16,
592 u16,
593 Coef76Set1Reg_SPEC,
594 crate::common::RW,
595 >::from_register(self, 0)
596 }
597
598 #[doc = "coefficient 6"]
599 #[inline(always)]
600 pub fn src_coef6(
601 self,
602 ) -> crate::common::RegisterField<
603 0,
604 0xffff,
605 1,
606 0,
607 u16,
608 u16,
609 Coef76Set1Reg_SPEC,
610 crate::common::RW,
611 > {
612 crate::common::RegisterField::<
613 0,
614 0xffff,
615 1,
616 0,
617 u16,
618 u16,
619 Coef76Set1Reg_SPEC,
620 crate::common::RW,
621 >::from_register(self, 0)
622 }
623}
624impl ::core::default::Default for Coef76Set1Reg {
625 #[inline(always)]
626 fn default() -> Coef76Set1Reg {
627 <crate::RegValueT<Coef76Set1Reg_SPEC> as RegisterValue<_>>::new(2147483647)
628 }
629}
630
631#[doc(hidden)]
632#[derive(Copy, Clone, Eq, PartialEq)]
633pub struct Coef98Set1Reg_SPEC;
634impl crate::sealed::RegSpec for Coef98Set1Reg_SPEC {
635 type DataType = u32;
636}
637
638#[doc = "SRC coefficient 9,8 set 1"]
639pub type Coef98Set1Reg = crate::RegValueT<Coef98Set1Reg_SPEC>;
640
641impl Coef98Set1Reg {
642 #[doc = "coefficient 9"]
643 #[inline(always)]
644 pub fn src_coef9(
645 self,
646 ) -> crate::common::RegisterField<
647 16,
648 0xffff,
649 1,
650 0,
651 u16,
652 u16,
653 Coef98Set1Reg_SPEC,
654 crate::common::RW,
655 > {
656 crate::common::RegisterField::<
657 16,
658 0xffff,
659 1,
660 0,
661 u16,
662 u16,
663 Coef98Set1Reg_SPEC,
664 crate::common::RW,
665 >::from_register(self, 0)
666 }
667
668 #[doc = "coefficient 8"]
669 #[inline(always)]
670 pub fn src_coef8(
671 self,
672 ) -> crate::common::RegisterField<
673 0,
674 0xffff,
675 1,
676 0,
677 u16,
678 u16,
679 Coef98Set1Reg_SPEC,
680 crate::common::RW,
681 > {
682 crate::common::RegisterField::<
683 0,
684 0xffff,
685 1,
686 0,
687 u16,
688 u16,
689 Coef98Set1Reg_SPEC,
690 crate::common::RW,
691 >::from_register(self, 0)
692 }
693}
694impl ::core::default::Default for Coef98Set1Reg {
695 #[inline(always)]
696 fn default() -> Coef98Set1Reg {
697 <crate::RegValueT<Coef98Set1Reg_SPEC> as RegisterValue<_>>::new(2147483647)
698 }
699}
700
701#[doc(hidden)]
702#[derive(Copy, Clone, Eq, PartialEq)]
703pub struct Pcm1CtrlReg_SPEC;
704impl crate::sealed::RegSpec for Pcm1CtrlReg_SPEC {
705 type DataType = u32;
706}
707
708#[doc = "PCM1 Control register"]
709pub type Pcm1CtrlReg = crate::RegValueT<Pcm1CtrlReg_SPEC>;
710
711impl Pcm1CtrlReg {
712 #[doc = "PCM Framesync divider, Values 7-0xFFF. To divide by N, write N-1. (Minimum value N-1=7 for 8 bits PCM_FSC)\nNote if PCM_CLK_BIT=1, N must always be even"]
713 #[inline(always)]
714 pub fn pcm_fsc_div(
715 self,
716 ) -> crate::common::RegisterField<20, 0xfff, 1, 0, u16, u16, Pcm1CtrlReg_SPEC, crate::common::RW>
717 {
718 crate::common::RegisterField::<20,0xfff,1,0,u16,u16,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
719 }
720
721 #[doc = "0: shift channels 1, 2, 3, 4, 5, 6, 7, 8 after PCM_FSC edge\n1: shift channels 1, 2, 3, 4 after PCM_FSC edge shift channels 5, 6, 7, 8 after opposite PCM_FSC edge"]
722 #[inline(always)]
723 pub fn pcm_fsc_edge(
724 self,
725 ) -> crate::common::RegisterFieldBool<16, 1, 0, Pcm1CtrlReg_SPEC, crate::common::RW> {
726 crate::common::RegisterFieldBool::<16,1,0,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
727 }
728
729 #[doc = "Channel delay in multiples of 8 bits"]
730 #[inline(always)]
731 pub fn pcm_ch_del(
732 self,
733 ) -> crate::common::RegisterField<11, 0x1f, 1, 0, u8, u8, Pcm1CtrlReg_SPEC, crate::common::RW>
734 {
735 crate::common::RegisterField::<11,0x1f,1,0,u8,u8,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
736 }
737
738 #[doc = "0:One clock cycle per data bit\n1:Two cloc cycles per data bit"]
739 #[inline(always)]
740 pub fn pcm_clk_bit(
741 self,
742 ) -> crate::common::RegisterFieldBool<10, 1, 0, Pcm1CtrlReg_SPEC, crate::common::RW> {
743 crate::common::RegisterFieldBool::<10,1,0,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
744 }
745
746 #[doc = "0: PCM FSC\n1: PCM FSC inverted"]
747 #[inline(always)]
748 pub fn pcm_fscinv(
749 self,
750 ) -> crate::common::RegisterFieldBool<9, 1, 0, Pcm1CtrlReg_SPEC, crate::common::RW> {
751 crate::common::RegisterFieldBool::<9,1,0,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
752 }
753
754 #[doc = "0:PCM CLK\n1:PCM CLK inverted"]
755 #[inline(always)]
756 pub fn pcm_clkinv(
757 self,
758 ) -> crate::common::RegisterFieldBool<8, 1, 0, Pcm1CtrlReg_SPEC, crate::common::RW> {
759 crate::common::RegisterFieldBool::<8,1,0,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
760 }
761
762 #[doc = "0:PCM DO push pull\n1:PCM DO open drain"]
763 #[inline(always)]
764 pub fn pcm_ppod(
765 self,
766 ) -> crate::common::RegisterFieldBool<7, 1, 0, Pcm1CtrlReg_SPEC, crate::common::RW> {
767 crate::common::RegisterFieldBool::<7,1,0,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
768 }
769
770 #[doc = "0:PCM FSC starts one cycle before MSB bit\n1:PCM FSC starts at the same time as MSB bit"]
771 #[inline(always)]
772 pub fn pcm_fscdel(
773 self,
774 ) -> crate::common::RegisterFieldBool<6, 1, 0, Pcm1CtrlReg_SPEC, crate::common::RW> {
775 crate::common::RegisterFieldBool::<6,1,0,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
776 }
777
778 #[doc = "0:PCM FSC length equal to 1 data bit\nN:PCM FSC length equal to N*8"]
779 #[inline(always)]
780 pub fn pcm_fsclen(
781 self,
782 ) -> crate::common::RegisterField<2, 0xf, 1, 0, u8, u8, Pcm1CtrlReg_SPEC, crate::common::RW>
783 {
784 crate::common::RegisterField::<2,0xf,1,0,u8,u8,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
785 }
786
787 #[doc = "0:PCM interface in slave mode\n1:PCM interface in master mode"]
788 #[inline(always)]
789 pub fn pcm_master(
790 self,
791 ) -> crate::common::RegisterFieldBool<1, 1, 0, Pcm1CtrlReg_SPEC, crate::common::RW> {
792 crate::common::RegisterFieldBool::<1,1,0,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
793 }
794
795 #[doc = "0:PCM interface disabled\n1:PCM interface enabled"]
796 #[inline(always)]
797 pub fn pcm_en(
798 self,
799 ) -> crate::common::RegisterFieldBool<0, 1, 0, Pcm1CtrlReg_SPEC, crate::common::RW> {
800 crate::common::RegisterFieldBool::<0,1,0,Pcm1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
801 }
802}
803impl ::core::default::Default for Pcm1CtrlReg {
804 #[inline(always)]
805 fn default() -> Pcm1CtrlReg {
806 <crate::RegValueT<Pcm1CtrlReg_SPEC> as RegisterValue<_>>::new(0)
807 }
808}
809
810#[doc(hidden)]
811#[derive(Copy, Clone, Eq, PartialEq)]
812pub struct Pcm1In1Reg_SPEC;
813impl crate::sealed::RegSpec for Pcm1In1Reg_SPEC {
814 type DataType = u32;
815}
816
817#[doc = "PCM1 data in 1"]
818pub type Pcm1In1Reg = crate::RegValueT<Pcm1In1Reg_SPEC>;
819
820impl Pcm1In1Reg {
821 #[doc = "PCM1_IN1 bits 31-0"]
822 #[inline(always)]
823 pub fn pcm_in(
824 self,
825 ) -> crate::common::RegisterField<
826 0,
827 0xffffffff,
828 1,
829 0,
830 u32,
831 u32,
832 Pcm1In1Reg_SPEC,
833 crate::common::R,
834 > {
835 crate::common::RegisterField::<
836 0,
837 0xffffffff,
838 1,
839 0,
840 u32,
841 u32,
842 Pcm1In1Reg_SPEC,
843 crate::common::R,
844 >::from_register(self, 0)
845 }
846}
847impl ::core::default::Default for Pcm1In1Reg {
848 #[inline(always)]
849 fn default() -> Pcm1In1Reg {
850 <crate::RegValueT<Pcm1In1Reg_SPEC> as RegisterValue<_>>::new(2147483647)
851 }
852}
853
854#[doc(hidden)]
855#[derive(Copy, Clone, Eq, PartialEq)]
856pub struct Pcm1In2Reg_SPEC;
857impl crate::sealed::RegSpec for Pcm1In2Reg_SPEC {
858 type DataType = u32;
859}
860
861#[doc = "PCM1 data in 2"]
862pub type Pcm1In2Reg = crate::RegValueT<Pcm1In2Reg_SPEC>;
863
864impl Pcm1In2Reg {
865 #[doc = "PCM1_IN2 bits 31-0"]
866 #[inline(always)]
867 pub fn pcm_in(
868 self,
869 ) -> crate::common::RegisterField<
870 0,
871 0xffffffff,
872 1,
873 0,
874 u32,
875 u32,
876 Pcm1In2Reg_SPEC,
877 crate::common::R,
878 > {
879 crate::common::RegisterField::<
880 0,
881 0xffffffff,
882 1,
883 0,
884 u32,
885 u32,
886 Pcm1In2Reg_SPEC,
887 crate::common::R,
888 >::from_register(self, 0)
889 }
890}
891impl ::core::default::Default for Pcm1In2Reg {
892 #[inline(always)]
893 fn default() -> Pcm1In2Reg {
894 <crate::RegValueT<Pcm1In2Reg_SPEC> as RegisterValue<_>>::new(2147483647)
895 }
896}
897
898#[doc(hidden)]
899#[derive(Copy, Clone, Eq, PartialEq)]
900pub struct Pcm1Out1Reg_SPEC;
901impl crate::sealed::RegSpec for Pcm1Out1Reg_SPEC {
902 type DataType = u32;
903}
904
905#[doc = "PCM1 data out 1"]
906pub type Pcm1Out1Reg = crate::RegValueT<Pcm1Out1Reg_SPEC>;
907
908impl Pcm1Out1Reg {
909 #[doc = "PCM1_OUT1 bits 31-0"]
910 #[inline(always)]
911 pub fn pcm_out(
912 self,
913 ) -> crate::common::RegisterField<
914 0,
915 0xffffffff,
916 1,
917 0,
918 u32,
919 u32,
920 Pcm1Out1Reg_SPEC,
921 crate::common::RW,
922 > {
923 crate::common::RegisterField::<
924 0,
925 0xffffffff,
926 1,
927 0,
928 u32,
929 u32,
930 Pcm1Out1Reg_SPEC,
931 crate::common::RW,
932 >::from_register(self, 0)
933 }
934}
935impl ::core::default::Default for Pcm1Out1Reg {
936 #[inline(always)]
937 fn default() -> Pcm1Out1Reg {
938 <crate::RegValueT<Pcm1Out1Reg_SPEC> as RegisterValue<_>>::new(2147483647)
939 }
940}
941
942#[doc(hidden)]
943#[derive(Copy, Clone, Eq, PartialEq)]
944pub struct Pcm1Out2Reg_SPEC;
945impl crate::sealed::RegSpec for Pcm1Out2Reg_SPEC {
946 type DataType = u32;
947}
948
949#[doc = "PCM1 data out 2"]
950pub type Pcm1Out2Reg = crate::RegValueT<Pcm1Out2Reg_SPEC>;
951
952impl Pcm1Out2Reg {
953 #[doc = "PCM1_OUT2 bits 31-0"]
954 #[inline(always)]
955 pub fn pcm_out(
956 self,
957 ) -> crate::common::RegisterField<
958 0,
959 0xffffffff,
960 1,
961 0,
962 u32,
963 u32,
964 Pcm1Out2Reg_SPEC,
965 crate::common::RW,
966 > {
967 crate::common::RegisterField::<
968 0,
969 0xffffffff,
970 1,
971 0,
972 u32,
973 u32,
974 Pcm1Out2Reg_SPEC,
975 crate::common::RW,
976 >::from_register(self, 0)
977 }
978}
979impl ::core::default::Default for Pcm1Out2Reg {
980 #[inline(always)]
981 fn default() -> Pcm1Out2Reg {
982 <crate::RegValueT<Pcm1Out2Reg_SPEC> as RegisterValue<_>>::new(2147483647)
983 }
984}
985
986#[doc(hidden)]
987#[derive(Copy, Clone, Eq, PartialEq)]
988pub struct Src1CtrlReg_SPEC;
989impl crate::sealed::RegSpec for Src1CtrlReg_SPEC {
990 type DataType = u32;
991}
992
993#[doc = "SRC1 control register"]
994pub type Src1CtrlReg = crate::RegValueT<Src1CtrlReg_SPEC>;
995
996impl Src1CtrlReg {
997 #[doc = "PDM Output mode selection on PDM_DO1\n00: No output\n01: Right channel (falling edge of PDM_CLK)\n10: Left channel (rising edge of PDM_CLK)\n11: Left and Right channel"]
998 #[inline(always)]
999 pub fn src_pdm_mode(
1000 self,
1001 ) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, Src1CtrlReg_SPEC, crate::common::RW>
1002 {
1003 crate::common::RegisterField::<28,0x3,1,0,u8,u8,Src1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
1004 }
1005
1006 #[doc = "Writing a 1 clears the SRC1_OUT Overflow/underflow bits 23-22. No more over/underflow indications while bit is 1. Keep 1 until the over/under flow bit is cleared"]
1007 #[inline(always)]
1008 pub fn src_out_flowclr(
1009 self,
1010 ) -> crate::common::RegisterFieldBool<25, 1, 0, Src1CtrlReg_SPEC, crate::common::W> {
1011 crate::common::RegisterFieldBool::<25,1,0,Src1CtrlReg_SPEC,crate::common::W>::from_register(self,0)
1012 }
1013
1014 #[doc = "Writing a 1 clears the SRC1_IN Overflow/underflow bits 21-20. No more over/underflow indications while bit is 1. Keep 1 until the over/under flow bit is cleared"]
1015 #[inline(always)]
1016 pub fn src_in_flowclr(
1017 self,
1018 ) -> crate::common::RegisterFieldBool<24, 1, 0, Src1CtrlReg_SPEC, crate::common::W> {
1019 crate::common::RegisterFieldBool::<24,1,0,Src1CtrlReg_SPEC,crate::common::W>::from_register(self,0)
1020 }
1021
1022 #[doc = "1 = SRC1_OUT Underflow occurred"]
1023 #[inline(always)]
1024 pub fn src_out_unflow(
1025 self,
1026 ) -> crate::common::RegisterFieldBool<23, 1, 0, Src1CtrlReg_SPEC, crate::common::R> {
1027 crate::common::RegisterFieldBool::<23,1,0,Src1CtrlReg_SPEC,crate::common::R>::from_register(self,0)
1028 }
1029
1030 #[doc = "1 = SRC1_OUT Overflow occurred"]
1031 #[inline(always)]
1032 pub fn src_out_ovflow(
1033 self,
1034 ) -> crate::common::RegisterFieldBool<22, 1, 0, Src1CtrlReg_SPEC, crate::common::R> {
1035 crate::common::RegisterFieldBool::<22,1,0,Src1CtrlReg_SPEC,crate::common::R>::from_register(self,0)
1036 }
1037
1038 #[doc = "1 = SRC1_IN Underflow occurred"]
1039 #[inline(always)]
1040 pub fn src_in_unflow(
1041 self,
1042 ) -> crate::common::RegisterFieldBool<21, 1, 0, Src1CtrlReg_SPEC, crate::common::R> {
1043 crate::common::RegisterFieldBool::<21,1,0,Src1CtrlReg_SPEC,crate::common::R>::from_register(self,0)
1044 }
1045
1046 #[doc = "1 = SRC1_IN Overflow occurred"]
1047 #[inline(always)]
1048 pub fn src_in_ovflow(
1049 self,
1050 ) -> crate::common::RegisterFieldBool<20, 1, 0, Src1CtrlReg_SPEC, crate::common::R> {
1051 crate::common::RegisterFieldBool::<20,1,0,Src1CtrlReg_SPEC,crate::common::R>::from_register(self,0)
1052 }
1053
1054 #[doc = "SRC1_OUT Status\n0: acquisition in progress\n1: acquisition ready (In manual mode this bit is always 1)"]
1055 #[inline(always)]
1056 pub fn src_out_ok(
1057 self,
1058 ) -> crate::common::RegisterFieldBool<18, 1, 0, Src1CtrlReg_SPEC, crate::common::R> {
1059 crate::common::RegisterFieldBool::<18,1,0,Src1CtrlReg_SPEC,crate::common::R>::from_register(self,0)
1060 }
1061
1062 #[doc = "SRC1_OUT UpSampling IIR filters setting\n00: for sample rates up-to 48kHz\n01: for sample rates of 96kHz\n10: reserved\n11: for sample rates of 192kHz"]
1063 #[inline(always)]
1064 pub fn src_out_us(
1065 self,
1066 ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, Src1CtrlReg_SPEC, crate::common::RW>
1067 {
1068 crate::common::RegisterField::<16,0x3,1,0,u8,u8,Src1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
1069 }
1070
1071 #[doc = "SRC1_OUT1 upsampiling filter bypass\n0:Do not bypass\n1:Bypass filter"]
1072 #[inline(always)]
1073 pub fn src_out_cal_bypass(
1074 self,
1075 ) -> crate::common::RegisterFieldBool<14, 1, 0, Src1CtrlReg_SPEC, crate::common::RW> {
1076 crate::common::RegisterFieldBool::<14,1,0,Src1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
1077 }
1078
1079 #[doc = "SRC1_OUT1 Automatic Conversion mode\n0:Manual mode\n1:Automatic mode"]
1080 #[inline(always)]
1081 pub fn src_out_amode(
1082 self,
1083 ) -> crate::common::RegisterFieldBool<13, 1, 0, Src1CtrlReg_SPEC, crate::common::RW> {
1084 crate::common::RegisterFieldBool::<13,1,0,Src1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
1085 }
1086
1087 #[doc = "Dithering feature\n0: Enable\n1: Disable"]
1088 #[inline(always)]
1089 pub fn src_dither_disable(
1090 self,
1091 ) -> crate::common::RegisterFieldBool<7, 1, 0, Src1CtrlReg_SPEC, crate::common::RW> {
1092 crate::common::RegisterFieldBool::<7,1,0,Src1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
1093 }
1094
1095 #[doc = "SRC1_IN status\n0: Acquisition in progress\n1: Acquisition ready"]
1096 #[inline(always)]
1097 pub fn src_in_ok(
1098 self,
1099 ) -> crate::common::RegisterFieldBool<6, 1, 0, Src1CtrlReg_SPEC, crate::common::R> {
1100 crate::common::RegisterFieldBool::<6,1,0,Src1CtrlReg_SPEC,crate::common::R>::from_register(self,0)
1101 }
1102
1103 #[doc = "SRC1_IN UpSampling IIR filters setting\n00: for sample rates up-to 48kHz\n01: for sample rates of 96kHz\n10: reserved\n11: for sample rates of 192kHz"]
1104 #[inline(always)]
1105 pub fn src_in_ds(
1106 self,
1107 ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, Src1CtrlReg_SPEC, crate::common::RW>
1108 {
1109 crate::common::RegisterField::<4,0x3,1,0,u8,u8,Src1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
1110 }
1111
1112 #[doc = "SRC1_IN upsampeling filter bypass\n0: Do not bypass\n1: Bypass filter"]
1113 #[inline(always)]
1114 pub fn src_in_cal_bypass(
1115 self,
1116 ) -> crate::common::RegisterFieldBool<2, 1, 0, Src1CtrlReg_SPEC, crate::common::RW> {
1117 crate::common::RegisterFieldBool::<2,1,0,Src1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
1118 }
1119
1120 #[doc = "SRC1_IN Automatic conversion mode\n0: Manual mode\n1: Automatic mode"]
1121 #[inline(always)]
1122 pub fn src_in_amode(
1123 self,
1124 ) -> crate::common::RegisterFieldBool<1, 1, 0, Src1CtrlReg_SPEC, crate::common::RW> {
1125 crate::common::RegisterFieldBool::<1,1,0,Src1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
1126 }
1127
1128 #[doc = "SRC1_IN and SRC1_OUT enable\n0: disabled\n1: enabled"]
1129 #[inline(always)]
1130 pub fn src_en(
1131 self,
1132 ) -> crate::common::RegisterFieldBool<0, 1, 0, Src1CtrlReg_SPEC, crate::common::RW> {
1133 crate::common::RegisterFieldBool::<0,1,0,Src1CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
1134 }
1135}
1136impl ::core::default::Default for Src1CtrlReg {
1137 #[inline(always)]
1138 fn default() -> Src1CtrlReg {
1139 <crate::RegValueT<Src1CtrlReg_SPEC> as RegisterValue<_>>::new(0)
1140 }
1141}
1142
1143#[doc(hidden)]
1144#[derive(Copy, Clone, Eq, PartialEq)]
1145pub struct Src1In1Reg_SPEC;
1146impl crate::sealed::RegSpec for Src1In1Reg_SPEC {
1147 type DataType = u32;
1148}
1149
1150#[doc = "SRC1 data in 1"]
1151pub type Src1In1Reg = crate::RegValueT<Src1In1Reg_SPEC>;
1152
1153impl Src1In1Reg {
1154 #[doc = "SRC1_IN1"]
1155 #[inline(always)]
1156 pub fn src_in(
1157 self,
1158 ) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Src1In1Reg_SPEC, crate::common::RW>
1159 {
1160 crate::common::RegisterField::<
1161 8,
1162 0xffffff,
1163 1,
1164 0,
1165 u32,
1166 u32,
1167 Src1In1Reg_SPEC,
1168 crate::common::RW,
1169 >::from_register(self, 0)
1170 }
1171}
1172impl ::core::default::Default for Src1In1Reg {
1173 #[inline(always)]
1174 fn default() -> Src1In1Reg {
1175 <crate::RegValueT<Src1In1Reg_SPEC> as RegisterValue<_>>::new(0)
1176 }
1177}
1178
1179#[doc(hidden)]
1180#[derive(Copy, Clone, Eq, PartialEq)]
1181pub struct Src1In2Reg_SPEC;
1182impl crate::sealed::RegSpec for Src1In2Reg_SPEC {
1183 type DataType = u32;
1184}
1185
1186#[doc = "SRC1 data in 2"]
1187pub type Src1In2Reg = crate::RegValueT<Src1In2Reg_SPEC>;
1188
1189impl Src1In2Reg {
1190 #[doc = "SRC1_IN2"]
1191 #[inline(always)]
1192 pub fn src_in(
1193 self,
1194 ) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Src1In2Reg_SPEC, crate::common::RW>
1195 {
1196 crate::common::RegisterField::<
1197 8,
1198 0xffffff,
1199 1,
1200 0,
1201 u32,
1202 u32,
1203 Src1In2Reg_SPEC,
1204 crate::common::RW,
1205 >::from_register(self, 0)
1206 }
1207}
1208impl ::core::default::Default for Src1In2Reg {
1209 #[inline(always)]
1210 fn default() -> Src1In2Reg {
1211 <crate::RegValueT<Src1In2Reg_SPEC> as RegisterValue<_>>::new(0)
1212 }
1213}
1214
1215#[doc(hidden)]
1216#[derive(Copy, Clone, Eq, PartialEq)]
1217pub struct Src1InFsReg_SPEC;
1218impl crate::sealed::RegSpec for Src1InFsReg_SPEC {
1219 type DataType = u32;
1220}
1221
1222#[doc = "SRC1 Sample input rate"]
1223pub type Src1InFsReg = crate::RegValueT<Src1InFsReg_SPEC>;
1224
1225impl Src1InFsReg {
1226 #[doc = "SRC_IN Sample rate\nSRC_IN_FS = 8192*Sample_rate/100\nSample_rate upper limit is 192 kHz. For 96 kHz and 192 kHz SRC_CTRLx_REG\\[SRC_IN_DS\\] must be set as shown below:\n\nSample_rate SRC_IN_FS SRC_IN_DS Audio BW\n8000 Hz 0xA0000 0 4000 Hz\n11025 Hz 0x0DC800 0 5512 Hz\n16000 Hz 0x140000 0 8000 Hz\n22050 Hz 0x1B9000 0 11025 Hz\n32000 Hz 0x280000 0 16000 Hz\n44100 Hz 0x372000 0 22050 Hz\n48000 Hz 0x3C0000 0 24000 Hz\n96000 Hz 0x3C0000 1 24000 Hz\n192000 Hz 0x3C0000 3 24000 Hz\n\nIn manual SRC mode, SRC_IN_FS can be set and adjusted to the desired sample rate at any time.\nIn automatic mode the SRC returns the final sample rate as soon as SRC_IN_OK. Note that SRC_DS is not calculated in automatic mode and must be set manually automatic mode with Sample_rate of 96 kHz and 192 kHz."]
1227 #[inline(always)]
1228 pub fn src_in_fs(
1229 self,
1230 ) -> crate::common::RegisterField<
1231 0,
1232 0xffffff,
1233 1,
1234 0,
1235 u32,
1236 u32,
1237 Src1InFsReg_SPEC,
1238 crate::common::RW,
1239 > {
1240 crate::common::RegisterField::<
1241 0,
1242 0xffffff,
1243 1,
1244 0,
1245 u32,
1246 u32,
1247 Src1InFsReg_SPEC,
1248 crate::common::RW,
1249 >::from_register(self, 0)
1250 }
1251}
1252impl ::core::default::Default for Src1InFsReg {
1253 #[inline(always)]
1254 fn default() -> Src1InFsReg {
1255 <crate::RegValueT<Src1InFsReg_SPEC> as RegisterValue<_>>::new(0)
1256 }
1257}
1258
1259#[doc(hidden)]
1260#[derive(Copy, Clone, Eq, PartialEq)]
1261pub struct Src1Out1Reg_SPEC;
1262impl crate::sealed::RegSpec for Src1Out1Reg_SPEC {
1263 type DataType = u32;
1264}
1265
1266#[doc = "SRC1 data out 1"]
1267pub type Src1Out1Reg = crate::RegValueT<Src1Out1Reg_SPEC>;
1268
1269impl Src1Out1Reg {
1270 #[doc = "SRC1_OUT1"]
1271 #[inline(always)]
1272 pub fn src_out(
1273 self,
1274 ) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Src1Out1Reg_SPEC, crate::common::R>
1275 {
1276 crate::common::RegisterField::<
1277 8,
1278 0xffffff,
1279 1,
1280 0,
1281 u32,
1282 u32,
1283 Src1Out1Reg_SPEC,
1284 crate::common::R,
1285 >::from_register(self, 0)
1286 }
1287}
1288impl ::core::default::Default for Src1Out1Reg {
1289 #[inline(always)]
1290 fn default() -> Src1Out1Reg {
1291 <crate::RegValueT<Src1Out1Reg_SPEC> as RegisterValue<_>>::new(0)
1292 }
1293}
1294
1295#[doc(hidden)]
1296#[derive(Copy, Clone, Eq, PartialEq)]
1297pub struct Src1Out2Reg_SPEC;
1298impl crate::sealed::RegSpec for Src1Out2Reg_SPEC {
1299 type DataType = u32;
1300}
1301
1302#[doc = "SRC1 data out 2"]
1303pub type Src1Out2Reg = crate::RegValueT<Src1Out2Reg_SPEC>;
1304
1305impl Src1Out2Reg {
1306 #[doc = "SRC1_OUT2"]
1307 #[inline(always)]
1308 pub fn src_out(
1309 self,
1310 ) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Src1Out2Reg_SPEC, crate::common::R>
1311 {
1312 crate::common::RegisterField::<
1313 8,
1314 0xffffff,
1315 1,
1316 0,
1317 u32,
1318 u32,
1319 Src1Out2Reg_SPEC,
1320 crate::common::R,
1321 >::from_register(self, 0)
1322 }
1323}
1324impl ::core::default::Default for Src1Out2Reg {
1325 #[inline(always)]
1326 fn default() -> Src1Out2Reg {
1327 <crate::RegValueT<Src1Out2Reg_SPEC> as RegisterValue<_>>::new(0)
1328 }
1329}
1330
1331#[doc(hidden)]
1332#[derive(Copy, Clone, Eq, PartialEq)]
1333pub struct Src1OutFsReg_SPEC;
1334impl crate::sealed::RegSpec for Src1OutFsReg_SPEC {
1335 type DataType = u32;
1336}
1337
1338#[doc = "SRC1 Sample output rate"]
1339pub type Src1OutFsReg = crate::RegValueT<Src1OutFsReg_SPEC>;
1340
1341impl Src1OutFsReg {
1342 #[doc = "SRC_OUT Sample rate\nSRC_OUT_FS = 8192*Sample_rate/100\nSample_rate upper limit is 192 kHz. For 96 kHz and 192 kHz SRC_CTRLx_REG\\[SRC_DS\\] must be set as shown below:\n\nSample_rate SRC_OUT_FS SRC_OUT_DS Audio BW\n8000 Hz 0xA0000 0 4000 Hz\n11025 Hz 0x0DC800 0 5512 Hz\n16000 Hz 0x140000 0 8000 Hz\n22050 Hz 0x1B9000 0 11025 Hz\n32000 Hz 0x280000 0 16000 Hz\n44100 Hz 0x372000 0 22050 Hz\n48000 Hz 0x3C0000 0 24000 Hz\n96000 Hz 0x3C0000 1 24000 Hz\n192000 Hz 0x3C0000 3 24000 Hz\n\nIn manual SRC mode, SRC_OUT_FS can be set and adjusted to the desired sample rate at any time.\nIn automatic mode the SRC returns the final sample rate as soon as SRC_OUT_OK. Note that SRC_DS is not calculated in automatic mode and must be set manually automatic mode with Sample_rate of 96 kHz and 192 kHz."]
1343 #[inline(always)]
1344 pub fn src_out_fs(
1345 self,
1346 ) -> crate::common::RegisterField<
1347 0,
1348 0xffffff,
1349 1,
1350 0,
1351 u32,
1352 u32,
1353 Src1OutFsReg_SPEC,
1354 crate::common::RW,
1355 > {
1356 crate::common::RegisterField::<
1357 0,
1358 0xffffff,
1359 1,
1360 0,
1361 u32,
1362 u32,
1363 Src1OutFsReg_SPEC,
1364 crate::common::RW,
1365 >::from_register(self, 0)
1366 }
1367}
1368impl ::core::default::Default for Src1OutFsReg {
1369 #[inline(always)]
1370 fn default() -> Src1OutFsReg {
1371 <crate::RegValueT<Src1OutFsReg_SPEC> as RegisterValue<_>>::new(0)
1372 }
1373}