da14580_pac/
nvic.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:44:20 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Cortex M0 NVIC registers"]
28unsafe impl ::core::marker::Send for super::Nvic {}
29unsafe impl ::core::marker::Sync for super::Nvic {}
30impl super::Nvic {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Interrupt set-enable register"]
38    #[inline(always)]
39    pub const fn iser(&self) -> &'static crate::common::Reg<self::Iser_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Iser_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "Interrupt clear-enable register"]
48    #[inline(always)]
49    pub const fn icer(&self) -> &'static crate::common::Reg<self::Icer_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Icer_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(128usize),
53            )
54        }
55    }
56
57    #[doc = "Interrupt set-pending register"]
58    #[inline(always)]
59    pub const fn ispr(&self) -> &'static crate::common::Reg<self::Ispr_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Ispr_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(256usize),
63            )
64        }
65    }
66
67    #[doc = "Interrupt clear-pending register"]
68    #[inline(always)]
69    pub const fn icpr(&self) -> &'static crate::common::Reg<self::Icpr_SPEC, crate::common::RW> {
70        unsafe {
71            crate::common::Reg::<self::Icpr_SPEC, crate::common::RW>::from_ptr(
72                self._svd2pac_as_ptr().add(384usize),
73            )
74        }
75    }
76
77    #[doc = "Interrupt priority register 0"]
78    #[inline(always)]
79    pub const fn ipr0(&self) -> &'static crate::common::Reg<self::Ipr0_SPEC, crate::common::RW> {
80        unsafe {
81            crate::common::Reg::<self::Ipr0_SPEC, crate::common::RW>::from_ptr(
82                self._svd2pac_as_ptr().add(768usize),
83            )
84        }
85    }
86
87    #[doc = "Interrupt priority register 1"]
88    #[inline(always)]
89    pub const fn ipr1(&self) -> &'static crate::common::Reg<self::Ipr1_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::Ipr1_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(772usize),
93            )
94        }
95    }
96
97    #[doc = "Interrupt priority register 2"]
98    #[inline(always)]
99    pub const fn ipr2(&self) -> &'static crate::common::Reg<self::Ipr2_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Ipr2_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(776usize),
103            )
104        }
105    }
106
107    #[doc = "Interrupt priority register 3"]
108    #[inline(always)]
109    pub const fn ipr3(&self) -> &'static crate::common::Reg<self::Ipr3_SPEC, crate::common::RW> {
110        unsafe {
111            crate::common::Reg::<self::Ipr3_SPEC, crate::common::RW>::from_ptr(
112                self._svd2pac_as_ptr().add(780usize),
113            )
114        }
115    }
116
117    #[doc = "Interrupt priority register 4"]
118    #[inline(always)]
119    pub const fn ipr4(&self) -> &'static crate::common::Reg<self::Ipr4_SPEC, crate::common::RW> {
120        unsafe {
121            crate::common::Reg::<self::Ipr4_SPEC, crate::common::RW>::from_ptr(
122                self._svd2pac_as_ptr().add(784usize),
123            )
124        }
125    }
126
127    #[doc = "Interrupt priority register 5"]
128    #[inline(always)]
129    pub const fn ipr5(&self) -> &'static crate::common::Reg<self::Ipr5_SPEC, crate::common::RW> {
130        unsafe {
131            crate::common::Reg::<self::Ipr5_SPEC, crate::common::RW>::from_ptr(
132                self._svd2pac_as_ptr().add(788usize),
133            )
134        }
135    }
136
137    #[doc = "Interrupt priority register 6"]
138    #[inline(always)]
139    pub const fn ipr6(&self) -> &'static crate::common::Reg<self::Ipr6_SPEC, crate::common::RW> {
140        unsafe {
141            crate::common::Reg::<self::Ipr6_SPEC, crate::common::RW>::from_ptr(
142                self._svd2pac_as_ptr().add(792usize),
143            )
144        }
145    }
146}
147#[doc(hidden)]
148#[derive(Copy, Clone, Eq, PartialEq)]
149pub struct Iser_SPEC;
150impl crate::sealed::RegSpec for Iser_SPEC {
151    type DataType = u32;
152}
153
154#[doc = "Interrupt set-enable register"]
155pub type Iser = crate::RegValueT<Iser_SPEC>;
156
157impl Iser {
158    #[doc = "BLE_WAKEUP_LP_IRQn (Interrupt set-enable bit)"]
159    #[inline(always)]
160    pub fn ble_wakeup_lp_irqn(
161        self,
162    ) -> crate::common::RegisterFieldBool<0, 1, 0, Iser_SPEC, crate::common::RW> {
163        crate::common::RegisterFieldBool::<0, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
164            self, 0,
165        )
166    }
167
168    #[doc = "BLE_GEN_IRQn (Interrupt set-enable bit)"]
169    #[inline(always)]
170    pub fn ble_gen_irqn(
171        self,
172    ) -> crate::common::RegisterFieldBool<1, 1, 0, Iser_SPEC, crate::common::RW> {
173        crate::common::RegisterFieldBool::<1, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
174            self, 0,
175        )
176    }
177
178    #[doc = "UART_IRQn (Interrupt set-enable bit)"]
179    #[inline(always)]
180    pub fn uart_irqn(
181        self,
182    ) -> crate::common::RegisterFieldBool<2, 1, 0, Iser_SPEC, crate::common::RW> {
183        crate::common::RegisterFieldBool::<2, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
184            self, 0,
185        )
186    }
187
188    #[doc = "UART2_IRQn (Interrupt set-enable bit)"]
189    #[inline(always)]
190    pub fn uart2_irqn(
191        self,
192    ) -> crate::common::RegisterFieldBool<3, 1, 0, Iser_SPEC, crate::common::RW> {
193        crate::common::RegisterFieldBool::<3, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
194            self, 0,
195        )
196    }
197
198    #[doc = "I2C_IRQn (Interrupt set-enable bit)"]
199    #[inline(always)]
200    pub fn i2c_irqn(
201        self,
202    ) -> crate::common::RegisterFieldBool<4, 1, 0, Iser_SPEC, crate::common::RW> {
203        crate::common::RegisterFieldBool::<4, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
204            self, 0,
205        )
206    }
207
208    #[doc = "SPI_IRQn (Interrupt set-enable bit)"]
209    #[inline(always)]
210    pub fn spi_irqn(
211        self,
212    ) -> crate::common::RegisterFieldBool<5, 1, 0, Iser_SPEC, crate::common::RW> {
213        crate::common::RegisterFieldBool::<5, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
214            self, 0,
215        )
216    }
217
218    #[doc = "ADC_IRQn (Interrupt set-enable bit)"]
219    #[inline(always)]
220    pub fn adc_irqn(
221        self,
222    ) -> crate::common::RegisterFieldBool<6, 1, 0, Iser_SPEC, crate::common::RW> {
223        crate::common::RegisterFieldBool::<6, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
224            self, 0,
225        )
226    }
227
228    #[doc = "KEYBRD_IRQn (Interrupt set-enable bit)"]
229    #[inline(always)]
230    pub fn keybrd_irqn(
231        self,
232    ) -> crate::common::RegisterFieldBool<7, 1, 0, Iser_SPEC, crate::common::RW> {
233        crate::common::RegisterFieldBool::<7, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
234            self, 0,
235        )
236    }
237
238    #[doc = "BLE baseband or Radio diagnostic (Interrupt set-enable bit))"]
239    #[inline(always)]
240    pub fn ble_rf_diag_irqn(
241        self,
242    ) -> crate::common::RegisterFieldBool<8, 1, 0, Iser_SPEC, crate::common::RW> {
243        crate::common::RegisterFieldBool::<8, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
244            self, 0,
245        )
246    }
247
248    #[doc = "RFCAL_IRQn (Interrupt set-enable bit)"]
249    #[inline(always)]
250    pub fn rfcal_irqn(
251        self,
252    ) -> crate::common::RegisterFieldBool<9, 1, 0, Iser_SPEC, crate::common::RW> {
253        crate::common::RegisterFieldBool::<9, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
254            self, 0,
255        )
256    }
257
258    #[doc = "GPIO0 interrupt through debounce (Interrupt set-enable bit)"]
259    #[inline(always)]
260    pub fn gpio0_irqn(
261        self,
262    ) -> crate::common::RegisterFieldBool<10, 1, 0, Iser_SPEC, crate::common::RW> {
263        crate::common::RegisterFieldBool::<10, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
264            self, 0,
265        )
266    }
267
268    #[doc = "GPIO1 interrupt through debounce (Interrupt set-enable bit)"]
269    #[inline(always)]
270    pub fn gpio1_irqn(
271        self,
272    ) -> crate::common::RegisterFieldBool<11, 1, 0, Iser_SPEC, crate::common::RW> {
273        crate::common::RegisterFieldBool::<11, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
274            self, 0,
275        )
276    }
277
278    #[doc = "GPIO2 interrupt through debounce (Interrupt set-enable bit)"]
279    #[inline(always)]
280    pub fn gpio2_irqn(
281        self,
282    ) -> crate::common::RegisterFieldBool<12, 1, 0, Iser_SPEC, crate::common::RW> {
283        crate::common::RegisterFieldBool::<12, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
284            self, 0,
285        )
286    }
287
288    #[doc = "IGPIO3 interrupt through debounce (Interrupt set-enable bit)"]
289    #[inline(always)]
290    pub fn gpio3_irqn(
291        self,
292    ) -> crate::common::RegisterFieldBool<13, 1, 0, Iser_SPEC, crate::common::RW> {
293        crate::common::RegisterFieldBool::<13, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
294            self, 0,
295        )
296    }
297
298    #[doc = "GPIO4 interrupt through debounce (Interrupt set-enable bit)"]
299    #[inline(always)]
300    pub fn gpio4_irqn(
301        self,
302    ) -> crate::common::RegisterFieldBool<14, 1, 0, Iser_SPEC, crate::common::RW> {
303        crate::common::RegisterFieldBool::<14, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
304            self, 0,
305        )
306    }
307
308    #[doc = "Software timer Interrupt (set-enable bit)"]
309    #[inline(always)]
310    pub fn swtim_irqn(
311        self,
312    ) -> crate::common::RegisterFieldBool<15, 1, 0, Iser_SPEC, crate::common::RW> {
313        crate::common::RegisterFieldBool::<15, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
314            self, 0,
315        )
316    }
317
318    #[doc = "Combined Wake up Capture Timer, GPIO and QuadDecoder interrupt (set-enable bit)"]
319    #[inline(always)]
320    pub fn wkup_quadec_irqn(
321        self,
322    ) -> crate::common::RegisterFieldBool<16, 1, 0, Iser_SPEC, crate::common::RW> {
323        crate::common::RegisterFieldBool::<16, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
324            self, 0,
325        )
326    }
327
328    #[doc = "PCM Interrupt (set-enable bit)"]
329    #[inline(always)]
330    pub fn pcm_irqn(
331        self,
332    ) -> crate::common::RegisterFieldBool<17, 1, 0, Iser_SPEC, crate::common::RW> {
333        crate::common::RegisterFieldBool::<17, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
334            self, 0,
335        )
336    }
337
338    #[doc = "Sample rate converter input Interrupt (set-enable bit)"]
339    #[inline(always)]
340    pub fn src_in_irqn(
341        self,
342    ) -> crate::common::RegisterFieldBool<18, 1, 0, Iser_SPEC, crate::common::RW> {
343        crate::common::RegisterFieldBool::<18, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
344            self, 0,
345        )
346    }
347
348    #[doc = "Sample rate converter output Interrupt (set-enable bit)"]
349    #[inline(always)]
350    pub fn src_out_irqn(
351        self,
352    ) -> crate::common::RegisterFieldBool<19, 1, 0, Iser_SPEC, crate::common::RW> {
353        crate::common::RegisterFieldBool::<19, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
354            self, 0,
355        )
356    }
357
358    #[doc = "DMA Interrupt (set-enable bit)"]
359    #[inline(always)]
360    pub fn dma_irqn(
361        self,
362    ) -> crate::common::RegisterFieldBool<20, 1, 0, Iser_SPEC, crate::common::RW> {
363        crate::common::RegisterFieldBool::<20, 1, 0, Iser_SPEC, crate::common::RW>::from_register(
364            self, 0,
365        )
366    }
367}
368impl ::core::default::Default for Iser {
369    #[inline(always)]
370    fn default() -> Iser {
371        <crate::RegValueT<Iser_SPEC> as RegisterValue<_>>::new(0)
372    }
373}
374
375#[doc(hidden)]
376#[derive(Copy, Clone, Eq, PartialEq)]
377pub struct Icer_SPEC;
378impl crate::sealed::RegSpec for Icer_SPEC {
379    type DataType = u32;
380}
381
382#[doc = "Interrupt clear-enable register"]
383pub type Icer = crate::RegValueT<Icer_SPEC>;
384
385impl Icer {
386    #[doc = "BLE_WAKEUP_LP_IRQn (Interrupt clear-enable bit)"]
387    #[inline(always)]
388    pub fn ble_wakeup_lp_irqn(
389        self,
390    ) -> crate::common::RegisterFieldBool<0, 1, 0, Icer_SPEC, crate::common::RW> {
391        crate::common::RegisterFieldBool::<0, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
392            self, 0,
393        )
394    }
395
396    #[doc = "BLE_GEN_IRQn (Interrupt clear-enable bit)"]
397    #[inline(always)]
398    pub fn ble_gen_irqn(
399        self,
400    ) -> crate::common::RegisterFieldBool<1, 1, 0, Icer_SPEC, crate::common::RW> {
401        crate::common::RegisterFieldBool::<1, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
402            self, 0,
403        )
404    }
405
406    #[doc = "UART_IRQn (Interrupt clear-enable bit)"]
407    #[inline(always)]
408    pub fn uart_irqn(
409        self,
410    ) -> crate::common::RegisterFieldBool<2, 1, 0, Icer_SPEC, crate::common::RW> {
411        crate::common::RegisterFieldBool::<2, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
412            self, 0,
413        )
414    }
415
416    #[doc = "UART2_IRQn (Interrupt clear-enable bit)"]
417    #[inline(always)]
418    pub fn uart2_irqn(
419        self,
420    ) -> crate::common::RegisterFieldBool<3, 1, 0, Icer_SPEC, crate::common::RW> {
421        crate::common::RegisterFieldBool::<3, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
422            self, 0,
423        )
424    }
425
426    #[doc = "I2C_IRQn (Interrupt clear-enable bit)"]
427    #[inline(always)]
428    pub fn i2c_irqn(
429        self,
430    ) -> crate::common::RegisterFieldBool<4, 1, 0, Icer_SPEC, crate::common::RW> {
431        crate::common::RegisterFieldBool::<4, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
432            self, 0,
433        )
434    }
435
436    #[doc = "SPI_IRQn (Interrupt clear-enable bit)"]
437    #[inline(always)]
438    pub fn spi_irqn(
439        self,
440    ) -> crate::common::RegisterFieldBool<5, 1, 0, Icer_SPEC, crate::common::RW> {
441        crate::common::RegisterFieldBool::<5, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
442            self, 0,
443        )
444    }
445
446    #[doc = "ADC_IRQn (Interrupt clear-enable bit)"]
447    #[inline(always)]
448    pub fn adc_irqn(
449        self,
450    ) -> crate::common::RegisterFieldBool<6, 1, 0, Icer_SPEC, crate::common::RW> {
451        crate::common::RegisterFieldBool::<6, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
452            self, 0,
453        )
454    }
455
456    #[doc = "KEYBRD_IRQn (Interrupt clear-enable bit)"]
457    #[inline(always)]
458    pub fn keybrd_irqn(
459        self,
460    ) -> crate::common::RegisterFieldBool<7, 1, 0, Icer_SPEC, crate::common::RW> {
461        crate::common::RegisterFieldBool::<7, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
462            self, 0,
463        )
464    }
465
466    #[doc = "BLE baseband or Radio diagnostic (Interrupt clear-enable bit))"]
467    #[inline(always)]
468    pub fn ble_rf_diag_irqn(
469        self,
470    ) -> crate::common::RegisterFieldBool<8, 1, 0, Icer_SPEC, crate::common::RW> {
471        crate::common::RegisterFieldBool::<8, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
472            self, 0,
473        )
474    }
475
476    #[doc = "RFCAL_IRQn (Interrupt clear-enable bit)"]
477    #[inline(always)]
478    pub fn rfcal_irqn(
479        self,
480    ) -> crate::common::RegisterFieldBool<9, 1, 0, Icer_SPEC, crate::common::RW> {
481        crate::common::RegisterFieldBool::<9, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
482            self, 0,
483        )
484    }
485
486    #[doc = "GPIO0 interrupt through debounce (Interrupt clear-enable bit)"]
487    #[inline(always)]
488    pub fn gpio0_irqn(
489        self,
490    ) -> crate::common::RegisterFieldBool<10, 1, 0, Icer_SPEC, crate::common::RW> {
491        crate::common::RegisterFieldBool::<10, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
492            self, 0,
493        )
494    }
495
496    #[doc = "GPIO1 interrupt through debounce (Interrupt clear-enable bit)"]
497    #[inline(always)]
498    pub fn gpio1_irqn(
499        self,
500    ) -> crate::common::RegisterFieldBool<11, 1, 0, Icer_SPEC, crate::common::RW> {
501        crate::common::RegisterFieldBool::<11, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
502            self, 0,
503        )
504    }
505
506    #[doc = "GPIO2 interrupt through debounce (Interrupt clear-enable bit)"]
507    #[inline(always)]
508    pub fn gpio2_irqn(
509        self,
510    ) -> crate::common::RegisterFieldBool<12, 1, 0, Icer_SPEC, crate::common::RW> {
511        crate::common::RegisterFieldBool::<12, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
512            self, 0,
513        )
514    }
515
516    #[doc = "IGPIO3 interrupt through debounce (Interrupt clear-enable bit)"]
517    #[inline(always)]
518    pub fn gpio3_irqn(
519        self,
520    ) -> crate::common::RegisterFieldBool<13, 1, 0, Icer_SPEC, crate::common::RW> {
521        crate::common::RegisterFieldBool::<13, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
522            self, 0,
523        )
524    }
525
526    #[doc = "GPIO4 interrupt through debounce (Interrupt clear-enable bit)"]
527    #[inline(always)]
528    pub fn gpio4_irqn(
529        self,
530    ) -> crate::common::RegisterFieldBool<14, 1, 0, Icer_SPEC, crate::common::RW> {
531        crate::common::RegisterFieldBool::<14, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
532            self, 0,
533        )
534    }
535
536    #[doc = "Software timer Interrupt (clear-enable bit)"]
537    #[inline(always)]
538    pub fn swtim_irqn(
539        self,
540    ) -> crate::common::RegisterFieldBool<15, 1, 0, Icer_SPEC, crate::common::RW> {
541        crate::common::RegisterFieldBool::<15, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
542            self, 0,
543        )
544    }
545
546    #[doc = "Combined Wake up Capture Timer, GPIO and QuadDecoder interrupt (clear-enable bit)"]
547    #[inline(always)]
548    pub fn wkup_quadec_irqn(
549        self,
550    ) -> crate::common::RegisterFieldBool<16, 1, 0, Icer_SPEC, crate::common::RW> {
551        crate::common::RegisterFieldBool::<16, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
552            self, 0,
553        )
554    }
555
556    #[doc = "PCM Interrupt (clear-enable bit)"]
557    #[inline(always)]
558    pub fn pcm_irqn(
559        self,
560    ) -> crate::common::RegisterFieldBool<17, 1, 0, Icer_SPEC, crate::common::RW> {
561        crate::common::RegisterFieldBool::<17, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
562            self, 0,
563        )
564    }
565
566    #[doc = "Sample rate converter input Interrupt (clear-enable bit)"]
567    #[inline(always)]
568    pub fn src_in_irqn(
569        self,
570    ) -> crate::common::RegisterFieldBool<18, 1, 0, Icer_SPEC, crate::common::RW> {
571        crate::common::RegisterFieldBool::<18, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
572            self, 0,
573        )
574    }
575
576    #[doc = "Sample rate converter output Interrupt (clear-enable bit)"]
577    #[inline(always)]
578    pub fn src_out_irqn(
579        self,
580    ) -> crate::common::RegisterFieldBool<19, 1, 0, Icer_SPEC, crate::common::RW> {
581        crate::common::RegisterFieldBool::<19, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
582            self, 0,
583        )
584    }
585
586    #[doc = "DMA Interrupt (clear-enable bit)"]
587    #[inline(always)]
588    pub fn dma_irqn(
589        self,
590    ) -> crate::common::RegisterFieldBool<20, 1, 0, Icer_SPEC, crate::common::RW> {
591        crate::common::RegisterFieldBool::<20, 1, 0, Icer_SPEC, crate::common::RW>::from_register(
592            self, 0,
593        )
594    }
595}
596impl ::core::default::Default for Icer {
597    #[inline(always)]
598    fn default() -> Icer {
599        <crate::RegValueT<Icer_SPEC> as RegisterValue<_>>::new(0)
600    }
601}
602
603#[doc(hidden)]
604#[derive(Copy, Clone, Eq, PartialEq)]
605pub struct Ispr_SPEC;
606impl crate::sealed::RegSpec for Ispr_SPEC {
607    type DataType = u32;
608}
609
610#[doc = "Interrupt set-pending register"]
611pub type Ispr = crate::RegValueT<Ispr_SPEC>;
612
613impl Ispr {
614    #[doc = "BLE_WAKEUP_LP_IRQn (Interrupt set-pending bit)"]
615    #[inline(always)]
616    pub fn ble_wakeup_lp_irqn(
617        self,
618    ) -> crate::common::RegisterFieldBool<0, 1, 0, Ispr_SPEC, crate::common::RW> {
619        crate::common::RegisterFieldBool::<0, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
620            self, 0,
621        )
622    }
623
624    #[doc = "BLE_GEN_IRQn (Interrupt set-pending bit)"]
625    #[inline(always)]
626    pub fn ble_gen_irqn(
627        self,
628    ) -> crate::common::RegisterFieldBool<1, 1, 0, Ispr_SPEC, crate::common::RW> {
629        crate::common::RegisterFieldBool::<1, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
630            self, 0,
631        )
632    }
633
634    #[doc = "UART_IRQn (Interrupt set-pending bit)"]
635    #[inline(always)]
636    pub fn uart_irqn(
637        self,
638    ) -> crate::common::RegisterFieldBool<2, 1, 0, Ispr_SPEC, crate::common::RW> {
639        crate::common::RegisterFieldBool::<2, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
640            self, 0,
641        )
642    }
643
644    #[doc = "UART2_IRQn (Interrupt set-pending bit)"]
645    #[inline(always)]
646    pub fn uart2_irqn(
647        self,
648    ) -> crate::common::RegisterFieldBool<3, 1, 0, Ispr_SPEC, crate::common::RW> {
649        crate::common::RegisterFieldBool::<3, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
650            self, 0,
651        )
652    }
653
654    #[doc = "I2C_IRQn (Interrupt set-pending bit)"]
655    #[inline(always)]
656    pub fn i2c_irqn(
657        self,
658    ) -> crate::common::RegisterFieldBool<4, 1, 0, Ispr_SPEC, crate::common::RW> {
659        crate::common::RegisterFieldBool::<4, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
660            self, 0,
661        )
662    }
663
664    #[doc = "SPI_IRQn (Interrupt set-pending bit)"]
665    #[inline(always)]
666    pub fn spi_irqn(
667        self,
668    ) -> crate::common::RegisterFieldBool<5, 1, 0, Ispr_SPEC, crate::common::RW> {
669        crate::common::RegisterFieldBool::<5, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
670            self, 0,
671        )
672    }
673
674    #[doc = "ADC_IRQn (Interrupt set-pending bit)"]
675    #[inline(always)]
676    pub fn adc_irqn(
677        self,
678    ) -> crate::common::RegisterFieldBool<6, 1, 0, Ispr_SPEC, crate::common::RW> {
679        crate::common::RegisterFieldBool::<6, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
680            self, 0,
681        )
682    }
683
684    #[doc = "KEYBRD_IRQn (Interrupt set-pending bit)"]
685    #[inline(always)]
686    pub fn keybrd_irqn(
687        self,
688    ) -> crate::common::RegisterFieldBool<7, 1, 0, Ispr_SPEC, crate::common::RW> {
689        crate::common::RegisterFieldBool::<7, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
690            self, 0,
691        )
692    }
693
694    #[doc = "BLE baseband or Radio diagnostic (Interrupt set-pending bit))"]
695    #[inline(always)]
696    pub fn ble_rf_diag_irqn(
697        self,
698    ) -> crate::common::RegisterFieldBool<8, 1, 0, Ispr_SPEC, crate::common::RW> {
699        crate::common::RegisterFieldBool::<8, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
700            self, 0,
701        )
702    }
703
704    #[doc = "RFCAL_IRQn (Interrupt set-pending bit)"]
705    #[inline(always)]
706    pub fn rfcal_irqn(
707        self,
708    ) -> crate::common::RegisterFieldBool<9, 1, 0, Ispr_SPEC, crate::common::RW> {
709        crate::common::RegisterFieldBool::<9, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
710            self, 0,
711        )
712    }
713
714    #[doc = "GPIO0 interrupt through debounce (Interrupt set-pending bit)"]
715    #[inline(always)]
716    pub fn gpio0_irqn(
717        self,
718    ) -> crate::common::RegisterFieldBool<10, 1, 0, Ispr_SPEC, crate::common::RW> {
719        crate::common::RegisterFieldBool::<10, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
720            self, 0,
721        )
722    }
723
724    #[doc = "GPIO1 interrupt through debounce (Interrupt set-pending bit)"]
725    #[inline(always)]
726    pub fn gpio1_irqn(
727        self,
728    ) -> crate::common::RegisterFieldBool<11, 1, 0, Ispr_SPEC, crate::common::RW> {
729        crate::common::RegisterFieldBool::<11, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
730            self, 0,
731        )
732    }
733
734    #[doc = "GPIO2 interrupt through debounce (Interrupt set-pending bit)"]
735    #[inline(always)]
736    pub fn gpio2_irqn(
737        self,
738    ) -> crate::common::RegisterFieldBool<12, 1, 0, Ispr_SPEC, crate::common::RW> {
739        crate::common::RegisterFieldBool::<12, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
740            self, 0,
741        )
742    }
743
744    #[doc = "IGPIO3 interrupt through debounce (Interrupt set-pending bit)"]
745    #[inline(always)]
746    pub fn gpio3_irqn(
747        self,
748    ) -> crate::common::RegisterFieldBool<13, 1, 0, Ispr_SPEC, crate::common::RW> {
749        crate::common::RegisterFieldBool::<13, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
750            self, 0,
751        )
752    }
753
754    #[doc = "GPIO4 interrupt through debounce (Interrupt set-pending bit)"]
755    #[inline(always)]
756    pub fn gpio4_irqn(
757        self,
758    ) -> crate::common::RegisterFieldBool<14, 1, 0, Ispr_SPEC, crate::common::RW> {
759        crate::common::RegisterFieldBool::<14, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
760            self, 0,
761        )
762    }
763
764    #[doc = "Software timer Interrupt (set-pending bit)"]
765    #[inline(always)]
766    pub fn swtim_irqn(
767        self,
768    ) -> crate::common::RegisterFieldBool<15, 1, 0, Ispr_SPEC, crate::common::RW> {
769        crate::common::RegisterFieldBool::<15, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
770            self, 0,
771        )
772    }
773
774    #[doc = "Combined Wake up Capture Timer, GPIO and QuadDecoder interrupt (set-pending bit)"]
775    #[inline(always)]
776    pub fn wkup_quadec_irqn(
777        self,
778    ) -> crate::common::RegisterFieldBool<16, 1, 0, Ispr_SPEC, crate::common::RW> {
779        crate::common::RegisterFieldBool::<16, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
780            self, 0,
781        )
782    }
783
784    #[doc = "PCM Interrupt (set-pending bit)"]
785    #[inline(always)]
786    pub fn pcm_irqn(
787        self,
788    ) -> crate::common::RegisterFieldBool<17, 1, 0, Ispr_SPEC, crate::common::RW> {
789        crate::common::RegisterFieldBool::<17, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
790            self, 0,
791        )
792    }
793
794    #[doc = "Sample rate converter input Interrupt (set-pending bit)"]
795    #[inline(always)]
796    pub fn src_in_irqn(
797        self,
798    ) -> crate::common::RegisterFieldBool<18, 1, 0, Ispr_SPEC, crate::common::RW> {
799        crate::common::RegisterFieldBool::<18, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
800            self, 0,
801        )
802    }
803
804    #[doc = "Sample rate converter output Interrupt (set-pending bit)"]
805    #[inline(always)]
806    pub fn src_out_irqn(
807        self,
808    ) -> crate::common::RegisterFieldBool<19, 1, 0, Ispr_SPEC, crate::common::RW> {
809        crate::common::RegisterFieldBool::<19, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
810            self, 0,
811        )
812    }
813
814    #[doc = "DMA Interrupt (set-pending bit)"]
815    #[inline(always)]
816    pub fn dma_irqn(
817        self,
818    ) -> crate::common::RegisterFieldBool<20, 1, 0, Ispr_SPEC, crate::common::RW> {
819        crate::common::RegisterFieldBool::<20, 1, 0, Ispr_SPEC, crate::common::RW>::from_register(
820            self, 0,
821        )
822    }
823}
824impl ::core::default::Default for Ispr {
825    #[inline(always)]
826    fn default() -> Ispr {
827        <crate::RegValueT<Ispr_SPEC> as RegisterValue<_>>::new(0)
828    }
829}
830
831#[doc(hidden)]
832#[derive(Copy, Clone, Eq, PartialEq)]
833pub struct Icpr_SPEC;
834impl crate::sealed::RegSpec for Icpr_SPEC {
835    type DataType = u32;
836}
837
838#[doc = "Interrupt clear-pending register"]
839pub type Icpr = crate::RegValueT<Icpr_SPEC>;
840
841impl Icpr {
842    #[doc = "BLE_WAKEUP_LP_IRQn (Interrupt clear-pending bit)"]
843    #[inline(always)]
844    pub fn ble_wakeup_lp_irqn(
845        self,
846    ) -> crate::common::RegisterFieldBool<0, 1, 0, Icpr_SPEC, crate::common::RW> {
847        crate::common::RegisterFieldBool::<0, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
848            self, 0,
849        )
850    }
851
852    #[doc = "BLE_GEN_IRQn (Interrupt clear-pending bit)"]
853    #[inline(always)]
854    pub fn ble_gen_irqn(
855        self,
856    ) -> crate::common::RegisterFieldBool<1, 1, 0, Icpr_SPEC, crate::common::RW> {
857        crate::common::RegisterFieldBool::<1, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
858            self, 0,
859        )
860    }
861
862    #[doc = "UART_IRQn (Interrupt clear-pending bit)"]
863    #[inline(always)]
864    pub fn uart_irqn(
865        self,
866    ) -> crate::common::RegisterFieldBool<2, 1, 0, Icpr_SPEC, crate::common::RW> {
867        crate::common::RegisterFieldBool::<2, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
868            self, 0,
869        )
870    }
871
872    #[doc = "UART2_IRQn (Interrupt clear-pending bit)"]
873    #[inline(always)]
874    pub fn uart2_irqn(
875        self,
876    ) -> crate::common::RegisterFieldBool<3, 1, 0, Icpr_SPEC, crate::common::RW> {
877        crate::common::RegisterFieldBool::<3, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
878            self, 0,
879        )
880    }
881
882    #[doc = "I2C_IRQn (Interrupt clear-pending bit)"]
883    #[inline(always)]
884    pub fn i2c_irqn(
885        self,
886    ) -> crate::common::RegisterFieldBool<4, 1, 0, Icpr_SPEC, crate::common::RW> {
887        crate::common::RegisterFieldBool::<4, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
888            self, 0,
889        )
890    }
891
892    #[doc = "SPI_IRQn (Interrupt clear-pending bit)"]
893    #[inline(always)]
894    pub fn spi_irqn(
895        self,
896    ) -> crate::common::RegisterFieldBool<5, 1, 0, Icpr_SPEC, crate::common::RW> {
897        crate::common::RegisterFieldBool::<5, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
898            self, 0,
899        )
900    }
901
902    #[doc = "ADC_IRQn (Interrupt clear-pending bit)"]
903    #[inline(always)]
904    pub fn adc_irqn(
905        self,
906    ) -> crate::common::RegisterFieldBool<6, 1, 0, Icpr_SPEC, crate::common::RW> {
907        crate::common::RegisterFieldBool::<6, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
908            self, 0,
909        )
910    }
911
912    #[doc = "KEYBRD_IRQn (Interrupt clear-pending bit)"]
913    #[inline(always)]
914    pub fn keybrd_irqn(
915        self,
916    ) -> crate::common::RegisterFieldBool<7, 1, 0, Icpr_SPEC, crate::common::RW> {
917        crate::common::RegisterFieldBool::<7, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
918            self, 0,
919        )
920    }
921
922    #[doc = "BLE baseband or Radio diagnostic (Interrupt clear-pending bit))"]
923    #[inline(always)]
924    pub fn ble_rf_diag_irqn(
925        self,
926    ) -> crate::common::RegisterFieldBool<8, 1, 0, Icpr_SPEC, crate::common::RW> {
927        crate::common::RegisterFieldBool::<8, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
928            self, 0,
929        )
930    }
931
932    #[doc = "RFCAL_IRQn (Interrupt clear-pending bit)"]
933    #[inline(always)]
934    pub fn rfcal_irqn(
935        self,
936    ) -> crate::common::RegisterFieldBool<9, 1, 0, Icpr_SPEC, crate::common::RW> {
937        crate::common::RegisterFieldBool::<9, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
938            self, 0,
939        )
940    }
941
942    #[doc = "GPIO0 interrupt through debounce (Interrupt clear-pending bit)"]
943    #[inline(always)]
944    pub fn gpio0_irqn(
945        self,
946    ) -> crate::common::RegisterFieldBool<10, 1, 0, Icpr_SPEC, crate::common::RW> {
947        crate::common::RegisterFieldBool::<10, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
948            self, 0,
949        )
950    }
951
952    #[doc = "GPIO1 interrupt through debounce (Interrupt clear-pending bit)"]
953    #[inline(always)]
954    pub fn gpio1_irqn(
955        self,
956    ) -> crate::common::RegisterFieldBool<11, 1, 0, Icpr_SPEC, crate::common::RW> {
957        crate::common::RegisterFieldBool::<11, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
958            self, 0,
959        )
960    }
961
962    #[doc = "GPIO2 interrupt through debounce (Interrupt clear-pending bit)"]
963    #[inline(always)]
964    pub fn gpio2_irqn(
965        self,
966    ) -> crate::common::RegisterFieldBool<12, 1, 0, Icpr_SPEC, crate::common::RW> {
967        crate::common::RegisterFieldBool::<12, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
968            self, 0,
969        )
970    }
971
972    #[doc = "IGPIO3 interrupt through debounce (Interrupt clear-pending bit)"]
973    #[inline(always)]
974    pub fn gpio3_irqn(
975        self,
976    ) -> crate::common::RegisterFieldBool<13, 1, 0, Icpr_SPEC, crate::common::RW> {
977        crate::common::RegisterFieldBool::<13, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
978            self, 0,
979        )
980    }
981
982    #[doc = "GPIO4 interrupt through debounce (Interrupt clear-pending bit)"]
983    #[inline(always)]
984    pub fn gpio4_irqn(
985        self,
986    ) -> crate::common::RegisterFieldBool<14, 1, 0, Icpr_SPEC, crate::common::RW> {
987        crate::common::RegisterFieldBool::<14, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
988            self, 0,
989        )
990    }
991
992    #[doc = "Software timer Interrupt (clear-pending bit)"]
993    #[inline(always)]
994    pub fn swtim_irqn(
995        self,
996    ) -> crate::common::RegisterFieldBool<15, 1, 0, Icpr_SPEC, crate::common::RW> {
997        crate::common::RegisterFieldBool::<15, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
998            self, 0,
999        )
1000    }
1001
1002    #[doc = "Combined Wake up Capture Timer, GPIO and QuadDecoder interrupt (clear-pending bit)"]
1003    #[inline(always)]
1004    pub fn wkup_quadec_irqn(
1005        self,
1006    ) -> crate::common::RegisterFieldBool<16, 1, 0, Icpr_SPEC, crate::common::RW> {
1007        crate::common::RegisterFieldBool::<16, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
1008            self, 0,
1009        )
1010    }
1011
1012    #[doc = "PCM Interrupt (clear-pending bit)"]
1013    #[inline(always)]
1014    pub fn pcm_irqn(
1015        self,
1016    ) -> crate::common::RegisterFieldBool<17, 1, 0, Icpr_SPEC, crate::common::RW> {
1017        crate::common::RegisterFieldBool::<17, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
1018            self, 0,
1019        )
1020    }
1021
1022    #[doc = "Sample rate converter input Interrupt (clear-pending bit)"]
1023    #[inline(always)]
1024    pub fn src_in_irqn(
1025        self,
1026    ) -> crate::common::RegisterFieldBool<18, 1, 0, Icpr_SPEC, crate::common::RW> {
1027        crate::common::RegisterFieldBool::<18, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
1028            self, 0,
1029        )
1030    }
1031
1032    #[doc = "Sample rate converter output Interrupt (clear-pending bit)"]
1033    #[inline(always)]
1034    pub fn src_out_irqn(
1035        self,
1036    ) -> crate::common::RegisterFieldBool<19, 1, 0, Icpr_SPEC, crate::common::RW> {
1037        crate::common::RegisterFieldBool::<19, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
1038            self, 0,
1039        )
1040    }
1041
1042    #[doc = "DMA Interrupt (clear-pending bit)"]
1043    #[inline(always)]
1044    pub fn dma_irqn(
1045        self,
1046    ) -> crate::common::RegisterFieldBool<20, 1, 0, Icpr_SPEC, crate::common::RW> {
1047        crate::common::RegisterFieldBool::<20, 1, 0, Icpr_SPEC, crate::common::RW>::from_register(
1048            self, 0,
1049        )
1050    }
1051}
1052impl ::core::default::Default for Icpr {
1053    #[inline(always)]
1054    fn default() -> Icpr {
1055        <crate::RegValueT<Icpr_SPEC> as RegisterValue<_>>::new(0)
1056    }
1057}
1058
1059#[doc(hidden)]
1060#[derive(Copy, Clone, Eq, PartialEq)]
1061pub struct Ipr0_SPEC;
1062impl crate::sealed::RegSpec for Ipr0_SPEC {
1063    type DataType = u32;
1064}
1065
1066#[doc = "Interrupt priority register 0"]
1067pub type Ipr0 = crate::RegValueT<Ipr0_SPEC>;
1068
1069impl Ipr0 {
1070    #[doc = "BLE_WAKEUP_LP_IRQn\\[7:0\\] bits (Interrupt priority)"]
1071    #[inline(always)]
1072    pub fn ble_wakeup_lp_irqn_prio(
1073        self,
1074    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Ipr0_SPEC, crate::common::RW> {
1075        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Ipr0_SPEC,crate::common::RW>::from_register(self,0)
1076    }
1077
1078    #[doc = "BLE_GEN_IRQn\\[7:0\\] bits (Interrupt priority)"]
1079    #[inline(always)]
1080    pub fn ble_gen_irqn_prio(
1081        self,
1082    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Ipr0_SPEC, crate::common::RW> {
1083        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Ipr0_SPEC,crate::common::RW>::from_register(self,0)
1084    }
1085
1086    #[doc = "UART_IRQn\\[7:0\\] bits (Interrupt priority)"]
1087    #[inline(always)]
1088    pub fn uart_irqn_prio(
1089        self,
1090    ) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Ipr0_SPEC, crate::common::RW> {
1091        crate::common::RegisterField::<16,0xff,1,0,u8,u8,Ipr0_SPEC,crate::common::RW>::from_register(self,0)
1092    }
1093
1094    #[doc = "UART2_IRQn\\[7:0\\] bits (Interrupt priority)"]
1095    #[inline(always)]
1096    pub fn uart2_irqn_prio(
1097        self,
1098    ) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Ipr0_SPEC, crate::common::RW> {
1099        crate::common::RegisterField::<24,0xff,1,0,u8,u8,Ipr0_SPEC,crate::common::RW>::from_register(self,0)
1100    }
1101}
1102impl ::core::default::Default for Ipr0 {
1103    #[inline(always)]
1104    fn default() -> Ipr0 {
1105        <crate::RegValueT<Ipr0_SPEC> as RegisterValue<_>>::new(0)
1106    }
1107}
1108
1109#[doc(hidden)]
1110#[derive(Copy, Clone, Eq, PartialEq)]
1111pub struct Ipr1_SPEC;
1112impl crate::sealed::RegSpec for Ipr1_SPEC {
1113    type DataType = u32;
1114}
1115
1116#[doc = "Interrupt priority register 1"]
1117pub type Ipr1 = crate::RegValueT<Ipr1_SPEC>;
1118
1119impl Ipr1 {
1120    #[doc = "I2C_IRQn\\[7:0\\] bits (Interrupt priority)"]
1121    #[inline(always)]
1122    pub fn i2c_irqn_prio(
1123        self,
1124    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Ipr1_SPEC, crate::common::RW> {
1125        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Ipr1_SPEC,crate::common::RW>::from_register(self,0)
1126    }
1127
1128    #[doc = "SPI_IRQn\\[7:0\\] bits (Interrupt priority)"]
1129    #[inline(always)]
1130    pub fn spi_irqn_prio(
1131        self,
1132    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Ipr1_SPEC, crate::common::RW> {
1133        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Ipr1_SPEC,crate::common::RW>::from_register(self,0)
1134    }
1135
1136    #[doc = "ADC_IRQn\\[7:0\\] bits (Interrupt priority)"]
1137    #[inline(always)]
1138    pub fn adc_irqn_prio(
1139        self,
1140    ) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Ipr1_SPEC, crate::common::RW> {
1141        crate::common::RegisterField::<16,0xff,1,0,u8,u8,Ipr1_SPEC,crate::common::RW>::from_register(self,0)
1142    }
1143
1144    #[doc = "KEYBRD_IRQn\\[7:0\\] bits (Interrupt priority)"]
1145    #[inline(always)]
1146    pub fn keybrd_irqn_prio(
1147        self,
1148    ) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Ipr1_SPEC, crate::common::RW> {
1149        crate::common::RegisterField::<24,0xff,1,0,u8,u8,Ipr1_SPEC,crate::common::RW>::from_register(self,0)
1150    }
1151}
1152impl ::core::default::Default for Ipr1 {
1153    #[inline(always)]
1154    fn default() -> Ipr1 {
1155        <crate::RegValueT<Ipr1_SPEC> as RegisterValue<_>>::new(0)
1156    }
1157}
1158
1159#[doc(hidden)]
1160#[derive(Copy, Clone, Eq, PartialEq)]
1161pub struct Ipr2_SPEC;
1162impl crate::sealed::RegSpec for Ipr2_SPEC {
1163    type DataType = u32;
1164}
1165
1166#[doc = "Interrupt priority register 2"]
1167pub type Ipr2 = crate::RegValueT<Ipr2_SPEC>;
1168
1169impl Ipr2 {
1170    #[doc = "BLE_RF_DIAG_IRQn\\[7:0\\] bits (Interrupt priority)"]
1171    #[inline(always)]
1172    pub fn ble_rf_diag_irqn_prio(
1173        self,
1174    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Ipr2_SPEC, crate::common::RW> {
1175        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Ipr2_SPEC,crate::common::RW>::from_register(self,0)
1176    }
1177
1178    #[doc = "RF_CAL_IRQn\\[7:0\\] bits (Interrupt priority)"]
1179    #[inline(always)]
1180    pub fn rf_cal_irqn_prio(
1181        self,
1182    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Ipr2_SPEC, crate::common::RW> {
1183        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Ipr2_SPEC,crate::common::RW>::from_register(self,0)
1184    }
1185
1186    #[doc = "GPIO0_IRQn\\[7:0\\] bits (Interrupt priority)"]
1187    #[inline(always)]
1188    pub fn gpio0_irqn_prio(
1189        self,
1190    ) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Ipr2_SPEC, crate::common::RW> {
1191        crate::common::RegisterField::<16,0xff,1,0,u8,u8,Ipr2_SPEC,crate::common::RW>::from_register(self,0)
1192    }
1193
1194    #[doc = "GPIO1_IRQn\\[7:0\\] bits (Interrupt priority)"]
1195    #[inline(always)]
1196    pub fn gpio1_irqn_prio(
1197        self,
1198    ) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Ipr2_SPEC, crate::common::RW> {
1199        crate::common::RegisterField::<24,0xff,1,0,u8,u8,Ipr2_SPEC,crate::common::RW>::from_register(self,0)
1200    }
1201}
1202impl ::core::default::Default for Ipr2 {
1203    #[inline(always)]
1204    fn default() -> Ipr2 {
1205        <crate::RegValueT<Ipr2_SPEC> as RegisterValue<_>>::new(0)
1206    }
1207}
1208
1209#[doc(hidden)]
1210#[derive(Copy, Clone, Eq, PartialEq)]
1211pub struct Ipr3_SPEC;
1212impl crate::sealed::RegSpec for Ipr3_SPEC {
1213    type DataType = u32;
1214}
1215
1216#[doc = "Interrupt priority register 3"]
1217pub type Ipr3 = crate::RegValueT<Ipr3_SPEC>;
1218
1219impl Ipr3 {
1220    #[doc = "SPI_IRQn\\[7:0\\] bits (Interrupt priority)"]
1221    #[inline(always)]
1222    pub fn spi_irqn_prio(
1223        self,
1224    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Ipr3_SPEC, crate::common::RW> {
1225        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Ipr3_SPEC,crate::common::RW>::from_register(self,0)
1226    }
1227
1228    #[doc = "SPI2_IRQn\\[7:0\\] bits (Interrupt priority)"]
1229    #[inline(always)]
1230    pub fn spi2_irqn_prio(
1231        self,
1232    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Ipr3_SPEC, crate::common::RW> {
1233        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Ipr3_SPEC,crate::common::RW>::from_register(self,0)
1234    }
1235
1236    #[doc = "ADC_IRQn\\[7:0\\] bits (Interrupt priority)"]
1237    #[inline(always)]
1238    pub fn adc_irqn_prio(
1239        self,
1240    ) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Ipr3_SPEC, crate::common::RW> {
1241        crate::common::RegisterField::<16,0xff,1,0,u8,u8,Ipr3_SPEC,crate::common::RW>::from_register(self,0)
1242    }
1243
1244    #[doc = "KEYBRD_IRQn\\[7:0\\] bits (Interrupt priority)"]
1245    #[inline(always)]
1246    pub fn keybrd_irqn_prio(
1247        self,
1248    ) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Ipr3_SPEC, crate::common::RW> {
1249        crate::common::RegisterField::<24,0xff,1,0,u8,u8,Ipr3_SPEC,crate::common::RW>::from_register(self,0)
1250    }
1251}
1252impl ::core::default::Default for Ipr3 {
1253    #[inline(always)]
1254    fn default() -> Ipr3 {
1255        <crate::RegValueT<Ipr3_SPEC> as RegisterValue<_>>::new(0)
1256    }
1257}
1258
1259#[doc(hidden)]
1260#[derive(Copy, Clone, Eq, PartialEq)]
1261pub struct Ipr4_SPEC;
1262impl crate::sealed::RegSpec for Ipr4_SPEC {
1263    type DataType = u32;
1264}
1265
1266#[doc = "Interrupt priority register 4"]
1267pub type Ipr4 = crate::RegValueT<Ipr4_SPEC>;
1268
1269impl Ipr4 {
1270    #[doc = "GPIO2_IRQn\\[7:0\\] bits (Interrupt priority)"]
1271    #[inline(always)]
1272    pub fn gpio2_irqn_prio(
1273        self,
1274    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Ipr4_SPEC, crate::common::RW> {
1275        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Ipr4_SPEC,crate::common::RW>::from_register(self,0)
1276    }
1277
1278    #[doc = "GPIO3_IRQn\\[7:0\\] bits (Interrupt priority)"]
1279    #[inline(always)]
1280    pub fn gpio3_irqn_prio(
1281        self,
1282    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Ipr4_SPEC, crate::common::RW> {
1283        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Ipr4_SPEC,crate::common::RW>::from_register(self,0)
1284    }
1285
1286    #[doc = "GPIO4_IRQn\\[7:0\\] bits (Interrupt priority)"]
1287    #[inline(always)]
1288    pub fn gpio4_irqn_prio(
1289        self,
1290    ) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Ipr4_SPEC, crate::common::RW> {
1291        crate::common::RegisterField::<16,0xff,1,0,u8,u8,Ipr4_SPEC,crate::common::RW>::from_register(self,0)
1292    }
1293
1294    #[doc = "SWTIM_IRQn\\[7:0\\] bits (Interrupt priority)"]
1295    #[inline(always)]
1296    pub fn swtim_irqn_prio(
1297        self,
1298    ) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Ipr4_SPEC, crate::common::RW> {
1299        crate::common::RegisterField::<24,0xff,1,0,u8,u8,Ipr4_SPEC,crate::common::RW>::from_register(self,0)
1300    }
1301}
1302impl ::core::default::Default for Ipr4 {
1303    #[inline(always)]
1304    fn default() -> Ipr4 {
1305        <crate::RegValueT<Ipr4_SPEC> as RegisterValue<_>>::new(0)
1306    }
1307}
1308
1309#[doc(hidden)]
1310#[derive(Copy, Clone, Eq, PartialEq)]
1311pub struct Ipr5_SPEC;
1312impl crate::sealed::RegSpec for Ipr5_SPEC {
1313    type DataType = u32;
1314}
1315
1316#[doc = "Interrupt priority register 5"]
1317pub type Ipr5 = crate::RegValueT<Ipr5_SPEC>;
1318
1319impl Ipr5 {
1320    #[doc = "WKUP_QUADEC_IRQn\\[7:0\\] bits (Interrupt priority)"]
1321    #[inline(always)]
1322    pub fn wkup_quadec_irqn_prio(
1323        self,
1324    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Ipr5_SPEC, crate::common::RW> {
1325        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Ipr5_SPEC,crate::common::RW>::from_register(self,0)
1326    }
1327
1328    #[doc = "PCM_IRQn\\[7:0\\] bits (Interrupt priority)"]
1329    #[inline(always)]
1330    pub fn pcm_irqn_prio(
1331        self,
1332    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Ipr5_SPEC, crate::common::RW> {
1333        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Ipr5_SPEC,crate::common::RW>::from_register(self,0)
1334    }
1335
1336    #[doc = "SRC_IN_IRQn\\[7:0\\] bits (Interrupt priority)"]
1337    #[inline(always)]
1338    pub fn src_in_irqn_prio(
1339        self,
1340    ) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Ipr5_SPEC, crate::common::RW> {
1341        crate::common::RegisterField::<16,0xff,1,0,u8,u8,Ipr5_SPEC,crate::common::RW>::from_register(self,0)
1342    }
1343
1344    #[doc = "SRC_OUT_IRQn\\[7:0\\] bits (Interrupt priority)"]
1345    #[inline(always)]
1346    pub fn src_out_irqn_prio(
1347        self,
1348    ) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Ipr5_SPEC, crate::common::RW> {
1349        crate::common::RegisterField::<24,0xff,1,0,u8,u8,Ipr5_SPEC,crate::common::RW>::from_register(self,0)
1350    }
1351}
1352impl ::core::default::Default for Ipr5 {
1353    #[inline(always)]
1354    fn default() -> Ipr5 {
1355        <crate::RegValueT<Ipr5_SPEC> as RegisterValue<_>>::new(0)
1356    }
1357}
1358
1359#[doc(hidden)]
1360#[derive(Copy, Clone, Eq, PartialEq)]
1361pub struct Ipr6_SPEC;
1362impl crate::sealed::RegSpec for Ipr6_SPEC {
1363    type DataType = u32;
1364}
1365
1366#[doc = "Interrupt priority register 6"]
1367pub type Ipr6 = crate::RegValueT<Ipr6_SPEC>;
1368
1369impl Ipr6 {
1370    #[doc = "DMA_IRQn\\[7:0\\] bits (Interrupt priority)"]
1371    #[inline(always)]
1372    pub fn dma_irqn_prio(
1373        self,
1374    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Ipr6_SPEC, crate::common::RW> {
1375        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Ipr6_SPEC,crate::common::RW>::from_register(self,0)
1376    }
1377}
1378impl ::core::default::Default for Ipr6 {
1379    #[inline(always)]
1380    fn default() -> Ipr6 {
1381        <crate::RegValueT<Ipr6_SPEC> as RegisterValue<_>>::new(0)
1382    }
1383}
da14580_pac/nvic.rs

da14580_pac/
nvic.rs
