1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"ANAMISC registers"]
28unsafe impl ::core::marker::Send for super::Anamisc {}
29unsafe impl ::core::marker::Sync for super::Anamisc {}
30impl super::Anamisc {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Count value for oscillator calibration"]
38 #[inline(always)]
39 pub const fn clk_ref_cnt_reg(
40 &self,
41 ) -> &'static crate::common::Reg<self::ClkRefCntReg_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::ClkRefCntReg_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(2usize),
45 )
46 }
47 }
48
49 #[doc = "Select clock for oscillator calibration"]
50 #[inline(always)]
51 pub const fn clk_ref_sel_reg(
52 &self,
53 ) -> &'static crate::common::Reg<self::ClkRefSelReg_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::ClkRefSelReg_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(0usize),
57 )
58 }
59 }
60
61 #[doc = "XTAL32M reference cycles, higher 16 bits"]
62 #[inline(always)]
63 pub const fn clk_ref_val_h_reg(
64 &self,
65 ) -> &'static crate::common::Reg<self::ClkRefValHReg_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::ClkRefValHReg_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(6usize),
69 )
70 }
71 }
72
73 #[doc = "XTAL32M reference cycles, lower 16 bits"]
74 #[inline(always)]
75 pub const fn clk_ref_val_l_reg(
76 &self,
77 ) -> &'static crate::common::Reg<self::ClkRefValLReg_SPEC, crate::common::RW> {
78 unsafe {
79 crate::common::Reg::<self::ClkRefValLReg_SPEC, crate::common::RW>::from_ptr(
80 self._svd2pac_as_ptr().add(4usize),
81 )
82 }
83 }
84}
85#[doc(hidden)]
86#[derive(Copy, Clone, Eq, PartialEq)]
87pub struct ClkRefCntReg_SPEC;
88impl crate::sealed::RegSpec for ClkRefCntReg_SPEC {
89 type DataType = u16;
90}
91
92#[doc = "Count value for oscillator calibration"]
93pub type ClkRefCntReg = crate::RegValueT<ClkRefCntReg_SPEC>;
94
95impl ClkRefCntReg {
96 #[doc = "Indicates the calibration time, with a decrement counter to 1."]
97 #[inline(always)]
98 pub fn ref_cnt_val(
99 self,
100 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, ClkRefCntReg_SPEC, crate::common::RW>
101 {
102 crate::common::RegisterField::<
103 0,
104 0xffff,
105 1,
106 0,
107 u16,
108 u16,
109 ClkRefCntReg_SPEC,
110 crate::common::RW,
111 >::from_register(self, 0)
112 }
113}
114impl ::core::default::Default for ClkRefCntReg {
115 #[inline(always)]
116 fn default() -> ClkRefCntReg {
117 <crate::RegValueT<ClkRefCntReg_SPEC> as RegisterValue<_>>::new(0)
118 }
119}
120
121#[doc(hidden)]
122#[derive(Copy, Clone, Eq, PartialEq)]
123pub struct ClkRefSelReg_SPEC;
124impl crate::sealed::RegSpec for ClkRefSelReg_SPEC {
125 type DataType = u16;
126}
127
128#[doc = "Select clock for oscillator calibration"]
129pub type ClkRefSelReg = crate::RegValueT<ClkRefSelReg_SPEC>;
130
131impl ClkRefSelReg {
132 #[doc = "0 : Enable XTAL_CNT counter by the REF_CLK selected by REF_CLK_SEL.\n1 : Enable XTAL_CNT counter from an external input."]
133 #[inline(always)]
134 pub fn ext_cnt_en_sel(
135 self,
136 ) -> crate::common::RegisterFieldBool<3, 1, 0, ClkRefSelReg_SPEC, crate::common::RW> {
137 crate::common::RegisterFieldBool::<3,1,0,ClkRefSelReg_SPEC,crate::common::RW>::from_register(self,0)
138 }
139
140 #[doc = "Writing a \'1\' starts a calibration of the clock selected by CLK_REF_SEL_REG\\[REF_CLK_SEL\\]. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready."]
141 #[inline(always)]
142 pub fn ref_cal_start(
143 self,
144 ) -> crate::common::RegisterFieldBool<2, 1, 0, ClkRefSelReg_SPEC, crate::common::RW> {
145 crate::common::RegisterFieldBool::<2,1,0,ClkRefSelReg_SPEC,crate::common::RW>::from_register(self,0)
146 }
147
148 #[doc = "Select clock input for calibration:\n0x0 : RC32K\n0x1 : RC32M\n0x2 : XTAL32K\n0x3 : RCX"]
149 #[inline(always)]
150 pub fn ref_clk_sel(
151 self,
152 ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, ClkRefSelReg_SPEC, crate::common::RW>
153 {
154 crate::common::RegisterField::<0,0x3,1,0,u8,u8,ClkRefSelReg_SPEC,crate::common::RW>::from_register(self,0)
155 }
156}
157impl ::core::default::Default for ClkRefSelReg {
158 #[inline(always)]
159 fn default() -> ClkRefSelReg {
160 <crate::RegValueT<ClkRefSelReg_SPEC> as RegisterValue<_>>::new(0)
161 }
162}
163
164#[doc(hidden)]
165#[derive(Copy, Clone, Eq, PartialEq)]
166pub struct ClkRefValHReg_SPEC;
167impl crate::sealed::RegSpec for ClkRefValHReg_SPEC {
168 type DataType = u16;
169}
170
171#[doc = "XTAL32M reference cycles, higher 16 bits"]
172pub type ClkRefValHReg = crate::RegValueT<ClkRefValHReg_SPEC>;
173
174impl ClkRefValHReg {
175 #[doc = "Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL"]
176 #[inline(always)]
177 pub fn xtal_cnt_val(
178 self,
179 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, ClkRefValHReg_SPEC, crate::common::R>
180 {
181 crate::common::RegisterField::<
182 0,
183 0xffff,
184 1,
185 0,
186 u16,
187 u16,
188 ClkRefValHReg_SPEC,
189 crate::common::R,
190 >::from_register(self, 0)
191 }
192}
193impl ::core::default::Default for ClkRefValHReg {
194 #[inline(always)]
195 fn default() -> ClkRefValHReg {
196 <crate::RegValueT<ClkRefValHReg_SPEC> as RegisterValue<_>>::new(0)
197 }
198}
199
200#[doc(hidden)]
201#[derive(Copy, Clone, Eq, PartialEq)]
202pub struct ClkRefValLReg_SPEC;
203impl crate::sealed::RegSpec for ClkRefValLReg_SPEC {
204 type DataType = u16;
205}
206
207#[doc = "XTAL32M reference cycles, lower 16 bits"]
208pub type ClkRefValLReg = crate::RegValueT<ClkRefValLReg_SPEC>;
209
210impl ClkRefValLReg {
211 #[doc = "Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL"]
212 #[inline(always)]
213 pub fn xtal_cnt_val(
214 self,
215 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, ClkRefValLReg_SPEC, crate::common::R>
216 {
217 crate::common::RegisterField::<
218 0,
219 0xffff,
220 1,
221 0,
222 u16,
223 u16,
224 ClkRefValLReg_SPEC,
225 crate::common::R,
226 >::from_register(self, 0)
227 }
228}
229impl ::core::default::Default for ClkRefValLReg {
230 #[inline(always)]
231 fn default() -> ClkRefValLReg {
232 <crate::RegValueT<ClkRefValLReg_SPEC> as RegisterValue<_>>::new(0)
233 }
234}