da14531_pac/
crg_tim.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:44:12 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"CRG_TIM registers"]
28unsafe impl ::core::marker::Send for super::CrgTim {}
29unsafe impl ::core::marker::Sync for super::CrgTim {}
30impl super::CrgTim {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Divisor for RTC 100Hz clock"]
38    #[inline(always)]
39    pub const fn clk_rtcdiv_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::ClkRtcdivReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::ClkRtcdivReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(76usize),
45            )
46        }
47    }
48}
49#[doc(hidden)]
50#[derive(Copy, Clone, Eq, PartialEq)]
51pub struct ClkRtcdivReg_SPEC;
52impl crate::sealed::RegSpec for ClkRtcdivReg_SPEC {
53    type DataType = u32;
54}
55
56#[doc = "Divisor for RTC 100Hz clock"]
57pub type ClkRtcdivReg = crate::RegValueT<ClkRtcdivReg_SPEC>;
58
59impl ClkRtcdivReg {
60    #[doc = "Reset request for the RTC module"]
61    #[inline(always)]
62    pub fn rtc_reset_req(
63        self,
64    ) -> crate::common::RegisterFieldBool<21, 1, 0, ClkRtcdivReg_SPEC, crate::common::RW> {
65        crate::common::RegisterFieldBool::<21,1,0,ClkRtcdivReg_SPEC,crate::common::RW>::from_register(self,0)
66    }
67
68    #[doc = "Enable for the 100 Hz generation for the RTC block"]
69    #[inline(always)]
70    pub fn rtc_div_enable(
71        self,
72    ) -> crate::common::RegisterFieldBool<20, 1, 0, ClkRtcdivReg_SPEC, crate::common::RW> {
73        crate::common::RegisterFieldBool::<20,1,0,ClkRtcdivReg_SPEC,crate::common::RW>::from_register(self,0)
74    }
75
76    #[doc = "Selects the denominator for the fractional division:\n0b0: 1000\n0b1: 1024"]
77    #[inline(always)]
78    pub fn rtc_div_denom(
79        self,
80    ) -> crate::common::RegisterFieldBool<19, 1, 0, ClkRtcdivReg_SPEC, crate::common::RW> {
81        crate::common::RegisterFieldBool::<19,1,0,ClkRtcdivReg_SPEC,crate::common::RW>::from_register(self,0)
82    }
83
84    #[doc = "Integer divisor part for RTC 100Hz generation"]
85    #[inline(always)]
86    pub fn rtc_div_int(
87        self,
88    ) -> crate::common::RegisterField<10, 0x1ff, 1, 0, u16, u16, ClkRtcdivReg_SPEC, crate::common::RW>
89    {
90        crate::common::RegisterField::<
91            10,
92            0x1ff,
93            1,
94            0,
95            u16,
96            u16,
97            ClkRtcdivReg_SPEC,
98            crate::common::RW,
99        >::from_register(self, 0)
100    }
101
102    #[doc = "Fractional divisor part for RTC 100Hz generation.\nif RTC_DIV_DENOM=1, <RTC_DIV_FRAC> out of 1024 cycles will divide by <RTC_DIV_INT+1>, the rest is <RTC_DIV_INT>\nIf RTC_DIV_DENOM=0, <RTC_DIV_FRAC> out of 1000 cycles will divide by <RTC_DIV_INT+1>, the rest is <RTC_DIV_INT>"]
103    #[inline(always)]
104    pub fn rtc_div_frac(
105        self,
106    ) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, ClkRtcdivReg_SPEC, crate::common::RW>
107    {
108        crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,ClkRtcdivReg_SPEC,crate::common::RW>::from_register(self,0)
109    }
110}
111impl ::core::default::Default for ClkRtcdivReg {
112    #[inline(always)]
113    fn default() -> ClkRtcdivReg {
114        <crate::RegValueT<ClkRtcdivReg_SPEC> as RegisterValue<_>>::new(335528)
115    }
116}
da14531_pac/crg_tim.rs

da14531_pac/
crg_tim.rs
