d1_pac/tve/
tve_configuration.rs

1#[doc = "Register `tve_configuration` reader"]
2pub type R = crate::R<TVE_CONFIGURATION_SPEC>;
3#[doc = "Register `tve_configuration` writer"]
4pub type W = crate::W<TVE_CONFIGURATION_SPEC>;
5#[doc = "Field `tvmode_select` reader - TVMode_Select\n\nNote: Changing this register value will cause some relative register setting to relative value."]
6pub type TVMODE_SELECT_R = crate::FieldReader<TVMODE_SELECT_A>;
7#[doc = "TVMode_Select\n\nNote: Changing this register value will cause some relative register setting to relative value.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum TVMODE_SELECT_A {
11    #[doc = "0: NTSC"]
12    NTSC = 0,
13    #[doc = "1: PAL"]
14    PAL = 1,
15}
16impl From<TVMODE_SELECT_A> for u8 {
17    #[inline(always)]
18    fn from(variant: TVMODE_SELECT_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for TVMODE_SELECT_A {
23    type Ux = u8;
24}
25impl TVMODE_SELECT_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<TVMODE_SELECT_A> {
29        match self.bits {
30            0 => Some(TVMODE_SELECT_A::NTSC),
31            1 => Some(TVMODE_SELECT_A::PAL),
32            _ => None,
33        }
34    }
35    #[doc = "NTSC"]
36    #[inline(always)]
37    pub fn is_ntsc(&self) -> bool {
38        *self == TVMODE_SELECT_A::NTSC
39    }
40    #[doc = "PAL"]
41    #[inline(always)]
42    pub fn is_pal(&self) -> bool {
43        *self == TVMODE_SELECT_A::PAL
44    }
45}
46#[doc = "Field `tvmode_select` writer - TVMode_Select\n\nNote: Changing this register value will cause some relative register setting to relative value."]
47pub type TVMODE_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, TVMODE_SELECT_A>;
48impl<'a, REG> TVMODE_SELECT_W<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51    REG::Ux: From<u8>,
52{
53    #[doc = "NTSC"]
54    #[inline(always)]
55    pub fn ntsc(self) -> &'a mut crate::W<REG> {
56        self.variant(TVMODE_SELECT_A::NTSC)
57    }
58    #[doc = "PAL"]
59    #[inline(always)]
60    pub fn pal(self) -> &'a mut crate::W<REG> {
61        self.variant(TVMODE_SELECT_A::PAL)
62    }
63}
64#[doc = "Field `mode_1080i_1250line_sel` reader - Mode_1080i_1250Line_Sel"]
65pub type MODE_1080I_1250LINE_SEL_R = crate::BitReader<MODE_1080I_1250LINE_SEL_A>;
66#[doc = "Mode_1080i_1250Line_Sel\n\nValue on reset: 0"]
67#[derive(Clone, Copy, Debug, PartialEq, Eq)]
68pub enum MODE_1080I_1250LINE_SEL_A {
69    #[doc = "0: 1125 Line mode"]
70    _1125 = 0,
71    #[doc = "1: 1250 Line mode"]
72    _1250 = 1,
73}
74impl From<MODE_1080I_1250LINE_SEL_A> for bool {
75    #[inline(always)]
76    fn from(variant: MODE_1080I_1250LINE_SEL_A) -> Self {
77        variant as u8 != 0
78    }
79}
80impl MODE_1080I_1250LINE_SEL_R {
81    #[doc = "Get enumerated values variant"]
82    #[inline(always)]
83    pub const fn variant(&self) -> MODE_1080I_1250LINE_SEL_A {
84        match self.bits {
85            false => MODE_1080I_1250LINE_SEL_A::_1125,
86            true => MODE_1080I_1250LINE_SEL_A::_1250,
87        }
88    }
89    #[doc = "1125 Line mode"]
90    #[inline(always)]
91    pub fn is_1125(&self) -> bool {
92        *self == MODE_1080I_1250LINE_SEL_A::_1125
93    }
94    #[doc = "1250 Line mode"]
95    #[inline(always)]
96    pub fn is_1250(&self) -> bool {
97        *self == MODE_1080I_1250LINE_SEL_A::_1250
98    }
99}
100#[doc = "Field `mode_1080i_1250line_sel` writer - Mode_1080i_1250Line_Sel"]
101pub type MODE_1080I_1250LINE_SEL_W<'a, REG> = crate::BitWriter<'a, REG, MODE_1080I_1250LINE_SEL_A>;
102impl<'a, REG> MODE_1080I_1250LINE_SEL_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    #[doc = "1125 Line mode"]
107    #[inline(always)]
108    pub fn _1125(self) -> &'a mut crate::W<REG> {
109        self.variant(MODE_1080I_1250LINE_SEL_A::_1125)
110    }
111    #[doc = "1250 Line mode"]
112    #[inline(always)]
113    pub fn _1250(self) -> &'a mut crate::W<REG> {
114        self.variant(MODE_1080I_1250LINE_SEL_A::_1250)
115    }
116}
117#[doc = "Field `color_bar_mode` reader - Standard Color bar input selection\n\nThis bit selects whether the Video Encoder video data input is replaced by an internal standard color bar generator or not."]
118pub type COLOR_BAR_MODE_R = crate::BitReader<COLOR_BAR_MODE_A>;
119#[doc = "Standard Color bar input selection\n\nThis bit selects whether the Video Encoder video data input is replaced by an internal standard color bar generator or not.\n\nValue on reset: 0"]
120#[derive(Clone, Copy, Debug, PartialEq, Eq)]
121pub enum COLOR_BAR_MODE_A {
122    #[doc = "0: The Video Encoder input is coming from the Display Engineer"]
123    D_ISPLAY_E_NGINEER = 0,
124    #[doc = "1: The Video Encoder input is coming from an internal standard color bar generator."]
125    I_NTERNAL_GENERATOR = 1,
126}
127impl From<COLOR_BAR_MODE_A> for bool {
128    #[inline(always)]
129    fn from(variant: COLOR_BAR_MODE_A) -> Self {
130        variant as u8 != 0
131    }
132}
133impl COLOR_BAR_MODE_R {
134    #[doc = "Get enumerated values variant"]
135    #[inline(always)]
136    pub const fn variant(&self) -> COLOR_BAR_MODE_A {
137        match self.bits {
138            false => COLOR_BAR_MODE_A::D_ISPLAY_E_NGINEER,
139            true => COLOR_BAR_MODE_A::I_NTERNAL_GENERATOR,
140        }
141    }
142    #[doc = "The Video Encoder input is coming from the Display Engineer"]
143    #[inline(always)]
144    pub fn is_d_isplay_e_ngineer(&self) -> bool {
145        *self == COLOR_BAR_MODE_A::D_ISPLAY_E_NGINEER
146    }
147    #[doc = "The Video Encoder input is coming from an internal standard color bar generator."]
148    #[inline(always)]
149    pub fn is_i_nternal_generator(&self) -> bool {
150        *self == COLOR_BAR_MODE_A::I_NTERNAL_GENERATOR
151    }
152}
153#[doc = "Field `color_bar_mode` writer - Standard Color bar input selection\n\nThis bit selects whether the Video Encoder video data input is replaced by an internal standard color bar generator or not."]
154pub type COLOR_BAR_MODE_W<'a, REG> = crate::BitWriter<'a, REG, COLOR_BAR_MODE_A>;
155impl<'a, REG> COLOR_BAR_MODE_W<'a, REG>
156where
157    REG: crate::Writable + crate::RegisterSpec,
158{
159    #[doc = "The Video Encoder input is coming from the Display Engineer"]
160    #[inline(always)]
161    pub fn d_isplay_e_ngineer(self) -> &'a mut crate::W<REG> {
162        self.variant(COLOR_BAR_MODE_A::D_ISPLAY_E_NGINEER)
163    }
164    #[doc = "The Video Encoder input is coming from an internal standard color bar generator."]
165    #[inline(always)]
166    pub fn i_nternal_generator(self) -> &'a mut crate::W<REG> {
167        self.variant(COLOR_BAR_MODE_A::I_NTERNAL_GENERATOR)
168    }
169}
170#[doc = "Field `color_bar_type` reader - "]
171pub type COLOR_BAR_TYPE_R = crate::BitReader<COLOR_BAR_TYPE_A>;
172#[doc = "\n\nValue on reset: 0"]
173#[derive(Clone, Copy, Debug, PartialEq, Eq)]
174pub enum COLOR_BAR_TYPE_A {
175    #[doc = "0: 75/7.5/75/7.5 (NTSC), 100/0/75/0(PAL)"]
176    _75 = 0,
177    #[doc = "1: 100/7.5/100/7.5(NTSC), 100/0/100/0(PAL)"]
178    _100 = 1,
179}
180impl From<COLOR_BAR_TYPE_A> for bool {
181    #[inline(always)]
182    fn from(variant: COLOR_BAR_TYPE_A) -> Self {
183        variant as u8 != 0
184    }
185}
186impl COLOR_BAR_TYPE_R {
187    #[doc = "Get enumerated values variant"]
188    #[inline(always)]
189    pub const fn variant(&self) -> COLOR_BAR_TYPE_A {
190        match self.bits {
191            false => COLOR_BAR_TYPE_A::_75,
192            true => COLOR_BAR_TYPE_A::_100,
193        }
194    }
195    #[doc = "75/7.5/75/7.5 (NTSC), 100/0/75/0(PAL)"]
196    #[inline(always)]
197    pub fn is_75(&self) -> bool {
198        *self == COLOR_BAR_TYPE_A::_75
199    }
200    #[doc = "100/7.5/100/7.5(NTSC), 100/0/100/0(PAL)"]
201    #[inline(always)]
202    pub fn is_100(&self) -> bool {
203        *self == COLOR_BAR_TYPE_A::_100
204    }
205}
206#[doc = "Field `color_bar_type` writer - "]
207pub type COLOR_BAR_TYPE_W<'a, REG> = crate::BitWriter<'a, REG, COLOR_BAR_TYPE_A>;
208impl<'a, REG> COLOR_BAR_TYPE_W<'a, REG>
209where
210    REG: crate::Writable + crate::RegisterSpec,
211{
212    #[doc = "75/7.5/75/7.5 (NTSC), 100/0/75/0(PAL)"]
213    #[inline(always)]
214    pub fn _75(self) -> &'a mut crate::W<REG> {
215        self.variant(COLOR_BAR_TYPE_A::_75)
216    }
217    #[doc = "100/7.5/100/7.5(NTSC), 100/0/100/0(PAL)"]
218    #[inline(always)]
219    pub fn _100(self) -> &'a mut crate::W<REG> {
220        self.variant(COLOR_BAR_TYPE_A::_100)
221    }
222}
223#[doc = "Field `cvbs_en` reader - Composite video enables selection\n\nThis bit selects whether the composite video output (CVBS) is enabled or disabled."]
224pub type CVBS_EN_R = crate::BitReader<CVBS_EN_A>;
225#[doc = "Composite video enables selection\n\nThis bit selects whether the composite video output (CVBS) is enabled or disabled.\n\nValue on reset: 1"]
226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
227pub enum CVBS_EN_A {
228    #[doc = "0: Composite video is disabled, Only Y/C is enabled"]
229    DISABLED = 0,
230    #[doc = "1: Composite video is enabled., CVBS and Y/C are enabled"]
231    ENABLED = 1,
232}
233impl From<CVBS_EN_A> for bool {
234    #[inline(always)]
235    fn from(variant: CVBS_EN_A) -> Self {
236        variant as u8 != 0
237    }
238}
239impl CVBS_EN_R {
240    #[doc = "Get enumerated values variant"]
241    #[inline(always)]
242    pub const fn variant(&self) -> CVBS_EN_A {
243        match self.bits {
244            false => CVBS_EN_A::DISABLED,
245            true => CVBS_EN_A::ENABLED,
246        }
247    }
248    #[doc = "Composite video is disabled, Only Y/C is enabled"]
249    #[inline(always)]
250    pub fn is_disabled(&self) -> bool {
251        *self == CVBS_EN_A::DISABLED
252    }
253    #[doc = "Composite video is enabled., CVBS and Y/C are enabled"]
254    #[inline(always)]
255    pub fn is_enabled(&self) -> bool {
256        *self == CVBS_EN_A::ENABLED
257    }
258}
259#[doc = "Field `cvbs_en` writer - Composite video enables selection\n\nThis bit selects whether the composite video output (CVBS) is enabled or disabled."]
260pub type CVBS_EN_W<'a, REG> = crate::BitWriter<'a, REG, CVBS_EN_A>;
261impl<'a, REG> CVBS_EN_W<'a, REG>
262where
263    REG: crate::Writable + crate::RegisterSpec,
264{
265    #[doc = "Composite video is disabled, Only Y/C is enabled"]
266    #[inline(always)]
267    pub fn disabled(self) -> &'a mut crate::W<REG> {
268        self.variant(CVBS_EN_A::DISABLED)
269    }
270    #[doc = "Composite video is enabled., CVBS and Y/C are enabled"]
271    #[inline(always)]
272    pub fn enabled(self) -> &'a mut crate::W<REG> {
273        self.variant(CVBS_EN_A::ENABLED)
274    }
275}
276#[doc = "Field `yc_en` reader - S-port Video enable Selection.\n\nThis bit selects whether the S-port(Y/C) video output is enabled or disabled."]
277pub type YC_EN_R = crate::BitReader<YC_EN_A>;
278#[doc = "S-port Video enable Selection.\n\nThis bit selects whether the S-port(Y/C) video output is enabled or disabled.\n\nValue on reset: 0"]
279#[derive(Clone, Copy, Debug, PartialEq, Eq)]
280pub enum YC_EN_A {
281    #[doc = "0: Y/C is disable"]
282    Y_C = 0,
283}
284impl From<YC_EN_A> for bool {
285    #[inline(always)]
286    fn from(variant: YC_EN_A) -> Self {
287        variant as u8 != 0
288    }
289}
290impl YC_EN_R {
291    #[doc = "Get enumerated values variant"]
292    #[inline(always)]
293    pub const fn variant(&self) -> Option<YC_EN_A> {
294        match self.bits {
295            false => Some(YC_EN_A::Y_C),
296            _ => None,
297        }
298    }
299    #[doc = "Y/C is disable"]
300    #[inline(always)]
301    pub fn is_y_c(&self) -> bool {
302        *self == YC_EN_A::Y_C
303    }
304}
305#[doc = "Field `yc_en` writer - S-port Video enable Selection.\n\nThis bit selects whether the S-port(Y/C) video output is enabled or disabled."]
306pub type YC_EN_W<'a, REG> = crate::BitWriter<'a, REG, YC_EN_A>;
307impl<'a, REG> YC_EN_W<'a, REG>
308where
309    REG: crate::Writable + crate::RegisterSpec,
310{
311    #[doc = "Y/C is disable"]
312    #[inline(always)]
313    pub fn y_c(self) -> &'a mut crate::W<REG> {
314        self.variant(YC_EN_A::Y_C)
315    }
316}
317#[doc = "Field `yuv_rgb_output_en` reader - "]
318pub type YUV_RGB_OUTPUT_EN_R = crate::BitReader<YUV_RGB_OUTPUT_EN_A>;
319#[doc = "\n\nValue on reset: 0"]
320#[derive(Clone, Copy, Debug, PartialEq, Eq)]
321pub enum YUV_RGB_OUTPUT_EN_A {
322    #[doc = "0: CVBS"]
323    CVBS = 0,
324}
325impl From<YUV_RGB_OUTPUT_EN_A> for bool {
326    #[inline(always)]
327    fn from(variant: YUV_RGB_OUTPUT_EN_A) -> Self {
328        variant as u8 != 0
329    }
330}
331impl YUV_RGB_OUTPUT_EN_R {
332    #[doc = "Get enumerated values variant"]
333    #[inline(always)]
334    pub const fn variant(&self) -> Option<YUV_RGB_OUTPUT_EN_A> {
335        match self.bits {
336            false => Some(YUV_RGB_OUTPUT_EN_A::CVBS),
337            _ => None,
338        }
339    }
340    #[doc = "CVBS"]
341    #[inline(always)]
342    pub fn is_cvbs(&self) -> bool {
343        *self == YUV_RGB_OUTPUT_EN_A::CVBS
344    }
345}
346#[doc = "Field `yuv_rgb_output_en` writer - "]
347pub type YUV_RGB_OUTPUT_EN_W<'a, REG> = crate::BitWriter<'a, REG, YUV_RGB_OUTPUT_EN_A>;
348impl<'a, REG> YUV_RGB_OUTPUT_EN_W<'a, REG>
349where
350    REG: crate::Writable + crate::RegisterSpec,
351{
352    #[doc = "CVBS"]
353    #[inline(always)]
354    pub fn cvbs(self) -> &'a mut crate::W<REG> {
355        self.variant(YUV_RGB_OUTPUT_EN_A::CVBS)
356    }
357}
358#[doc = "Field `input_chroma_data_sampling_rate_sel` reader - "]
359pub type INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_R =
360    crate::BitReader<INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A>;
361#[doc = "\n\nValue on reset: 0"]
362#[derive(Clone, Copy, Debug, PartialEq, Eq)]
363pub enum INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A {
364    #[doc = "0: 4:4:4"]
365    _4_4_4 = 0,
366    #[doc = "1: 4:2:2"]
367    _4_2_2 = 1,
368}
369impl From<INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A> for bool {
370    #[inline(always)]
371    fn from(variant: INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A) -> Self {
372        variant as u8 != 0
373    }
374}
375impl INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_R {
376    #[doc = "Get enumerated values variant"]
377    #[inline(always)]
378    pub const fn variant(&self) -> INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A {
379        match self.bits {
380            false => INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A::_4_4_4,
381            true => INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A::_4_2_2,
382        }
383    }
384    #[doc = "4:4:4"]
385    #[inline(always)]
386    pub fn is_4_4_4(&self) -> bool {
387        *self == INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A::_4_4_4
388    }
389    #[doc = "4:2:2"]
390    #[inline(always)]
391    pub fn is_4_2_2(&self) -> bool {
392        *self == INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A::_4_2_2
393    }
394}
395#[doc = "Field `input_chroma_data_sampling_rate_sel` writer - "]
396pub type INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_W<'a, REG> =
397    crate::BitWriter<'a, REG, INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A>;
398impl<'a, REG> INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_W<'a, REG>
399where
400    REG: crate::Writable + crate::RegisterSpec,
401{
402    #[doc = "4:4:4"]
403    #[inline(always)]
404    pub fn _4_4_4(self) -> &'a mut crate::W<REG> {
405        self.variant(INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A::_4_4_4)
406    }
407    #[doc = "4:2:2"]
408    #[inline(always)]
409    pub fn _4_2_2(self) -> &'a mut crate::W<REG> {
410        self.variant(INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_A::_4_2_2)
411    }
412}
413#[doc = "Field `cb_cr_seq_for_422_mode` reader - Cb_Cr_Seq_For_422_Mode"]
414pub type CB_CR_SEQ_FOR_422_MODE_R = crate::BitReader<CB_CR_SEQ_FOR_422_MODE_A>;
415#[doc = "Cb_Cr_Seq_For_422_Mode\n\nValue on reset: 0"]
416#[derive(Clone, Copy, Debug, PartialEq, Eq)]
417pub enum CB_CR_SEQ_FOR_422_MODE_A {
418    #[doc = "0: Cb first"]
419    C_B = 0,
420    #[doc = "1: Cr first"]
421    C_R = 1,
422}
423impl From<CB_CR_SEQ_FOR_422_MODE_A> for bool {
424    #[inline(always)]
425    fn from(variant: CB_CR_SEQ_FOR_422_MODE_A) -> Self {
426        variant as u8 != 0
427    }
428}
429impl CB_CR_SEQ_FOR_422_MODE_R {
430    #[doc = "Get enumerated values variant"]
431    #[inline(always)]
432    pub const fn variant(&self) -> CB_CR_SEQ_FOR_422_MODE_A {
433        match self.bits {
434            false => CB_CR_SEQ_FOR_422_MODE_A::C_B,
435            true => CB_CR_SEQ_FOR_422_MODE_A::C_R,
436        }
437    }
438    #[doc = "Cb first"]
439    #[inline(always)]
440    pub fn is_c_b(&self) -> bool {
441        *self == CB_CR_SEQ_FOR_422_MODE_A::C_B
442    }
443    #[doc = "Cr first"]
444    #[inline(always)]
445    pub fn is_c_r(&self) -> bool {
446        *self == CB_CR_SEQ_FOR_422_MODE_A::C_R
447    }
448}
449#[doc = "Field `cb_cr_seq_for_422_mode` writer - Cb_Cr_Seq_For_422_Mode"]
450pub type CB_CR_SEQ_FOR_422_MODE_W<'a, REG> = crate::BitWriter<'a, REG, CB_CR_SEQ_FOR_422_MODE_A>;
451impl<'a, REG> CB_CR_SEQ_FOR_422_MODE_W<'a, REG>
452where
453    REG: crate::Writable + crate::RegisterSpec,
454{
455    #[doc = "Cb first"]
456    #[inline(always)]
457    pub fn c_b(self) -> &'a mut crate::W<REG> {
458        self.variant(CB_CR_SEQ_FOR_422_MODE_A::C_B)
459    }
460    #[doc = "Cr first"]
461    #[inline(always)]
462    pub fn c_r(self) -> &'a mut crate::W<REG> {
463        self.variant(CB_CR_SEQ_FOR_422_MODE_A::C_R)
464    }
465}
466#[doc = "Field `core_control_logic_clock_sel` reader - "]
467pub type CORE_CONTROL_LOGIC_CLOCK_SEL_R = crate::BitReader<CORE_CONTROL_LOGIC_CLOCK_SEL_A>;
468#[doc = "\n\nValue on reset: 0"]
469#[derive(Clone, Copy, Debug, PartialEq, Eq)]
470pub enum CORE_CONTROL_LOGIC_CLOCK_SEL_A {
471    #[doc = "0: Using 27 MHz clock or 74.25 MHz clock depend on CCU setting"]
472    _27M_74_25M = 0,
473    #[doc = "1: Using 54 MHz clock or 148.5 MHz clock depend on CCU setting"]
474    _54M_148_5M = 1,
475}
476impl From<CORE_CONTROL_LOGIC_CLOCK_SEL_A> for bool {
477    #[inline(always)]
478    fn from(variant: CORE_CONTROL_LOGIC_CLOCK_SEL_A) -> Self {
479        variant as u8 != 0
480    }
481}
482impl CORE_CONTROL_LOGIC_CLOCK_SEL_R {
483    #[doc = "Get enumerated values variant"]
484    #[inline(always)]
485    pub const fn variant(&self) -> CORE_CONTROL_LOGIC_CLOCK_SEL_A {
486        match self.bits {
487            false => CORE_CONTROL_LOGIC_CLOCK_SEL_A::_27M_74_25M,
488            true => CORE_CONTROL_LOGIC_CLOCK_SEL_A::_54M_148_5M,
489        }
490    }
491    #[doc = "Using 27 MHz clock or 74.25 MHz clock depend on CCU setting"]
492    #[inline(always)]
493    pub fn is_27m_74_25m(&self) -> bool {
494        *self == CORE_CONTROL_LOGIC_CLOCK_SEL_A::_27M_74_25M
495    }
496    #[doc = "Using 54 MHz clock or 148.5 MHz clock depend on CCU setting"]
497    #[inline(always)]
498    pub fn is_54m_148_5m(&self) -> bool {
499        *self == CORE_CONTROL_LOGIC_CLOCK_SEL_A::_54M_148_5M
500    }
501}
502#[doc = "Field `core_control_logic_clock_sel` writer - "]
503pub type CORE_CONTROL_LOGIC_CLOCK_SEL_W<'a, REG> =
504    crate::BitWriter<'a, REG, CORE_CONTROL_LOGIC_CLOCK_SEL_A>;
505impl<'a, REG> CORE_CONTROL_LOGIC_CLOCK_SEL_W<'a, REG>
506where
507    REG: crate::Writable + crate::RegisterSpec,
508{
509    #[doc = "Using 27 MHz clock or 74.25 MHz clock depend on CCU setting"]
510    #[inline(always)]
511    pub fn _27m_74_25m(self) -> &'a mut crate::W<REG> {
512        self.variant(CORE_CONTROL_LOGIC_CLOCK_SEL_A::_27M_74_25M)
513    }
514    #[doc = "Using 54 MHz clock or 148.5 MHz clock depend on CCU setting"]
515    #[inline(always)]
516    pub fn _54m_148_5m(self) -> &'a mut crate::W<REG> {
517        self.variant(CORE_CONTROL_LOGIC_CLOCK_SEL_A::_54M_148_5M)
518    }
519}
520#[doc = "Field `core_datapath_logic_clock_sel` reader - "]
521pub type CORE_DATAPATH_LOGIC_CLOCK_SEL_R = crate::BitReader<CORE_DATAPATH_LOGIC_CLOCK_SEL_A>;
522#[doc = "\n\nValue on reset: 0"]
523#[derive(Clone, Copy, Debug, PartialEq, Eq)]
524pub enum CORE_DATAPATH_LOGIC_CLOCK_SEL_A {
525    #[doc = "0: Using 27 MHz clock or 74.25 MHz clock depend on CCU setting"]
526    _27M_74_25M = 0,
527    #[doc = "1: Using 54 MHz clock or 148.5 MHz clock depend on CCU setting"]
528    _54M_148_5M = 1,
529}
530impl From<CORE_DATAPATH_LOGIC_CLOCK_SEL_A> for bool {
531    #[inline(always)]
532    fn from(variant: CORE_DATAPATH_LOGIC_CLOCK_SEL_A) -> Self {
533        variant as u8 != 0
534    }
535}
536impl CORE_DATAPATH_LOGIC_CLOCK_SEL_R {
537    #[doc = "Get enumerated values variant"]
538    #[inline(always)]
539    pub const fn variant(&self) -> CORE_DATAPATH_LOGIC_CLOCK_SEL_A {
540        match self.bits {
541            false => CORE_DATAPATH_LOGIC_CLOCK_SEL_A::_27M_74_25M,
542            true => CORE_DATAPATH_LOGIC_CLOCK_SEL_A::_54M_148_5M,
543        }
544    }
545    #[doc = "Using 27 MHz clock or 74.25 MHz clock depend on CCU setting"]
546    #[inline(always)]
547    pub fn is_27m_74_25m(&self) -> bool {
548        *self == CORE_DATAPATH_LOGIC_CLOCK_SEL_A::_27M_74_25M
549    }
550    #[doc = "Using 54 MHz clock or 148.5 MHz clock depend on CCU setting"]
551    #[inline(always)]
552    pub fn is_54m_148_5m(&self) -> bool {
553        *self == CORE_DATAPATH_LOGIC_CLOCK_SEL_A::_54M_148_5M
554    }
555}
556#[doc = "Field `core_datapath_logic_clock_sel` writer - "]
557pub type CORE_DATAPATH_LOGIC_CLOCK_SEL_W<'a, REG> =
558    crate::BitWriter<'a, REG, CORE_DATAPATH_LOGIC_CLOCK_SEL_A>;
559impl<'a, REG> CORE_DATAPATH_LOGIC_CLOCK_SEL_W<'a, REG>
560where
561    REG: crate::Writable + crate::RegisterSpec,
562{
563    #[doc = "Using 27 MHz clock or 74.25 MHz clock depend on CCU setting"]
564    #[inline(always)]
565    pub fn _27m_74_25m(self) -> &'a mut crate::W<REG> {
566        self.variant(CORE_DATAPATH_LOGIC_CLOCK_SEL_A::_27M_74_25M)
567    }
568    #[doc = "Using 54 MHz clock or 148.5 MHz clock depend on CCU setting"]
569    #[inline(always)]
570    pub fn _54m_148_5m(self) -> &'a mut crate::W<REG> {
571        self.variant(CORE_DATAPATH_LOGIC_CLOCK_SEL_A::_54M_148_5M)
572    }
573}
574#[doc = "Field `dac_control_logic_clock_sel` reader - "]
575pub type DAC_CONTROL_LOGIC_CLOCK_SEL_R = crate::BitReader<DAC_CONTROL_LOGIC_CLOCK_SEL_A>;
576#[doc = "\n\nValue on reset: 0"]
577#[derive(Clone, Copy, Debug, PartialEq, Eq)]
578pub enum DAC_CONTROL_LOGIC_CLOCK_SEL_A {
579    #[doc = "0: Using 27 MHz clock or 74.25 MHz clock depend on CCU setting"]
580    _27M_74_25M = 0,
581    #[doc = "1: Using 54 MHz clock or 148.5 MHz clock depend on CCU setting"]
582    _54M_148_5M = 1,
583}
584impl From<DAC_CONTROL_LOGIC_CLOCK_SEL_A> for bool {
585    #[inline(always)]
586    fn from(variant: DAC_CONTROL_LOGIC_CLOCK_SEL_A) -> Self {
587        variant as u8 != 0
588    }
589}
590impl DAC_CONTROL_LOGIC_CLOCK_SEL_R {
591    #[doc = "Get enumerated values variant"]
592    #[inline(always)]
593    pub const fn variant(&self) -> DAC_CONTROL_LOGIC_CLOCK_SEL_A {
594        match self.bits {
595            false => DAC_CONTROL_LOGIC_CLOCK_SEL_A::_27M_74_25M,
596            true => DAC_CONTROL_LOGIC_CLOCK_SEL_A::_54M_148_5M,
597        }
598    }
599    #[doc = "Using 27 MHz clock or 74.25 MHz clock depend on CCU setting"]
600    #[inline(always)]
601    pub fn is_27m_74_25m(&self) -> bool {
602        *self == DAC_CONTROL_LOGIC_CLOCK_SEL_A::_27M_74_25M
603    }
604    #[doc = "Using 54 MHz clock or 148.5 MHz clock depend on CCU setting"]
605    #[inline(always)]
606    pub fn is_54m_148_5m(&self) -> bool {
607        *self == DAC_CONTROL_LOGIC_CLOCK_SEL_A::_54M_148_5M
608    }
609}
610#[doc = "Field `dac_control_logic_clock_sel` writer - "]
611pub type DAC_CONTROL_LOGIC_CLOCK_SEL_W<'a, REG> =
612    crate::BitWriter<'a, REG, DAC_CONTROL_LOGIC_CLOCK_SEL_A>;
613impl<'a, REG> DAC_CONTROL_LOGIC_CLOCK_SEL_W<'a, REG>
614where
615    REG: crate::Writable + crate::RegisterSpec,
616{
617    #[doc = "Using 27 MHz clock or 74.25 MHz clock depend on CCU setting"]
618    #[inline(always)]
619    pub fn _27m_74_25m(self) -> &'a mut crate::W<REG> {
620        self.variant(DAC_CONTROL_LOGIC_CLOCK_SEL_A::_27M_74_25M)
621    }
622    #[doc = "Using 54 MHz clock or 148.5 MHz clock depend on CCU setting"]
623    #[inline(always)]
624    pub fn _54m_148_5m(self) -> &'a mut crate::W<REG> {
625        self.variant(DAC_CONTROL_LOGIC_CLOCK_SEL_A::_54M_148_5M)
626    }
627}
628#[doc = "Field `dac_src_sel` reader - "]
629pub type DAC_SRC_SEL_R = crate::FieldReader<DAC_SRC_SEL_A>;
630#[doc = "\n\nValue on reset: 0"]
631#[derive(Clone, Copy, Debug, PartialEq, Eq)]
632#[repr(u8)]
633pub enum DAC_SRC_SEL_A {
634    #[doc = "0: TV Encoder"]
635    TVE = 0,
636    #[doc = "1: LCD controller, override all other TV encoder setting, the DAC clock can from LCD controller."]
637    LCD_CONTROLLER = 1,
638    #[doc = "2: DAC test mode, DAC using DAC clock"]
639    DAC_TEST = 2,
640    #[doc = "3: DAC test mode, DAC using AHB clock"]
641    DAC_TEST_AHB = 3,
642}
643impl From<DAC_SRC_SEL_A> for u8 {
644    #[inline(always)]
645    fn from(variant: DAC_SRC_SEL_A) -> Self {
646        variant as _
647    }
648}
649impl crate::FieldSpec for DAC_SRC_SEL_A {
650    type Ux = u8;
651}
652impl DAC_SRC_SEL_R {
653    #[doc = "Get enumerated values variant"]
654    #[inline(always)]
655    pub const fn variant(&self) -> DAC_SRC_SEL_A {
656        match self.bits {
657            0 => DAC_SRC_SEL_A::TVE,
658            1 => DAC_SRC_SEL_A::LCD_CONTROLLER,
659            2 => DAC_SRC_SEL_A::DAC_TEST,
660            3 => DAC_SRC_SEL_A::DAC_TEST_AHB,
661            _ => unreachable!(),
662        }
663    }
664    #[doc = "TV Encoder"]
665    #[inline(always)]
666    pub fn is_tve(&self) -> bool {
667        *self == DAC_SRC_SEL_A::TVE
668    }
669    #[doc = "LCD controller, override all other TV encoder setting, the DAC clock can from LCD controller."]
670    #[inline(always)]
671    pub fn is_lcd_controller(&self) -> bool {
672        *self == DAC_SRC_SEL_A::LCD_CONTROLLER
673    }
674    #[doc = "DAC test mode, DAC using DAC clock"]
675    #[inline(always)]
676    pub fn is_dac_test(&self) -> bool {
677        *self == DAC_SRC_SEL_A::DAC_TEST
678    }
679    #[doc = "DAC test mode, DAC using AHB clock"]
680    #[inline(always)]
681    pub fn is_dac_test_ahb(&self) -> bool {
682        *self == DAC_SRC_SEL_A::DAC_TEST_AHB
683    }
684}
685#[doc = "Field `dac_src_sel` writer - "]
686pub type DAC_SRC_SEL_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DAC_SRC_SEL_A>;
687impl<'a, REG> DAC_SRC_SEL_W<'a, REG>
688where
689    REG: crate::Writable + crate::RegisterSpec,
690    REG::Ux: From<u8>,
691{
692    #[doc = "TV Encoder"]
693    #[inline(always)]
694    pub fn tve(self) -> &'a mut crate::W<REG> {
695        self.variant(DAC_SRC_SEL_A::TVE)
696    }
697    #[doc = "LCD controller, override all other TV encoder setting, the DAC clock can from LCD controller."]
698    #[inline(always)]
699    pub fn lcd_controller(self) -> &'a mut crate::W<REG> {
700        self.variant(DAC_SRC_SEL_A::LCD_CONTROLLER)
701    }
702    #[doc = "DAC test mode, DAC using DAC clock"]
703    #[inline(always)]
704    pub fn dac_test(self) -> &'a mut crate::W<REG> {
705        self.variant(DAC_SRC_SEL_A::DAC_TEST)
706    }
707    #[doc = "DAC test mode, DAC using AHB clock"]
708    #[inline(always)]
709    pub fn dac_test_ahb(self) -> &'a mut crate::W<REG> {
710        self.variant(DAC_SRC_SEL_A::DAC_TEST_AHB)
711    }
712}
713#[doc = "Field `bypass_tv` reader - "]
714pub type BYPASS_TV_R = crate::BitReader<BYPASS_TV_A>;
715#[doc = "\n\nValue on reset: 0"]
716#[derive(Clone, Copy, Debug, PartialEq, Eq)]
717pub enum BYPASS_TV_A {
718    #[doc = "0: Disable"]
719    DISABLE = 0,
720    #[doc = "1: Enable"]
721    ENABLE = 1,
722}
723impl From<BYPASS_TV_A> for bool {
724    #[inline(always)]
725    fn from(variant: BYPASS_TV_A) -> Self {
726        variant as u8 != 0
727    }
728}
729impl BYPASS_TV_R {
730    #[doc = "Get enumerated values variant"]
731    #[inline(always)]
732    pub const fn variant(&self) -> BYPASS_TV_A {
733        match self.bits {
734            false => BYPASS_TV_A::DISABLE,
735            true => BYPASS_TV_A::ENABLE,
736        }
737    }
738    #[doc = "Disable"]
739    #[inline(always)]
740    pub fn is_disable(&self) -> bool {
741        *self == BYPASS_TV_A::DISABLE
742    }
743    #[doc = "Enable"]
744    #[inline(always)]
745    pub fn is_enable(&self) -> bool {
746        *self == BYPASS_TV_A::ENABLE
747    }
748}
749#[doc = "Field `bypass_tv` writer - "]
750pub type BYPASS_TV_W<'a, REG> = crate::BitWriter<'a, REG, BYPASS_TV_A>;
751impl<'a, REG> BYPASS_TV_W<'a, REG>
752where
753    REG: crate::Writable + crate::RegisterSpec,
754{
755    #[doc = "Disable"]
756    #[inline(always)]
757    pub fn disable(self) -> &'a mut crate::W<REG> {
758        self.variant(BYPASS_TV_A::DISABLE)
759    }
760    #[doc = "Enable"]
761    #[inline(always)]
762    pub fn enable(self) -> &'a mut crate::W<REG> {
763        self.variant(BYPASS_TV_A::ENABLE)
764    }
765}
766impl R {
767    #[doc = "Bits 0:3 - TVMode_Select\n\nNote: Changing this register value will cause some relative register setting to relative value."]
768    #[inline(always)]
769    pub fn tvmode_select(&self) -> TVMODE_SELECT_R {
770        TVMODE_SELECT_R::new((self.bits & 0x0f) as u8)
771    }
772    #[doc = "Bit 4 - Mode_1080i_1250Line_Sel"]
773    #[inline(always)]
774    pub fn mode_1080i_1250line_sel(&self) -> MODE_1080I_1250LINE_SEL_R {
775        MODE_1080I_1250LINE_SEL_R::new(((self.bits >> 4) & 1) != 0)
776    }
777    #[doc = "Bit 8 - Standard Color bar input selection\n\nThis bit selects whether the Video Encoder video data input is replaced by an internal standard color bar generator or not."]
778    #[inline(always)]
779    pub fn color_bar_mode(&self) -> COLOR_BAR_MODE_R {
780        COLOR_BAR_MODE_R::new(((self.bits >> 8) & 1) != 0)
781    }
782    #[doc = "Bit 9"]
783    #[inline(always)]
784    pub fn color_bar_type(&self) -> COLOR_BAR_TYPE_R {
785        COLOR_BAR_TYPE_R::new(((self.bits >> 9) & 1) != 0)
786    }
787    #[doc = "Bit 16 - Composite video enables selection\n\nThis bit selects whether the composite video output (CVBS) is enabled or disabled."]
788    #[inline(always)]
789    pub fn cvbs_en(&self) -> CVBS_EN_R {
790        CVBS_EN_R::new(((self.bits >> 16) & 1) != 0)
791    }
792    #[doc = "Bit 17 - S-port Video enable Selection.\n\nThis bit selects whether the S-port(Y/C) video output is enabled or disabled."]
793    #[inline(always)]
794    pub fn yc_en(&self) -> YC_EN_R {
795        YC_EN_R::new(((self.bits >> 17) & 1) != 0)
796    }
797    #[doc = "Bit 18"]
798    #[inline(always)]
799    pub fn yuv_rgb_output_en(&self) -> YUV_RGB_OUTPUT_EN_R {
800        YUV_RGB_OUTPUT_EN_R::new(((self.bits >> 18) & 1) != 0)
801    }
802    #[doc = "Bit 19"]
803    #[inline(always)]
804    pub fn input_chroma_data_sampling_rate_sel(&self) -> INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_R {
805        INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_R::new(((self.bits >> 19) & 1) != 0)
806    }
807    #[doc = "Bit 20 - Cb_Cr_Seq_For_422_Mode"]
808    #[inline(always)]
809    pub fn cb_cr_seq_for_422_mode(&self) -> CB_CR_SEQ_FOR_422_MODE_R {
810        CB_CR_SEQ_FOR_422_MODE_R::new(((self.bits >> 20) & 1) != 0)
811    }
812    #[doc = "Bit 24"]
813    #[inline(always)]
814    pub fn core_control_logic_clock_sel(&self) -> CORE_CONTROL_LOGIC_CLOCK_SEL_R {
815        CORE_CONTROL_LOGIC_CLOCK_SEL_R::new(((self.bits >> 24) & 1) != 0)
816    }
817    #[doc = "Bit 25"]
818    #[inline(always)]
819    pub fn core_datapath_logic_clock_sel(&self) -> CORE_DATAPATH_LOGIC_CLOCK_SEL_R {
820        CORE_DATAPATH_LOGIC_CLOCK_SEL_R::new(((self.bits >> 25) & 1) != 0)
821    }
822    #[doc = "Bit 26"]
823    #[inline(always)]
824    pub fn dac_control_logic_clock_sel(&self) -> DAC_CONTROL_LOGIC_CLOCK_SEL_R {
825        DAC_CONTROL_LOGIC_CLOCK_SEL_R::new(((self.bits >> 26) & 1) != 0)
826    }
827    #[doc = "Bits 27:28"]
828    #[inline(always)]
829    pub fn dac_src_sel(&self) -> DAC_SRC_SEL_R {
830        DAC_SRC_SEL_R::new(((self.bits >> 27) & 3) as u8)
831    }
832    #[doc = "Bit 29"]
833    #[inline(always)]
834    pub fn bypass_tv(&self) -> BYPASS_TV_R {
835        BYPASS_TV_R::new(((self.bits >> 29) & 1) != 0)
836    }
837}
838impl W {
839    #[doc = "Bits 0:3 - TVMode_Select\n\nNote: Changing this register value will cause some relative register setting to relative value."]
840    #[inline(always)]
841    #[must_use]
842    pub fn tvmode_select(&mut self) -> TVMODE_SELECT_W<TVE_CONFIGURATION_SPEC> {
843        TVMODE_SELECT_W::new(self, 0)
844    }
845    #[doc = "Bit 4 - Mode_1080i_1250Line_Sel"]
846    #[inline(always)]
847    #[must_use]
848    pub fn mode_1080i_1250line_sel(&mut self) -> MODE_1080I_1250LINE_SEL_W<TVE_CONFIGURATION_SPEC> {
849        MODE_1080I_1250LINE_SEL_W::new(self, 4)
850    }
851    #[doc = "Bit 8 - Standard Color bar input selection\n\nThis bit selects whether the Video Encoder video data input is replaced by an internal standard color bar generator or not."]
852    #[inline(always)]
853    #[must_use]
854    pub fn color_bar_mode(&mut self) -> COLOR_BAR_MODE_W<TVE_CONFIGURATION_SPEC> {
855        COLOR_BAR_MODE_W::new(self, 8)
856    }
857    #[doc = "Bit 9"]
858    #[inline(always)]
859    #[must_use]
860    pub fn color_bar_type(&mut self) -> COLOR_BAR_TYPE_W<TVE_CONFIGURATION_SPEC> {
861        COLOR_BAR_TYPE_W::new(self, 9)
862    }
863    #[doc = "Bit 16 - Composite video enables selection\n\nThis bit selects whether the composite video output (CVBS) is enabled or disabled."]
864    #[inline(always)]
865    #[must_use]
866    pub fn cvbs_en(&mut self) -> CVBS_EN_W<TVE_CONFIGURATION_SPEC> {
867        CVBS_EN_W::new(self, 16)
868    }
869    #[doc = "Bit 17 - S-port Video enable Selection.\n\nThis bit selects whether the S-port(Y/C) video output is enabled or disabled."]
870    #[inline(always)]
871    #[must_use]
872    pub fn yc_en(&mut self) -> YC_EN_W<TVE_CONFIGURATION_SPEC> {
873        YC_EN_W::new(self, 17)
874    }
875    #[doc = "Bit 18"]
876    #[inline(always)]
877    #[must_use]
878    pub fn yuv_rgb_output_en(&mut self) -> YUV_RGB_OUTPUT_EN_W<TVE_CONFIGURATION_SPEC> {
879        YUV_RGB_OUTPUT_EN_W::new(self, 18)
880    }
881    #[doc = "Bit 19"]
882    #[inline(always)]
883    #[must_use]
884    pub fn input_chroma_data_sampling_rate_sel(
885        &mut self,
886    ) -> INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_W<TVE_CONFIGURATION_SPEC> {
887        INPUT_CHROMA_DATA_SAMPLING_RATE_SEL_W::new(self, 19)
888    }
889    #[doc = "Bit 20 - Cb_Cr_Seq_For_422_Mode"]
890    #[inline(always)]
891    #[must_use]
892    pub fn cb_cr_seq_for_422_mode(&mut self) -> CB_CR_SEQ_FOR_422_MODE_W<TVE_CONFIGURATION_SPEC> {
893        CB_CR_SEQ_FOR_422_MODE_W::new(self, 20)
894    }
895    #[doc = "Bit 24"]
896    #[inline(always)]
897    #[must_use]
898    pub fn core_control_logic_clock_sel(
899        &mut self,
900    ) -> CORE_CONTROL_LOGIC_CLOCK_SEL_W<TVE_CONFIGURATION_SPEC> {
901        CORE_CONTROL_LOGIC_CLOCK_SEL_W::new(self, 24)
902    }
903    #[doc = "Bit 25"]
904    #[inline(always)]
905    #[must_use]
906    pub fn core_datapath_logic_clock_sel(
907        &mut self,
908    ) -> CORE_DATAPATH_LOGIC_CLOCK_SEL_W<TVE_CONFIGURATION_SPEC> {
909        CORE_DATAPATH_LOGIC_CLOCK_SEL_W::new(self, 25)
910    }
911    #[doc = "Bit 26"]
912    #[inline(always)]
913    #[must_use]
914    pub fn dac_control_logic_clock_sel(
915        &mut self,
916    ) -> DAC_CONTROL_LOGIC_CLOCK_SEL_W<TVE_CONFIGURATION_SPEC> {
917        DAC_CONTROL_LOGIC_CLOCK_SEL_W::new(self, 26)
918    }
919    #[doc = "Bits 27:28"]
920    #[inline(always)]
921    #[must_use]
922    pub fn dac_src_sel(&mut self) -> DAC_SRC_SEL_W<TVE_CONFIGURATION_SPEC> {
923        DAC_SRC_SEL_W::new(self, 27)
924    }
925    #[doc = "Bit 29"]
926    #[inline(always)]
927    #[must_use]
928    pub fn bypass_tv(&mut self) -> BYPASS_TV_W<TVE_CONFIGURATION_SPEC> {
929        BYPASS_TV_W::new(self, 29)
930    }
931    #[doc = r" Writes raw bits to the register."]
932    #[doc = r""]
933    #[doc = r" # Safety"]
934    #[doc = r""]
935    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
936    #[inline(always)]
937    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
938        self.bits = bits;
939        self
940    }
941}
942#[doc = "TV Encoder Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tve_configuration::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tve_configuration::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
943pub struct TVE_CONFIGURATION_SPEC;
944impl crate::RegisterSpec for TVE_CONFIGURATION_SPEC {
945    type Ux = u32;
946}
947#[doc = "`read()` method returns [`tve_configuration::R`](R) reader structure"]
948impl crate::Readable for TVE_CONFIGURATION_SPEC {}
949#[doc = "`write(|w| ..)` method takes [`tve_configuration::W`](W) writer structure"]
950impl crate::Writable for TVE_CONFIGURATION_SPEC {
951    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
952    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
953}
954#[doc = "`reset()` method sets tve_configuration to value 0x0001_0000"]
955impl crate::Resettable for TVE_CONFIGURATION_SPEC {
956    const RESET_VALUE: Self::Ux = 0x0001_0000;
957}
d1_pac/tve/tve_configuration.rs

d1_pac/tve/
tve_configuration.rs
