d1_pac/pwm/
pcgr.rs

1#[doc = "Register `pcgr` reader"]
2pub type R = crate::R<PCGR_SPEC>;
3#[doc = "Register `pcgr` writer"]
4pub type W = crate::W<PCGR_SPEC>;
5#[doc = "Field `pwm_clk_gating[0-7]` reader - Gating clock for PWM"]
6pub type PWM_CLK_GATING_R = crate::BitReader<PWM_CLK_GATING_A>;
7#[doc = "Gating clock for PWM\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum PWM_CLK_GATING_A {
10    #[doc = "0: Mask"]
11    MASK = 0,
12    #[doc = "1: Pass"]
13    PASS = 1,
14}
15impl From<PWM_CLK_GATING_A> for bool {
16    #[inline(always)]
17    fn from(variant: PWM_CLK_GATING_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl PWM_CLK_GATING_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> PWM_CLK_GATING_A {
25        match self.bits {
26            false => PWM_CLK_GATING_A::MASK,
27            true => PWM_CLK_GATING_A::PASS,
28        }
29    }
30    #[doc = "Mask"]
31    #[inline(always)]
32    pub fn is_mask(&self) -> bool {
33        *self == PWM_CLK_GATING_A::MASK
34    }
35    #[doc = "Pass"]
36    #[inline(always)]
37    pub fn is_pass(&self) -> bool {
38        *self == PWM_CLK_GATING_A::PASS
39    }
40}
41#[doc = "Field `pwm_clk_gating[0-7]` writer - Gating clock for PWM"]
42pub type PWM_CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, PWM_CLK_GATING_A>;
43impl<'a, REG> PWM_CLK_GATING_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Mask"]
48    #[inline(always)]
49    pub fn mask(self) -> &'a mut crate::W<REG> {
50        self.variant(PWM_CLK_GATING_A::MASK)
51    }
52    #[doc = "Pass"]
53    #[inline(always)]
54    pub fn pass(self) -> &'a mut crate::W<REG> {
55        self.variant(PWM_CLK_GATING_A::PASS)
56    }
57}
58#[doc = "Field `pwm_clk_bypass[0-7]` reader - Bypass clock source (after pre-scale) to PWM output"]
59pub type PWM_CLK_BYPASS_R = crate::BitReader<PWM_CLK_BYPASS_A>;
60#[doc = "Bypass clock source (after pre-scale) to PWM output\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum PWM_CLK_BYPASS_A {
63    #[doc = "0: not bypass"]
64    NOT_BYPASS = 0,
65    #[doc = "1: bypass"]
66    BYPASS = 1,
67}
68impl From<PWM_CLK_BYPASS_A> for bool {
69    #[inline(always)]
70    fn from(variant: PWM_CLK_BYPASS_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl PWM_CLK_BYPASS_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> PWM_CLK_BYPASS_A {
78        match self.bits {
79            false => PWM_CLK_BYPASS_A::NOT_BYPASS,
80            true => PWM_CLK_BYPASS_A::BYPASS,
81        }
82    }
83    #[doc = "not bypass"]
84    #[inline(always)]
85    pub fn is_not_bypass(&self) -> bool {
86        *self == PWM_CLK_BYPASS_A::NOT_BYPASS
87    }
88    #[doc = "bypass"]
89    #[inline(always)]
90    pub fn is_bypass(&self) -> bool {
91        *self == PWM_CLK_BYPASS_A::BYPASS
92    }
93}
94#[doc = "Field `pwm_clk_bypass[0-7]` writer - Bypass clock source (after pre-scale) to PWM output"]
95pub type PWM_CLK_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG, PWM_CLK_BYPASS_A>;
96impl<'a, REG> PWM_CLK_BYPASS_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "not bypass"]
101    #[inline(always)]
102    pub fn not_bypass(self) -> &'a mut crate::W<REG> {
103        self.variant(PWM_CLK_BYPASS_A::NOT_BYPASS)
104    }
105    #[doc = "bypass"]
106    #[inline(always)]
107    pub fn bypass(self) -> &'a mut crate::W<REG> {
108        self.variant(PWM_CLK_BYPASS_A::BYPASS)
109    }
110}
111impl R {
112    #[doc = "Gating clock for PWM\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pwm0_clk_gating` field"]
113    #[inline(always)]
114    pub fn pwm_clk_gating(&self, n: u8) -> PWM_CLK_GATING_R {
115        #[allow(clippy::no_effect)]
116        [(); 8][n as usize];
117        PWM_CLK_GATING_R::new(((self.bits >> n) & 1) != 0)
118    }
119    #[doc = "Bit 0 - Gating clock for PWM"]
120    #[inline(always)]
121    pub fn pwm0_clk_gating(&self) -> PWM_CLK_GATING_R {
122        PWM_CLK_GATING_R::new((self.bits & 1) != 0)
123    }
124    #[doc = "Bit 1 - Gating clock for PWM"]
125    #[inline(always)]
126    pub fn pwm1_clk_gating(&self) -> PWM_CLK_GATING_R {
127        PWM_CLK_GATING_R::new(((self.bits >> 1) & 1) != 0)
128    }
129    #[doc = "Bit 2 - Gating clock for PWM"]
130    #[inline(always)]
131    pub fn pwm2_clk_gating(&self) -> PWM_CLK_GATING_R {
132        PWM_CLK_GATING_R::new(((self.bits >> 2) & 1) != 0)
133    }
134    #[doc = "Bit 3 - Gating clock for PWM"]
135    #[inline(always)]
136    pub fn pwm3_clk_gating(&self) -> PWM_CLK_GATING_R {
137        PWM_CLK_GATING_R::new(((self.bits >> 3) & 1) != 0)
138    }
139    #[doc = "Bit 4 - Gating clock for PWM"]
140    #[inline(always)]
141    pub fn pwm4_clk_gating(&self) -> PWM_CLK_GATING_R {
142        PWM_CLK_GATING_R::new(((self.bits >> 4) & 1) != 0)
143    }
144    #[doc = "Bit 5 - Gating clock for PWM"]
145    #[inline(always)]
146    pub fn pwm5_clk_gating(&self) -> PWM_CLK_GATING_R {
147        PWM_CLK_GATING_R::new(((self.bits >> 5) & 1) != 0)
148    }
149    #[doc = "Bit 6 - Gating clock for PWM"]
150    #[inline(always)]
151    pub fn pwm6_clk_gating(&self) -> PWM_CLK_GATING_R {
152        PWM_CLK_GATING_R::new(((self.bits >> 6) & 1) != 0)
153    }
154    #[doc = "Bit 7 - Gating clock for PWM"]
155    #[inline(always)]
156    pub fn pwm7_clk_gating(&self) -> PWM_CLK_GATING_R {
157        PWM_CLK_GATING_R::new(((self.bits >> 7) & 1) != 0)
158    }
159    #[doc = "Bypass clock source (after pre-scale) to PWM output\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pwm0_clk_bypass` field"]
160    #[inline(always)]
161    pub fn pwm_clk_bypass(&self, n: u8) -> PWM_CLK_BYPASS_R {
162        #[allow(clippy::no_effect)]
163        [(); 8][n as usize];
164        PWM_CLK_BYPASS_R::new(((self.bits >> (n + 16)) & 1) != 0)
165    }
166    #[doc = "Bit 16 - Bypass clock source (after pre-scale) to PWM output"]
167    #[inline(always)]
168    pub fn pwm0_clk_bypass(&self) -> PWM_CLK_BYPASS_R {
169        PWM_CLK_BYPASS_R::new(((self.bits >> 16) & 1) != 0)
170    }
171    #[doc = "Bit 17 - Bypass clock source (after pre-scale) to PWM output"]
172    #[inline(always)]
173    pub fn pwm1_clk_bypass(&self) -> PWM_CLK_BYPASS_R {
174        PWM_CLK_BYPASS_R::new(((self.bits >> 17) & 1) != 0)
175    }
176    #[doc = "Bit 18 - Bypass clock source (after pre-scale) to PWM output"]
177    #[inline(always)]
178    pub fn pwm2_clk_bypass(&self) -> PWM_CLK_BYPASS_R {
179        PWM_CLK_BYPASS_R::new(((self.bits >> 18) & 1) != 0)
180    }
181    #[doc = "Bit 19 - Bypass clock source (after pre-scale) to PWM output"]
182    #[inline(always)]
183    pub fn pwm3_clk_bypass(&self) -> PWM_CLK_BYPASS_R {
184        PWM_CLK_BYPASS_R::new(((self.bits >> 19) & 1) != 0)
185    }
186    #[doc = "Bit 20 - Bypass clock source (after pre-scale) to PWM output"]
187    #[inline(always)]
188    pub fn pwm4_clk_bypass(&self) -> PWM_CLK_BYPASS_R {
189        PWM_CLK_BYPASS_R::new(((self.bits >> 20) & 1) != 0)
190    }
191    #[doc = "Bit 21 - Bypass clock source (after pre-scale) to PWM output"]
192    #[inline(always)]
193    pub fn pwm5_clk_bypass(&self) -> PWM_CLK_BYPASS_R {
194        PWM_CLK_BYPASS_R::new(((self.bits >> 21) & 1) != 0)
195    }
196    #[doc = "Bit 22 - Bypass clock source (after pre-scale) to PWM output"]
197    #[inline(always)]
198    pub fn pwm6_clk_bypass(&self) -> PWM_CLK_BYPASS_R {
199        PWM_CLK_BYPASS_R::new(((self.bits >> 22) & 1) != 0)
200    }
201    #[doc = "Bit 23 - Bypass clock source (after pre-scale) to PWM output"]
202    #[inline(always)]
203    pub fn pwm7_clk_bypass(&self) -> PWM_CLK_BYPASS_R {
204        PWM_CLK_BYPASS_R::new(((self.bits >> 23) & 1) != 0)
205    }
206}
207impl W {
208    #[doc = "Gating clock for PWM\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pwm0_clk_gating` field"]
209    #[inline(always)]
210    #[must_use]
211    pub fn pwm_clk_gating(&mut self, n: u8) -> PWM_CLK_GATING_W<PCGR_SPEC> {
212        #[allow(clippy::no_effect)]
213        [(); 8][n as usize];
214        PWM_CLK_GATING_W::new(self, n)
215    }
216    #[doc = "Bit 0 - Gating clock for PWM"]
217    #[inline(always)]
218    #[must_use]
219    pub fn pwm0_clk_gating(&mut self) -> PWM_CLK_GATING_W<PCGR_SPEC> {
220        PWM_CLK_GATING_W::new(self, 0)
221    }
222    #[doc = "Bit 1 - Gating clock for PWM"]
223    #[inline(always)]
224    #[must_use]
225    pub fn pwm1_clk_gating(&mut self) -> PWM_CLK_GATING_W<PCGR_SPEC> {
226        PWM_CLK_GATING_W::new(self, 1)
227    }
228    #[doc = "Bit 2 - Gating clock for PWM"]
229    #[inline(always)]
230    #[must_use]
231    pub fn pwm2_clk_gating(&mut self) -> PWM_CLK_GATING_W<PCGR_SPEC> {
232        PWM_CLK_GATING_W::new(self, 2)
233    }
234    #[doc = "Bit 3 - Gating clock for PWM"]
235    #[inline(always)]
236    #[must_use]
237    pub fn pwm3_clk_gating(&mut self) -> PWM_CLK_GATING_W<PCGR_SPEC> {
238        PWM_CLK_GATING_W::new(self, 3)
239    }
240    #[doc = "Bit 4 - Gating clock for PWM"]
241    #[inline(always)]
242    #[must_use]
243    pub fn pwm4_clk_gating(&mut self) -> PWM_CLK_GATING_W<PCGR_SPEC> {
244        PWM_CLK_GATING_W::new(self, 4)
245    }
246    #[doc = "Bit 5 - Gating clock for PWM"]
247    #[inline(always)]
248    #[must_use]
249    pub fn pwm5_clk_gating(&mut self) -> PWM_CLK_GATING_W<PCGR_SPEC> {
250        PWM_CLK_GATING_W::new(self, 5)
251    }
252    #[doc = "Bit 6 - Gating clock for PWM"]
253    #[inline(always)]
254    #[must_use]
255    pub fn pwm6_clk_gating(&mut self) -> PWM_CLK_GATING_W<PCGR_SPEC> {
256        PWM_CLK_GATING_W::new(self, 6)
257    }
258    #[doc = "Bit 7 - Gating clock for PWM"]
259    #[inline(always)]
260    #[must_use]
261    pub fn pwm7_clk_gating(&mut self) -> PWM_CLK_GATING_W<PCGR_SPEC> {
262        PWM_CLK_GATING_W::new(self, 7)
263    }
264    #[doc = "Bypass clock source (after pre-scale) to PWM output\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pwm0_clk_bypass` field"]
265    #[inline(always)]
266    #[must_use]
267    pub fn pwm_clk_bypass(&mut self, n: u8) -> PWM_CLK_BYPASS_W<PCGR_SPEC> {
268        #[allow(clippy::no_effect)]
269        [(); 8][n as usize];
270        PWM_CLK_BYPASS_W::new(self, n + 16)
271    }
272    #[doc = "Bit 16 - Bypass clock source (after pre-scale) to PWM output"]
273    #[inline(always)]
274    #[must_use]
275    pub fn pwm0_clk_bypass(&mut self) -> PWM_CLK_BYPASS_W<PCGR_SPEC> {
276        PWM_CLK_BYPASS_W::new(self, 16)
277    }
278    #[doc = "Bit 17 - Bypass clock source (after pre-scale) to PWM output"]
279    #[inline(always)]
280    #[must_use]
281    pub fn pwm1_clk_bypass(&mut self) -> PWM_CLK_BYPASS_W<PCGR_SPEC> {
282        PWM_CLK_BYPASS_W::new(self, 17)
283    }
284    #[doc = "Bit 18 - Bypass clock source (after pre-scale) to PWM output"]
285    #[inline(always)]
286    #[must_use]
287    pub fn pwm2_clk_bypass(&mut self) -> PWM_CLK_BYPASS_W<PCGR_SPEC> {
288        PWM_CLK_BYPASS_W::new(self, 18)
289    }
290    #[doc = "Bit 19 - Bypass clock source (after pre-scale) to PWM output"]
291    #[inline(always)]
292    #[must_use]
293    pub fn pwm3_clk_bypass(&mut self) -> PWM_CLK_BYPASS_W<PCGR_SPEC> {
294        PWM_CLK_BYPASS_W::new(self, 19)
295    }
296    #[doc = "Bit 20 - Bypass clock source (after pre-scale) to PWM output"]
297    #[inline(always)]
298    #[must_use]
299    pub fn pwm4_clk_bypass(&mut self) -> PWM_CLK_BYPASS_W<PCGR_SPEC> {
300        PWM_CLK_BYPASS_W::new(self, 20)
301    }
302    #[doc = "Bit 21 - Bypass clock source (after pre-scale) to PWM output"]
303    #[inline(always)]
304    #[must_use]
305    pub fn pwm5_clk_bypass(&mut self) -> PWM_CLK_BYPASS_W<PCGR_SPEC> {
306        PWM_CLK_BYPASS_W::new(self, 21)
307    }
308    #[doc = "Bit 22 - Bypass clock source (after pre-scale) to PWM output"]
309    #[inline(always)]
310    #[must_use]
311    pub fn pwm6_clk_bypass(&mut self) -> PWM_CLK_BYPASS_W<PCGR_SPEC> {
312        PWM_CLK_BYPASS_W::new(self, 22)
313    }
314    #[doc = "Bit 23 - Bypass clock source (after pre-scale) to PWM output"]
315    #[inline(always)]
316    #[must_use]
317    pub fn pwm7_clk_bypass(&mut self) -> PWM_CLK_BYPASS_W<PCGR_SPEC> {
318        PWM_CLK_BYPASS_W::new(self, 23)
319    }
320    #[doc = r" Writes raw bits to the register."]
321    #[doc = r""]
322    #[doc = r" # Safety"]
323    #[doc = r""]
324    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
325    #[inline(always)]
326    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
327        self.bits = bits;
328        self
329    }
330}
331#[doc = "PWM Clock Gating Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
332pub struct PCGR_SPEC;
333impl crate::RegisterSpec for PCGR_SPEC {
334    type Ux = u32;
335}
336#[doc = "`read()` method returns [`pcgr::R`](R) reader structure"]
337impl crate::Readable for PCGR_SPEC {}
338#[doc = "`write(|w| ..)` method takes [`pcgr::W`](W) writer structure"]
339impl crate::Writable for PCGR_SPEC {
340    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
341    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
342}
343#[doc = "`reset()` method sets pcgr to value 0"]
344impl crate::Resettable for PCGR_SPEC {
345    const RESET_VALUE: Self::Ux = 0;
346}
d1_pac/pwm/pcgr.rs

d1_pac/pwm/
pcgr.rs
