d1_pac/iommu/
iommu_int_clr.rs

1#[doc = "Register `iommu_int_clr` reader"]
2pub type R = crate::R<IOMMU_INT_CLR_SPEC>;
3#[doc = "Register `iommu_int_clr` writer"]
4pub type W = crate::W<IOMMU_INT_CLR_SPEC>;
5#[doc = "Micro TLB\\[i\\] permission invalid interrupt clear bit\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum MICRO_TLB_INVALID_CLR_AW {
8    #[doc = "0: Invalid operation"]
9    INVALID = 0,
10    #[doc = "1: Clear interrupt Note: The bit is not used."]
11    CLEAR = 1,
12}
13impl From<MICRO_TLB_INVALID_CLR_AW> for bool {
14    #[inline(always)]
15    fn from(variant: MICRO_TLB_INVALID_CLR_AW) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `micro_tlb_invalid_clr[0-6]` writer - Micro TLB\\[i\\] permission invalid interrupt clear bit"]
20pub type MICRO_TLB_INVALID_CLR_W<'a, REG> = crate::BitWriter<'a, REG, MICRO_TLB_INVALID_CLR_AW>;
21impl<'a, REG> MICRO_TLB_INVALID_CLR_W<'a, REG>
22where
23    REG: crate::Writable + crate::RegisterSpec,
24{
25    #[doc = "Invalid operation"]
26    #[inline(always)]
27    pub fn invalid(self) -> &'a mut crate::W<REG> {
28        self.variant(MICRO_TLB_INVALID_CLR_AW::INVALID)
29    }
30    #[doc = "Clear interrupt Note: The bit is not used."]
31    #[inline(always)]
32    pub fn clear(self) -> &'a mut crate::W<REG> {
33        self.variant(MICRO_TLB_INVALID_CLR_AW::CLEAR)
34    }
35}
36#[doc = "Level\\[i\\] page table invalid interrupt clear bit\n\nValue on reset: 0"]
37#[derive(Clone, Copy, Debug, PartialEq, Eq)]
38pub enum L_PAGE_TABLE_INVALID_CLR_AW {
39    #[doc = "0: Invalid operation"]
40    INVALID = 0,
41    #[doc = "1: Clear interrupt"]
42    CLEAR = 1,
43}
44impl From<L_PAGE_TABLE_INVALID_CLR_AW> for bool {
45    #[inline(always)]
46    fn from(variant: L_PAGE_TABLE_INVALID_CLR_AW) -> Self {
47        variant as u8 != 0
48    }
49}
50#[doc = "Field `l_page_table_invalid_clr[0-1]` writer - Level\\[i\\] page table invalid interrupt clear bit"]
51pub type L_PAGE_TABLE_INVALID_CLR_W<'a, REG> =
52    crate::BitWriter<'a, REG, L_PAGE_TABLE_INVALID_CLR_AW>;
53impl<'a, REG> L_PAGE_TABLE_INVALID_CLR_W<'a, REG>
54where
55    REG: crate::Writable + crate::RegisterSpec,
56{
57    #[doc = "Invalid operation"]
58    #[inline(always)]
59    pub fn invalid(self) -> &'a mut crate::W<REG> {
60        self.variant(L_PAGE_TABLE_INVALID_CLR_AW::INVALID)
61    }
62    #[doc = "Clear interrupt"]
63    #[inline(always)]
64    pub fn clear(self) -> &'a mut crate::W<REG> {
65        self.variant(L_PAGE_TABLE_INVALID_CLR_AW::CLEAR)
66    }
67}
68impl W {
69    #[doc = "Micro TLB\\[i\\] permission invalid interrupt clear bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `micro_tlb0_invalid_clr` field"]
70    #[inline(always)]
71    #[must_use]
72    pub fn micro_tlb_invalid_clr(&mut self, n: u8) -> MICRO_TLB_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
73        #[allow(clippy::no_effect)]
74        [(); 7][n as usize];
75        MICRO_TLB_INVALID_CLR_W::new(self, n * 2)
76    }
77    #[doc = "Bit 0 - Micro TLB\\[i\\] permission invalid interrupt clear bit"]
78    #[inline(always)]
79    #[must_use]
80    pub fn micro_tlb0_invalid_clr(&mut self) -> MICRO_TLB_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
81        MICRO_TLB_INVALID_CLR_W::new(self, 0)
82    }
83    #[doc = "Bit 2 - Micro TLB\\[i\\] permission invalid interrupt clear bit"]
84    #[inline(always)]
85    #[must_use]
86    pub fn micro_tlb1_invalid_clr(&mut self) -> MICRO_TLB_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
87        MICRO_TLB_INVALID_CLR_W::new(self, 2)
88    }
89    #[doc = "Bit 4 - Micro TLB\\[i\\] permission invalid interrupt clear bit"]
90    #[inline(always)]
91    #[must_use]
92    pub fn micro_tlb2_invalid_clr(&mut self) -> MICRO_TLB_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
93        MICRO_TLB_INVALID_CLR_W::new(self, 4)
94    }
95    #[doc = "Bit 6 - Micro TLB\\[i\\] permission invalid interrupt clear bit"]
96    #[inline(always)]
97    #[must_use]
98    pub fn micro_tlb3_invalid_clr(&mut self) -> MICRO_TLB_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
99        MICRO_TLB_INVALID_CLR_W::new(self, 6)
100    }
101    #[doc = "Bit 8 - Micro TLB\\[i\\] permission invalid interrupt clear bit"]
102    #[inline(always)]
103    #[must_use]
104    pub fn micro_tlb4_invalid_clr(&mut self) -> MICRO_TLB_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
105        MICRO_TLB_INVALID_CLR_W::new(self, 8)
106    }
107    #[doc = "Bit 10 - Micro TLB\\[i\\] permission invalid interrupt clear bit"]
108    #[inline(always)]
109    #[must_use]
110    pub fn micro_tlb5_invalid_clr(&mut self) -> MICRO_TLB_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
111        MICRO_TLB_INVALID_CLR_W::new(self, 10)
112    }
113    #[doc = "Bit 12 - Micro TLB\\[i\\] permission invalid interrupt clear bit"]
114    #[inline(always)]
115    #[must_use]
116    pub fn micro_tlb6_invalid_clr(&mut self) -> MICRO_TLB_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
117        MICRO_TLB_INVALID_CLR_W::new(self, 12)
118    }
119    #[doc = "Level\\[i\\] page table invalid interrupt clear bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `l0_page_table_invalid_clr` field"]
120    #[inline(always)]
121    #[must_use]
122    pub fn l_page_table_invalid_clr(
123        &mut self,
124        n: u8,
125    ) -> L_PAGE_TABLE_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
126        #[allow(clippy::no_effect)]
127        [(); 2][n as usize];
128        L_PAGE_TABLE_INVALID_CLR_W::new(self, n + 16)
129    }
130    #[doc = "Bit 16 - Level\\[i\\] page table invalid interrupt clear bit"]
131    #[inline(always)]
132    #[must_use]
133    pub fn l0_page_table_invalid_clr(&mut self) -> L_PAGE_TABLE_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
134        L_PAGE_TABLE_INVALID_CLR_W::new(self, 16)
135    }
136    #[doc = "Bit 17 - Level\\[i\\] page table invalid interrupt clear bit"]
137    #[inline(always)]
138    #[must_use]
139    pub fn l1_page_table_invalid_clr(&mut self) -> L_PAGE_TABLE_INVALID_CLR_W<IOMMU_INT_CLR_SPEC> {
140        L_PAGE_TABLE_INVALID_CLR_W::new(self, 17)
141    }
142    #[doc = r" Writes raw bits to the register."]
143    #[doc = r""]
144    #[doc = r" # Safety"]
145    #[doc = r""]
146    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
147    #[inline(always)]
148    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
149        self.bits = bits;
150        self
151    }
152}
153#[doc = "IOMMU Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_int_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
154pub struct IOMMU_INT_CLR_SPEC;
155impl crate::RegisterSpec for IOMMU_INT_CLR_SPEC {
156    type Ux = u32;
157}
158#[doc = "`read()` method returns [`iommu_int_clr::R`](R) reader structure"]
159impl crate::Readable for IOMMU_INT_CLR_SPEC {}
160#[doc = "`write(|w| ..)` method takes [`iommu_int_clr::W`](W) writer structure"]
161impl crate::Writable for IOMMU_INT_CLR_SPEC {
162    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
163    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
164}
165#[doc = "`reset()` method sets iommu_int_clr to value 0"]
166impl crate::Resettable for IOMMU_INT_CLR_SPEC {
167    const RESET_VALUE: Self::Ux = 0;
168}
d1_pac/iommu/iommu_int_clr.rs

d1_pac/iommu/
iommu_int_clr.rs
