d1_pac/usb1/ohci_memory_pointer_partition/
hc_hcca.rs

1#[doc = "Register `hc_hcca` reader"]
2pub type R = crate::R<HC_HCCA_SPEC>;
3#[doc = "Register `hc_hcca` writer"]
4pub type W = crate::W<HC_HCCA_SPEC>;
5#[doc = "Field `hcca_7_0` reader - The alignment restriction in HcHCCA register is evaluated by examining the number of zeros in the lower order bits. The minimum alignment is 256 bytes, therefore, bits 0 through 7 must always return 0 when read."]
6pub type HCCA_7_0_R = crate::FieldReader;
7#[doc = "Field `hcca_31_8` reader - This is the base address of the Host Controller Communication Area. This area is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver."]
8pub type HCCA_31_8_R = crate::FieldReader<u32>;
9#[doc = "Field `hcca_31_8` writer - This is the base address of the Host Controller Communication Area. This area is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver."]
10pub type HCCA_31_8_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
11impl R {
12    #[doc = "Bits 0:7 - The alignment restriction in HcHCCA register is evaluated by examining the number of zeros in the lower order bits. The minimum alignment is 256 bytes, therefore, bits 0 through 7 must always return 0 when read."]
13    #[inline(always)]
14    pub fn hcca_7_0(&self) -> HCCA_7_0_R {
15        HCCA_7_0_R::new((self.bits & 0xff) as u8)
16    }
17    #[doc = "Bits 8:31 - This is the base address of the Host Controller Communication Area. This area is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver."]
18    #[inline(always)]
19    pub fn hcca_31_8(&self) -> HCCA_31_8_R {
20        HCCA_31_8_R::new((self.bits >> 8) & 0x00ff_ffff)
21    }
22}
23impl W {
24    #[doc = "Bits 8:31 - This is the base address of the Host Controller Communication Area. This area is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver."]
25    #[inline(always)]
26    #[must_use]
27    pub fn hcca_31_8(&mut self) -> HCCA_31_8_W<HC_HCCA_SPEC> {
28        HCCA_31_8_W::new(self, 8)
29    }
30    #[doc = r" Writes raw bits to the register."]
31    #[doc = r""]
32    #[doc = r" # Safety"]
33    #[doc = r""]
34    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
35    #[inline(always)]
36    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
37        self.bits = bits;
38        self
39    }
40}
41#[doc = "OHCI HCCA Base\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hc_hcca::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hc_hcca::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
42pub struct HC_HCCA_SPEC;
43impl crate::RegisterSpec for HC_HCCA_SPEC {
44    type Ux = u32;
45}
46#[doc = "`read()` method returns [`hc_hcca::R`](R) reader structure"]
47impl crate::Readable for HC_HCCA_SPEC {}
48#[doc = "`write(|w| ..)` method takes [`hc_hcca::W`](W) writer structure"]
49impl crate::Writable for HC_HCCA_SPEC {
50    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
51    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
52}
53#[doc = "`reset()` method sets hc_hcca to value 0"]
54impl crate::Resettable for HC_HCCA_SPEC {
55    const RESET_VALUE: Self::Ux = 0;
56}
d1_pac/usb1/ohci_memory_pointer_partition/hc_hcca.rs

d1_pac/usb1/ohci_memory_pointer_partition/
hc_hcca.rs
