d1_pac/usb1/ohci_memory_pointer_partition/
hc_done_head.rs1#[doc = "Register `hc_done_head` reader"]
2pub type R = crate::R<HC_DONE_HEAD_SPEC>;
3#[doc = "Register `hc_done_head` writer"]
4pub type W = crate::W<HC_DONE_HEAD_SPEC>;
5#[doc = "Field `dh_3_0` reader - Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the PCED, through bit 0 to bit 3 must be zero in this field."]
6pub type DH_3_0_R = crate::FieldReader;
7#[doc = "Field `dh_31_4` reader - When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. HC then overwrites the content of HcDoneHead with the address of this TD. This is set to zero whenever HC writes the content of this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus."]
8pub type DH_31_4_R = crate::FieldReader<u32>;
9#[doc = "Field `dh_31_4` writer - When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. HC then overwrites the content of HcDoneHead with the address of this TD. This is set to zero whenever HC writes the content of this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus."]
10pub type DH_31_4_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
11impl R {
12 #[doc = "Bits 0:3 - Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the PCED, through bit 0 to bit 3 must be zero in this field."]
13 #[inline(always)]
14 pub fn dh_3_0(&self) -> DH_3_0_R {
15 DH_3_0_R::new((self.bits & 0x0f) as u8)
16 }
17 #[doc = "Bits 4:31 - When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. HC then overwrites the content of HcDoneHead with the address of this TD. This is set to zero whenever HC writes the content of this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus."]
18 #[inline(always)]
19 pub fn dh_31_4(&self) -> DH_31_4_R {
20 DH_31_4_R::new((self.bits >> 4) & 0x0fff_ffff)
21 }
22}
23impl W {
24 #[doc = "Bits 4:31 - When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. HC then overwrites the content of HcDoneHead with the address of this TD. This is set to zero whenever HC writes the content of this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus."]
25 #[inline(always)]
26 #[must_use]
27 pub fn dh_31_4(&mut self) -> DH_31_4_W<HC_DONE_HEAD_SPEC> {
28 DH_31_4_W::new(self, 4)
29 }
30 #[doc = r" Writes raw bits to the register."]
31 #[doc = r""]
32 #[doc = r" # Safety"]
33 #[doc = r""]
34 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
35 #[inline(always)]
36 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
37 self.bits = bits;
38 self
39 }
40}
41#[doc = "OHCI Done Head Base\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hc_done_head::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hc_done_head::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
42pub struct HC_DONE_HEAD_SPEC;
43impl crate::RegisterSpec for HC_DONE_HEAD_SPEC {
44 type Ux = u32;
45}
46#[doc = "`read()` method returns [`hc_done_head::R`](R) reader structure"]
47impl crate::Readable for HC_DONE_HEAD_SPEC {}
48#[doc = "`write(|w| ..)` method takes [`hc_done_head::W`](W) writer structure"]
49impl crate::Writable for HC_DONE_HEAD_SPEC {
50 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
51 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
52}
53#[doc = "`reset()` method sets hc_done_head to value 0"]
54impl crate::Resettable for HC_DONE_HEAD_SPEC {
55 const RESET_VALUE: Self::Ux = 0;
56}