d1_pac/usb1/ohci_control_status_partition/
hc_interrupt_enable.rs

1#[doc = "Register `hc_interrupt_enable` reader"]
2pub type R = crate::R<HC_INTERRUPT_ENABLE_SPEC>;
3#[doc = "Register `hc_interrupt_enable` writer"]
4pub type W = crate::W<HC_INTERRUPT_ENABLE_SPEC>;
5#[doc = "Field `scheduling_overrun` reader - SchedulingOverrun Interrupt Enable"]
6pub type SCHEDULING_OVERRUN_R = crate::BitReader<SCHEDULING_OVERRUN_A>;
7#[doc = "SchedulingOverrun Interrupt Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum SCHEDULING_OVERRUN_A {
10    #[doc = "0: Ignore"]
11    IGNORE = 0,
12    #[doc = "1: Enable interrupt generation due to Scheduling Overrun"]
13    ENABLE = 1,
14}
15impl From<SCHEDULING_OVERRUN_A> for bool {
16    #[inline(always)]
17    fn from(variant: SCHEDULING_OVERRUN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl SCHEDULING_OVERRUN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> SCHEDULING_OVERRUN_A {
25        match self.bits {
26            false => SCHEDULING_OVERRUN_A::IGNORE,
27            true => SCHEDULING_OVERRUN_A::ENABLE,
28        }
29    }
30    #[doc = "Ignore"]
31    #[inline(always)]
32    pub fn is_ignore(&self) -> bool {
33        *self == SCHEDULING_OVERRUN_A::IGNORE
34    }
35    #[doc = "Enable interrupt generation due to Scheduling Overrun"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == SCHEDULING_OVERRUN_A::ENABLE
39    }
40}
41#[doc = "Field `scheduling_overrun` writer - SchedulingOverrun Interrupt Enable"]
42pub type SCHEDULING_OVERRUN_W<'a, REG> = crate::BitWriter<'a, REG, SCHEDULING_OVERRUN_A>;
43impl<'a, REG> SCHEDULING_OVERRUN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Ignore"]
48    #[inline(always)]
49    pub fn ignore(self) -> &'a mut crate::W<REG> {
50        self.variant(SCHEDULING_OVERRUN_A::IGNORE)
51    }
52    #[doc = "Enable interrupt generation due to Scheduling Overrun"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(SCHEDULING_OVERRUN_A::ENABLE)
56    }
57}
58#[doc = "Field `writeback_done_head` reader - WritebackDoneHead Interrupt Enable"]
59pub type WRITEBACK_DONE_HEAD_R = crate::BitReader<WRITEBACK_DONE_HEAD_A>;
60#[doc = "WritebackDoneHead Interrupt Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum WRITEBACK_DONE_HEAD_A {
63    #[doc = "0: Ignore"]
64    IGNORE = 0,
65    #[doc = "1: Enable interrupt generation due to Writeback Done Head"]
66    ENABLE = 1,
67}
68impl From<WRITEBACK_DONE_HEAD_A> for bool {
69    #[inline(always)]
70    fn from(variant: WRITEBACK_DONE_HEAD_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl WRITEBACK_DONE_HEAD_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> WRITEBACK_DONE_HEAD_A {
78        match self.bits {
79            false => WRITEBACK_DONE_HEAD_A::IGNORE,
80            true => WRITEBACK_DONE_HEAD_A::ENABLE,
81        }
82    }
83    #[doc = "Ignore"]
84    #[inline(always)]
85    pub fn is_ignore(&self) -> bool {
86        *self == WRITEBACK_DONE_HEAD_A::IGNORE
87    }
88    #[doc = "Enable interrupt generation due to Writeback Done Head"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == WRITEBACK_DONE_HEAD_A::ENABLE
92    }
93}
94#[doc = "Field `writeback_done_head` writer - WritebackDoneHead Interrupt Enable"]
95pub type WRITEBACK_DONE_HEAD_W<'a, REG> = crate::BitWriter<'a, REG, WRITEBACK_DONE_HEAD_A>;
96impl<'a, REG> WRITEBACK_DONE_HEAD_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Ignore"]
101    #[inline(always)]
102    pub fn ignore(self) -> &'a mut crate::W<REG> {
103        self.variant(WRITEBACK_DONE_HEAD_A::IGNORE)
104    }
105    #[doc = "Enable interrupt generation due to Writeback Done Head"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(WRITEBACK_DONE_HEAD_A::ENABLE)
109    }
110}
111#[doc = "Field `start_of_frame` reader - StartofFrame Interrupt Enable"]
112pub type START_OF_FRAME_R = crate::BitReader<START_OF_FRAME_A>;
113#[doc = "StartofFrame Interrupt Enable\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum START_OF_FRAME_A {
116    #[doc = "0: Ignore"]
117    IGNORE = 0,
118    #[doc = "1: Enable interrupt generation due to Start of Frame"]
119    ENABLE = 1,
120}
121impl From<START_OF_FRAME_A> for bool {
122    #[inline(always)]
123    fn from(variant: START_OF_FRAME_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl START_OF_FRAME_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> START_OF_FRAME_A {
131        match self.bits {
132            false => START_OF_FRAME_A::IGNORE,
133            true => START_OF_FRAME_A::ENABLE,
134        }
135    }
136    #[doc = "Ignore"]
137    #[inline(always)]
138    pub fn is_ignore(&self) -> bool {
139        *self == START_OF_FRAME_A::IGNORE
140    }
141    #[doc = "Enable interrupt generation due to Start of Frame"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == START_OF_FRAME_A::ENABLE
145    }
146}
147#[doc = "Field `start_of_frame` writer - StartofFrame Interrupt Enable"]
148pub type START_OF_FRAME_W<'a, REG> = crate::BitWriter<'a, REG, START_OF_FRAME_A>;
149impl<'a, REG> START_OF_FRAME_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Ignore"]
154    #[inline(always)]
155    pub fn ignore(self) -> &'a mut crate::W<REG> {
156        self.variant(START_OF_FRAME_A::IGNORE)
157    }
158    #[doc = "Enable interrupt generation due to Start of Frame"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(START_OF_FRAME_A::ENABLE)
162    }
163}
164#[doc = "Field `resume_detected` reader - ResumeDetected Interrupt Enable"]
165pub type RESUME_DETECTED_R = crate::BitReader<RESUME_DETECTED_A>;
166#[doc = "ResumeDetected Interrupt Enable\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum RESUME_DETECTED_A {
169    #[doc = "0: Ignore"]
170    IGNORE = 0,
171    #[doc = "1: Enable interrupt generation due to Resume Detected"]
172    ENABLE = 1,
173}
174impl From<RESUME_DETECTED_A> for bool {
175    #[inline(always)]
176    fn from(variant: RESUME_DETECTED_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl RESUME_DETECTED_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> RESUME_DETECTED_A {
184        match self.bits {
185            false => RESUME_DETECTED_A::IGNORE,
186            true => RESUME_DETECTED_A::ENABLE,
187        }
188    }
189    #[doc = "Ignore"]
190    #[inline(always)]
191    pub fn is_ignore(&self) -> bool {
192        *self == RESUME_DETECTED_A::IGNORE
193    }
194    #[doc = "Enable interrupt generation due to Resume Detected"]
195    #[inline(always)]
196    pub fn is_enable(&self) -> bool {
197        *self == RESUME_DETECTED_A::ENABLE
198    }
199}
200#[doc = "Field `resume_detected` writer - ResumeDetected Interrupt Enable"]
201pub type RESUME_DETECTED_W<'a, REG> = crate::BitWriter<'a, REG, RESUME_DETECTED_A>;
202impl<'a, REG> RESUME_DETECTED_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Ignore"]
207    #[inline(always)]
208    pub fn ignore(self) -> &'a mut crate::W<REG> {
209        self.variant(RESUME_DETECTED_A::IGNORE)
210    }
211    #[doc = "Enable interrupt generation due to Resume Detected"]
212    #[inline(always)]
213    pub fn enable(self) -> &'a mut crate::W<REG> {
214        self.variant(RESUME_DETECTED_A::ENABLE)
215    }
216}
217#[doc = "Field `unrecoverable_error` reader - UnrecoverableError Interrupt Enable"]
218pub type UNRECOVERABLE_ERROR_R = crate::BitReader<UNRECOVERABLE_ERROR_A>;
219#[doc = "UnrecoverableError Interrupt Enable\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum UNRECOVERABLE_ERROR_A {
222    #[doc = "0: Ignore"]
223    IGNORE = 0,
224    #[doc = "1: Enable interrupt generation due to Unrecoverable Error"]
225    ENABLE = 1,
226}
227impl From<UNRECOVERABLE_ERROR_A> for bool {
228    #[inline(always)]
229    fn from(variant: UNRECOVERABLE_ERROR_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl UNRECOVERABLE_ERROR_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> UNRECOVERABLE_ERROR_A {
237        match self.bits {
238            false => UNRECOVERABLE_ERROR_A::IGNORE,
239            true => UNRECOVERABLE_ERROR_A::ENABLE,
240        }
241    }
242    #[doc = "Ignore"]
243    #[inline(always)]
244    pub fn is_ignore(&self) -> bool {
245        *self == UNRECOVERABLE_ERROR_A::IGNORE
246    }
247    #[doc = "Enable interrupt generation due to Unrecoverable Error"]
248    #[inline(always)]
249    pub fn is_enable(&self) -> bool {
250        *self == UNRECOVERABLE_ERROR_A::ENABLE
251    }
252}
253#[doc = "Field `unrecoverable_error` writer - UnrecoverableError Interrupt Enable"]
254pub type UNRECOVERABLE_ERROR_W<'a, REG> = crate::BitWriter<'a, REG, UNRECOVERABLE_ERROR_A>;
255impl<'a, REG> UNRECOVERABLE_ERROR_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "Ignore"]
260    #[inline(always)]
261    pub fn ignore(self) -> &'a mut crate::W<REG> {
262        self.variant(UNRECOVERABLE_ERROR_A::IGNORE)
263    }
264    #[doc = "Enable interrupt generation due to Unrecoverable Error"]
265    #[inline(always)]
266    pub fn enable(self) -> &'a mut crate::W<REG> {
267        self.variant(UNRECOVERABLE_ERROR_A::ENABLE)
268    }
269}
270#[doc = "Field `frame_number_overflow` reader - FrameNumberOverflow Interrupt Enable"]
271pub type FRAME_NUMBER_OVERFLOW_R = crate::BitReader<FRAME_NUMBER_OVERFLOW_A>;
272#[doc = "FrameNumberOverflow Interrupt Enable\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum FRAME_NUMBER_OVERFLOW_A {
275    #[doc = "0: Ignore"]
276    IGNORE = 0,
277    #[doc = "1: Enable interrupt generation due to Frame Number Overflow"]
278    ENABLE = 1,
279}
280impl From<FRAME_NUMBER_OVERFLOW_A> for bool {
281    #[inline(always)]
282    fn from(variant: FRAME_NUMBER_OVERFLOW_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl FRAME_NUMBER_OVERFLOW_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> FRAME_NUMBER_OVERFLOW_A {
290        match self.bits {
291            false => FRAME_NUMBER_OVERFLOW_A::IGNORE,
292            true => FRAME_NUMBER_OVERFLOW_A::ENABLE,
293        }
294    }
295    #[doc = "Ignore"]
296    #[inline(always)]
297    pub fn is_ignore(&self) -> bool {
298        *self == FRAME_NUMBER_OVERFLOW_A::IGNORE
299    }
300    #[doc = "Enable interrupt generation due to Frame Number Overflow"]
301    #[inline(always)]
302    pub fn is_enable(&self) -> bool {
303        *self == FRAME_NUMBER_OVERFLOW_A::ENABLE
304    }
305}
306#[doc = "Field `frame_number_overflow` writer - FrameNumberOverflow Interrupt Enable"]
307pub type FRAME_NUMBER_OVERFLOW_W<'a, REG> = crate::BitWriter<'a, REG, FRAME_NUMBER_OVERFLOW_A>;
308impl<'a, REG> FRAME_NUMBER_OVERFLOW_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "Ignore"]
313    #[inline(always)]
314    pub fn ignore(self) -> &'a mut crate::W<REG> {
315        self.variant(FRAME_NUMBER_OVERFLOW_A::IGNORE)
316    }
317    #[doc = "Enable interrupt generation due to Frame Number Overflow"]
318    #[inline(always)]
319    pub fn enable(self) -> &'a mut crate::W<REG> {
320        self.variant(FRAME_NUMBER_OVERFLOW_A::ENABLE)
321    }
322}
323#[doc = "Field `root_hub_status_change` reader - RootHubStatusChange Interrupt Enable"]
324pub type ROOT_HUB_STATUS_CHANGE_R = crate::BitReader<ROOT_HUB_STATUS_CHANGE_A>;
325#[doc = "RootHubStatusChange Interrupt Enable\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq, Eq)]
327pub enum ROOT_HUB_STATUS_CHANGE_A {
328    #[doc = "0: Ignore"]
329    IGNORE = 0,
330    #[doc = "1: Enable interrupt generation due to Root Hub Status Change"]
331    ENABLE = 1,
332}
333impl From<ROOT_HUB_STATUS_CHANGE_A> for bool {
334    #[inline(always)]
335    fn from(variant: ROOT_HUB_STATUS_CHANGE_A) -> Self {
336        variant as u8 != 0
337    }
338}
339impl ROOT_HUB_STATUS_CHANGE_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> ROOT_HUB_STATUS_CHANGE_A {
343        match self.bits {
344            false => ROOT_HUB_STATUS_CHANGE_A::IGNORE,
345            true => ROOT_HUB_STATUS_CHANGE_A::ENABLE,
346        }
347    }
348    #[doc = "Ignore"]
349    #[inline(always)]
350    pub fn is_ignore(&self) -> bool {
351        *self == ROOT_HUB_STATUS_CHANGE_A::IGNORE
352    }
353    #[doc = "Enable interrupt generation due to Root Hub Status Change"]
354    #[inline(always)]
355    pub fn is_enable(&self) -> bool {
356        *self == ROOT_HUB_STATUS_CHANGE_A::ENABLE
357    }
358}
359#[doc = "Field `root_hub_status_change` writer - RootHubStatusChange Interrupt Enable"]
360pub type ROOT_HUB_STATUS_CHANGE_W<'a, REG> = crate::BitWriter<'a, REG, ROOT_HUB_STATUS_CHANGE_A>;
361impl<'a, REG> ROOT_HUB_STATUS_CHANGE_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "Ignore"]
366    #[inline(always)]
367    pub fn ignore(self) -> &'a mut crate::W<REG> {
368        self.variant(ROOT_HUB_STATUS_CHANGE_A::IGNORE)
369    }
370    #[doc = "Enable interrupt generation due to Root Hub Status Change"]
371    #[inline(always)]
372    pub fn enable(self) -> &'a mut crate::W<REG> {
373        self.variant(ROOT_HUB_STATUS_CHANGE_A::ENABLE)
374    }
375}
376#[doc = "Field `master_interrupt_enable` reader - MasterInterruptEnable\n\nA '0' writtern to this field is ignored by HC. A '1' written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as Master Interrupt Enable."]
377pub type MASTER_INTERRUPT_ENABLE_R = crate::BitReader;
378#[doc = "Field `master_interrupt_enable` writer - MasterInterruptEnable\n\nA '0' writtern to this field is ignored by HC. A '1' written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as Master Interrupt Enable."]
379pub type MASTER_INTERRUPT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
380impl R {
381    #[doc = "Bit 0 - SchedulingOverrun Interrupt Enable"]
382    #[inline(always)]
383    pub fn scheduling_overrun(&self) -> SCHEDULING_OVERRUN_R {
384        SCHEDULING_OVERRUN_R::new((self.bits & 1) != 0)
385    }
386    #[doc = "Bit 1 - WritebackDoneHead Interrupt Enable"]
387    #[inline(always)]
388    pub fn writeback_done_head(&self) -> WRITEBACK_DONE_HEAD_R {
389        WRITEBACK_DONE_HEAD_R::new(((self.bits >> 1) & 1) != 0)
390    }
391    #[doc = "Bit 2 - StartofFrame Interrupt Enable"]
392    #[inline(always)]
393    pub fn start_of_frame(&self) -> START_OF_FRAME_R {
394        START_OF_FRAME_R::new(((self.bits >> 2) & 1) != 0)
395    }
396    #[doc = "Bit 3 - ResumeDetected Interrupt Enable"]
397    #[inline(always)]
398    pub fn resume_detected(&self) -> RESUME_DETECTED_R {
399        RESUME_DETECTED_R::new(((self.bits >> 3) & 1) != 0)
400    }
401    #[doc = "Bit 4 - UnrecoverableError Interrupt Enable"]
402    #[inline(always)]
403    pub fn unrecoverable_error(&self) -> UNRECOVERABLE_ERROR_R {
404        UNRECOVERABLE_ERROR_R::new(((self.bits >> 4) & 1) != 0)
405    }
406    #[doc = "Bit 5 - FrameNumberOverflow Interrupt Enable"]
407    #[inline(always)]
408    pub fn frame_number_overflow(&self) -> FRAME_NUMBER_OVERFLOW_R {
409        FRAME_NUMBER_OVERFLOW_R::new(((self.bits >> 5) & 1) != 0)
410    }
411    #[doc = "Bit 6 - RootHubStatusChange Interrupt Enable"]
412    #[inline(always)]
413    pub fn root_hub_status_change(&self) -> ROOT_HUB_STATUS_CHANGE_R {
414        ROOT_HUB_STATUS_CHANGE_R::new(((self.bits >> 6) & 1) != 0)
415    }
416    #[doc = "Bit 31 - MasterInterruptEnable\n\nA '0' writtern to this field is ignored by HC. A '1' written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as Master Interrupt Enable."]
417    #[inline(always)]
418    pub fn master_interrupt_enable(&self) -> MASTER_INTERRUPT_ENABLE_R {
419        MASTER_INTERRUPT_ENABLE_R::new(((self.bits >> 31) & 1) != 0)
420    }
421}
422impl W {
423    #[doc = "Bit 0 - SchedulingOverrun Interrupt Enable"]
424    #[inline(always)]
425    #[must_use]
426    pub fn scheduling_overrun(&mut self) -> SCHEDULING_OVERRUN_W<HC_INTERRUPT_ENABLE_SPEC> {
427        SCHEDULING_OVERRUN_W::new(self, 0)
428    }
429    #[doc = "Bit 1 - WritebackDoneHead Interrupt Enable"]
430    #[inline(always)]
431    #[must_use]
432    pub fn writeback_done_head(&mut self) -> WRITEBACK_DONE_HEAD_W<HC_INTERRUPT_ENABLE_SPEC> {
433        WRITEBACK_DONE_HEAD_W::new(self, 1)
434    }
435    #[doc = "Bit 2 - StartofFrame Interrupt Enable"]
436    #[inline(always)]
437    #[must_use]
438    pub fn start_of_frame(&mut self) -> START_OF_FRAME_W<HC_INTERRUPT_ENABLE_SPEC> {
439        START_OF_FRAME_W::new(self, 2)
440    }
441    #[doc = "Bit 3 - ResumeDetected Interrupt Enable"]
442    #[inline(always)]
443    #[must_use]
444    pub fn resume_detected(&mut self) -> RESUME_DETECTED_W<HC_INTERRUPT_ENABLE_SPEC> {
445        RESUME_DETECTED_W::new(self, 3)
446    }
447    #[doc = "Bit 4 - UnrecoverableError Interrupt Enable"]
448    #[inline(always)]
449    #[must_use]
450    pub fn unrecoverable_error(&mut self) -> UNRECOVERABLE_ERROR_W<HC_INTERRUPT_ENABLE_SPEC> {
451        UNRECOVERABLE_ERROR_W::new(self, 4)
452    }
453    #[doc = "Bit 5 - FrameNumberOverflow Interrupt Enable"]
454    #[inline(always)]
455    #[must_use]
456    pub fn frame_number_overflow(&mut self) -> FRAME_NUMBER_OVERFLOW_W<HC_INTERRUPT_ENABLE_SPEC> {
457        FRAME_NUMBER_OVERFLOW_W::new(self, 5)
458    }
459    #[doc = "Bit 6 - RootHubStatusChange Interrupt Enable"]
460    #[inline(always)]
461    #[must_use]
462    pub fn root_hub_status_change(&mut self) -> ROOT_HUB_STATUS_CHANGE_W<HC_INTERRUPT_ENABLE_SPEC> {
463        ROOT_HUB_STATUS_CHANGE_W::new(self, 6)
464    }
465    #[doc = "Bit 31 - MasterInterruptEnable\n\nA '0' writtern to this field is ignored by HC. A '1' written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as Master Interrupt Enable."]
466    #[inline(always)]
467    #[must_use]
468    pub fn master_interrupt_enable(
469        &mut self,
470    ) -> MASTER_INTERRUPT_ENABLE_W<HC_INTERRUPT_ENABLE_SPEC> {
471        MASTER_INTERRUPT_ENABLE_W::new(self, 31)
472    }
473    #[doc = r" Writes raw bits to the register."]
474    #[doc = r""]
475    #[doc = r" # Safety"]
476    #[doc = r""]
477    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
478    #[inline(always)]
479    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
480        self.bits = bits;
481        self
482    }
483}
484#[doc = "OHCI Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hc_interrupt_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hc_interrupt_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
485pub struct HC_INTERRUPT_ENABLE_SPEC;
486impl crate::RegisterSpec for HC_INTERRUPT_ENABLE_SPEC {
487    type Ux = u32;
488}
489#[doc = "`read()` method returns [`hc_interrupt_enable::R`](R) reader structure"]
490impl crate::Readable for HC_INTERRUPT_ENABLE_SPEC {}
491#[doc = "`write(|w| ..)` method takes [`hc_interrupt_enable::W`](W) writer structure"]
492impl crate::Writable for HC_INTERRUPT_ENABLE_SPEC {
493    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
494    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
495}
496#[doc = "`reset()` method sets hc_interrupt_enable to value 0"]
497impl crate::Resettable for HC_INTERRUPT_ENABLE_SPEC {
498    const RESET_VALUE: Self::Ux = 0;
499}
d1_pac/usb1/ohci_control_status_partition/hc_interrupt_enable.rs

d1_pac/usb1/ohci_control_status_partition/
hc_interrupt_enable.rs
